29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsyncfrom __future__ import print_function;

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync__copyright__ = \

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync__version__ = "$Revision$";

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsyncimport io;

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsyncimport os;

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsyncfrom optparse import OptionParser

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsyncimport random;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncimport sys;

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsyncRTEXITCODE_SUCCESS = 0;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncRTEXITCODE_SYNTAX = 2;

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsyncUINT8_MAX = 0xff

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsyncUINT16_MAX = 0xffff

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncUINT32_MAX = 0xffffffff

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncUINT64_MAX = 0xffffffffffffffff

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncdef RT_BIT_32(iBit): # pylint: disable=C0103

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ 32-bit one bit mask. """

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync return 1 << iBit;

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncdef RT_BIT_64(iBit): # pylint: disable=C0103

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync """ 64-bit one bit mask. """

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync return 1 << iBit;

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncX86_MODRM_RM_MASK = 0x07;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncX86_MODRM_REG_MASK = 0x38;

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsyncX86_MODRM_REG_SMASK = 0x07;

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncX86_MODRM_REG_SHIFT = 3;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncX86_MODRM_MOD_MASK = 0xc0;

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncX86_MODRM_MOD_SMASK = 0x03;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncX86_MODRM_MOD_SHIFT = 6;

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncX86_SIB_BASE_MASK = 0x07;

fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsyncX86_SIB_INDEX_MASK = 0x38;

fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsyncX86_SIB_INDEX_SMASK = 0x07;

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncX86_SIB_INDEX_SHIFT = 3;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncX86_SIB_SCALE_MASK = 0xc0;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncX86_SIB_SCALE_SMASK = 0x03;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncX86_SIB_SCALE_SHIFT = 6;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsyncX86_OP_PRF_CS = 0x2e;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncX86_OP_PRF_SS = 0x36;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncX86_OP_PRF_DS = 0x3e;

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncX86_OP_PRF_ES = 0x26;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncX86_OP_PRF_FS = 0x64;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncX86_OP_PRF_GS = 0x65;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncX86_OP_PRF_SIZE_OP = 0x66;

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncX86_OP_PRF_SIZE_ADDR = 0x67;

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncX86_OP_PRF_LOCK = 0xf0;

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncX86_OP_PRF_REPZ = 0xf2;

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncX86_OP_PRF_REPNZ = 0xf3;

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncX86_OP_REX_B = 0x41;

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncX86_OP_REX_X = 0x42;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncX86_OP_REX_R = 0x44;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncX86_OP_REX_W = 0x48;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncX86_GREG_xAX = 0

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncX86_GREG_xCX = 1

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncX86_GREG_xDX = 2

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncX86_GREG_xBX = 3

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncX86_GREG_xSP = 4

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncX86_GREG_xBP = 5

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncX86_GREG_xSI = 6

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncX86_GREG_xDI = 7

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncX86_GREG_x8 = 8

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncX86_GREG_x9 = 9

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncX86_GREG_x10 = 10

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncX86_GREG_x11 = 11

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncX86_GREG_x12 = 12

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncX86_GREG_x13 = 13

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncX86_GREG_x14 = 14

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncX86_GREG_x15 = 15

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncg_asGRegs64NoSp = ('rax', 'rcx', 'rdx', 'rbx', None, 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15');

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncg_asGRegs64 = ('rax', 'rcx', 'rdx', 'rbx', 'rsp', 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15');

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncg_asGRegs32NoSp = ('eax', 'ecx', 'edx', 'ebx', None, 'ebp', 'esi', 'edi',

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync 'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d');

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncg_asGRegs32 = ('eax', 'ecx', 'edx', 'ebx', 'esp', 'ebp', 'esi', 'edi',

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync 'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d');

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncg_asGRegs16NoSp = ('ax', 'cx', 'dx', 'bx', None, 'bp', 'si', 'di',

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync 'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w');

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncg_asGRegs16 = ('ax', 'cx', 'dx', 'bx', 'sp', 'bp', 'si', 'di',

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync 'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w');

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncg_asGRegs8 = ('al', 'cl', 'dl', 'bl', 'ah', 'ch', 'dh', 'bh');

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncg_asGRegs8Rex = ('al', 'cl', 'dl', 'bl', 'spl', 'bpl', 'sil', 'dil',

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync 'r8b', 'r9b', 'r10b', 'r11b', 'r12b', 'r13b', 'r14b', 'r15b',

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync 'ah', 'ch', 'dh', 'bh');

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncg_iMyRandSeed = int((os.urandom(4)).encode('hex'), 16);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncg_oMyRand = random.Random(g_iMyRandSeed);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncdef randU8():

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Unsigned 8-bit random number. """

f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync return g_oMyRand.getrandbits(8);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncdef randU16():

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Unsigned 16-bit random number. """

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return g_oMyRand.getrandbits(16);

f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncdef randU32():

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Unsigned 32-bit random number. """

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return g_oMyRand.getrandbits(32);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncdef randU64():

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync """ Unsigned 64-bit random number. """

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return g_oMyRand.getrandbits(64);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncdef randUxx(cBits):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Unsigned 8-, 16-, 32-, or 64-bit random number. """

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return g_oMyRand.getrandbits(cBits);

1969e98a26e5b56b67fbe3b6bfa007f8f09e86ebvboxsync

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsyncdef randSxx(cBits):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Signed 8-, 16-, 32-, or 64-bit random number. """

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uVal = randUxx(cBits);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync iRet = uVal & ((1 << (cBits - 1)) - 1);

0c94a8282c9042b02f022302a3d987746140eab9vboxsync if iRet != uVal:

0c94a8282c9042b02f022302a3d987746140eab9vboxsync iRet = -iRet;

0c94a8282c9042b02f022302a3d987746140eab9vboxsync return iRet;

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncdef randUxxList(cBits, cElements):

0c94a8282c9042b02f022302a3d987746140eab9vboxsync """ List of unsigned 8-, 16-, 32-, or 64-bit random numbers. """

0c94a8282c9042b02f022302a3d987746140eab9vboxsync return [randUxx(cBits) for _ in range(cElements)];

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncdef calcRexPrefixForTwoModRmRegs(iReg, iRm, bOtherRexPrefixes = 0):

0c94a8282c9042b02f022302a3d987746140eab9vboxsync """

0c94a8282c9042b02f022302a3d987746140eab9vboxsync bRex = bOtherRexPrefixes;

0c94a8282c9042b02f022302a3d987746140eab9vboxsync if iReg >= 8:

0c94a8282c9042b02f022302a3d987746140eab9vboxsync bRex |= X86_OP_REX_R;

0c94a8282c9042b02f022302a3d987746140eab9vboxsync if iRm >= 8:

0c94a8282c9042b02f022302a3d987746140eab9vboxsync bRex |= X86_OP_REX_B;

0c94a8282c9042b02f022302a3d987746140eab9vboxsync if bRex == 0:

0c94a8282c9042b02f022302a3d987746140eab9vboxsync return [];

0c94a8282c9042b02f022302a3d987746140eab9vboxsync return [bRex,];

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncdef calcModRmForTwoRegs(iReg, iRm):

0c94a8282c9042b02f022302a3d987746140eab9vboxsync """

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync bRm = (0x3 << X86_MODRM_MOD_SHIFT) \

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync | ((iReg << X86_MODRM_REG_SHIFT) & X86_MODRM_REG_MASK) \

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync | (iRm & X86_MODRM_RM_MASK);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return [bRm,];

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncdef convU32ToSigned(u32):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync """ Converts a 32-bit unsigned value to 32-bit signed. """

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if u32 < 0x80000000:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return u32;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return u32 - UINT32_MAX - 1;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncdef rotateLeftUxx(cBits, uVal, cShift):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Rotate a xx-bit wide unsigned number to the left. """

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync assert cShift < cBits;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if cBits == 16:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uMask = UINT16_MAX;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync elif cBits == 32:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uMask = UINT32_MAX;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync elif cBits == 64:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uMask = UINT64_MAX;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync else:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync assert cBits == 8;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uMask = UINT8_MAX;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uVal &= uMask;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uRet = (uVal << cShift) & uMask;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uRet |= (uVal >> (cBits - cShift));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return uRet;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncdef rotateRightUxx(cBits, uVal, cShift):

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync """ Rotate a xx-bit wide unsigned number to the right. """

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync assert cShift < cBits;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if cBits == 16:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uMask = UINT16_MAX;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync elif cBits == 32:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uMask = UINT32_MAX;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync elif cBits == 64:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uMask = UINT64_MAX;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync else:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync assert cBits == 8;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uMask = UINT8_MAX;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uVal &= uMask;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uRet = (uVal >> cShift);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uRet |= (uVal << (cBits - cShift)) & uMask;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return uRet;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncdef gregName(iReg, cBits, fRexByteRegs = True):

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync """ Gets the name of a general register by index and width. """

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if cBits == 64:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return g_asGRegs64[iReg];

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if cBits == 32:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return g_asGRegs32[iReg];

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if cBits == 16:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return g_asGRegs16[iReg];

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync assert cBits == 8;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if fRexByteRegs:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return g_asGRegs8Rex[iReg];

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return g_asGRegs8[iReg];

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncclass TargetEnv(object):

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync """

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ## @name CPU Modes

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ## @{

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ksCpuMode_Real = 'real';

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ksCpuMode_Protect = 'prot';

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ksCpuMode_Paged = 'paged';

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ksCpuMode_Long = 'long';

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ksCpuMode_V86 = 'v86';

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ## @}

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ## @name Instruction set.

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ## @{

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ksInstrSet_16 = '16';

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ksInstrSet_32 = '32';

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ksInstrSet_64 = '64';

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ## @}

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync def __init__(self, sName,

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync sInstrSet = ksInstrSet_32,

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync sCpuMode = ksCpuMode_Paged,

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync iRing = 3,

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.sName = sName;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.sInstrSet = sInstrSet;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.sCpuMode = sCpuMode;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.iRing = iRing;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync self.asGRegs = g_asGRegs64 if self.is64Bit() else g_asGRegs32;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync self.asGRegsNoSp = g_asGRegs64NoSp if self.is64Bit() else g_asGRegs32NoSp;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync def isUsingIprt(self):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Whether it's an IPRT environment or not. """

29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync return self.sName.startswith('iprt');

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync def is64Bit(self):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Whether it's a 64-bit environment or not. """

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return self.sInstrSet == self.ksInstrSet_64;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync def getDefOpBits(self):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Get the default operand size as a bit count. """

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if self.sInstrSet == self.ksInstrSet_16:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return 16;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return 32;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync def getDefOpBytes(self):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Get the default operand size as a byte count. """

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return self.getDefOpBits() / 8;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync def getMaxOpBits(self):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Get the max operand size as a bit count. """

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if self.sInstrSet == self.ksInstrSet_64:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return 64;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return 32;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync def getMaxOpBytes(self):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Get the max operand size as a byte count. """

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return self.getMaxOpBits() / 8;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync def getDefAddrBits(self):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Get the default address size as a bit count. """

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if self.sInstrSet == self.ksInstrSet_16:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return 16;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if self.sInstrSet == self.ksInstrSet_32:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return 32;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return 64;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync def getDefAddrBytes(self):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync """ Get the default address size as a byte count. """

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return self.getDefAddrBits() / 8;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync def getGRegCount(self, cbEffBytes = 4):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync """ Get the number of general registers. """

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if self.sInstrSet == self.ksInstrSet_64:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if cbEffBytes == 1:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return 16 + 4;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return 16;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return 8;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync def randGRegNoSp(self, cbEffBytes = 4):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync """ Returns a random general register number, excluding the SP register. """

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync iReg = randU16() % self.getGRegCount(cbEffBytes);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync while iReg == X86_GREG_xSP:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync iReg = randU16() % self.getGRegCount(cbEffBytes);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return iReg;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync def randGRegNoSpList(self, cItems, cbEffBytes = 4):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync """ List of randGRegNoSp values. """

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync aiRegs = [];

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync for _ in range(cItems):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync aiRegs.append(self.randGRegNoSp(cbEffBytes));

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return aiRegs;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync def getAddrModes(self):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync """ Gets a list of addressing mode (16, 32, or/and 64). """

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if self.sInstrSet == self.ksInstrSet_16:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return [16, 32];

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if self.sInstrSet == self.ksInstrSet_32:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return [32, 16];

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return [64, 32];

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync def is8BitHighGReg(self, cbEffOp, iGReg):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync """ Checks if the given register is a high 8-bit general register (AH, CH, DH or BH). """

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync assert cbEffOp in [1, 2, 4, 8];

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if cbEffOp == 1:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if iGReg >= 16:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return True;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if iGReg >= 4 and not self.is64Bit():

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return True;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return False;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

0c94a8282c9042b02f022302a3d987746140eab9vboxsyncg_dTargetEnvs = {

0c94a8282c9042b02f022302a3d987746140eab9vboxsync 'iprt-r3-32': TargetEnv('iprt-r3-32', TargetEnv.ksInstrSet_32, TargetEnv.ksCpuMode_Protect, 3),

0c94a8282c9042b02f022302a3d987746140eab9vboxsync 'iprt-r3-64': TargetEnv('iprt-r3-64', TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long, 3),

0c94a8282c9042b02f022302a3d987746140eab9vboxsync 'bs2-r0-64': TargetEnv('bs2-r0-64', TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long, 0),

0c94a8282c9042b02f022302a3d987746140eab9vboxsync};

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsyncclass InstrTestBase(object):

0c94a8282c9042b02f022302a3d987746140eab9vboxsync """

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

0c94a8282c9042b02f022302a3d987746140eab9vboxsync def __init__(self, sName, sInstr = None):

0c94a8282c9042b02f022302a3d987746140eab9vboxsync self.sName = sName;

0c94a8282c9042b02f022302a3d987746140eab9vboxsync self.sInstr = sInstr if sInstr else sName.split()[0];

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync def isApplicable(self, oGen):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync """

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync _ = oGen;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return True;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync def generateTest(self, oGen, sTestFnName):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.write(';; @todo not implemented. This is for the linter: %s, %s\n' % (oGen, sTestFnName));

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return True;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync def generateInputs(self, cbEffOp, cbMaxOp, oGen, fLong = False):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Generate a list of inputs. """

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if fLong:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync #

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync # Try do extremes as well as different ranges of random numbers.

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync #

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync auRet = [0, 1, ];

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if cbMaxOp >= 1:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync auRet += [ UINT8_MAX / 2, UINT8_MAX / 2 + 1, UINT8_MAX ];

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if cbMaxOp >= 2:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync auRet += [ UINT16_MAX / 2, UINT16_MAX / 2 + 1, UINT16_MAX ];

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if cbMaxOp >= 4:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync auRet += [ UINT32_MAX / 2, UINT32_MAX / 2 + 1, UINT32_MAX ];

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if cbMaxOp >= 8:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync auRet += [ UINT64_MAX / 2, UINT64_MAX / 2 + 1, UINT64_MAX ];

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:

f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync for cBits, cValues in ( (8, 4), (16, 4), (32, 8), (64, 8) ):

f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync if cBits < cbMaxOp * 8:

f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync auRet += randUxxList(cBits, cValues);

f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync cWanted = 16;

f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync for cBits, cValues in ( (8, 8), (16, 8), (24, 2), (32, 16), (40, 1), (48, 1), (56, 1), (64, 16) ):

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if cBits < cbMaxOp * 8:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync auRet += randUxxList(cBits, cValues);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync cWanted = 64;

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync else:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync for cBits, cValues in ( (8, 16), (16, 16), (24, 4), (32, 64), (40, 4), (48, 4), (56, 4), (64, 64) ):

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if cBits < cbMaxOp * 8:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync auRet += randUxxList(cBits, cValues);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync cWanted = 168;

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync if len(auRet) < cWanted:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync auRet += randUxxList(cbEffOp * 8, cWanted - len(auRet));

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync else:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync #

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync # Short list, just do some random numbers.

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync #

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync auRet = [];

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync auRet += randUxxList(cbMaxOp, 1);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync auRet += randUxxList(cbMaxOp, 2);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync else:

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync auRet = [];

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync for cBits in (8, 16, 32, 64):

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync if cBits < cbMaxOp * 8:

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync auRet += randUxxList(cBits, 1);

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync return auRet;

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsyncclass InstrTest_MemOrGreg_2_Greg(InstrTestBase):

f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync """

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync def __init__(self, sName, fnCalcResult, sInstr = None, acbOpVars = None):

f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync InstrTestBase.__init__(self, sName, sInstr);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync self.fnCalcResult = fnCalcResult;

f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync self.acbOpVars = [ 1, 2, 4, 8 ] if not acbOpVars else list(acbOpVars);

f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync ## @name Test Instruction Writers

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync ## @{

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen):

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync """ Writes the instruction with two general registers as operands. """

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync fRexByteRegs = oGen.oTarget.is64Bit();

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.write(' %s %s, %s\n'

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync % (self.sInstr, gregName(iOp1, cbEffOp * 8, fRexByteRegs), gregName(iOp2, cbEffOp * 8, fRexByteRegs),));

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync return True;

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync def writeInstrGregPureRM(self, cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen):

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync """ Writes the instruction with two general registers as operands. """

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync oGen.write(' ');

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync if iOp2 == 13 and iMod == 0 and cAddrBits == 64:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync oGen.write('altrexb '); # Alternative encoding for rip relative addressing.

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync if cbEffOp == 8:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync oGen.write('%s %s, [' % (self.sInstr, g_asGRegs64[iOp1],));

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync elif cbEffOp == 4:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync oGen.write('%s %s, [' % (self.sInstr, g_asGRegs32[iOp1],));

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync elif cbEffOp == 2:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync oGen.write('%s %s, [' % (self.sInstr, g_asGRegs16[iOp1],));

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync elif cbEffOp == 1:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync oGen.write('%s %s, [' % (self.sInstr, g_asGRegs8Rex[iOp1],));

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync else:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync assert False;

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if (iOp2 == 5 or iOp2 == 13) and iMod == 0:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write('VBINSTST_NAME(g_u%sData)' % (cbEffOp * 8,))

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if oGen.oTarget.is64Bit():

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(' wrt rip');

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync else:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync if iMod == 1:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.write('byte %d + ' % (offDisp,));

0c94a8282c9042b02f022302a3d987746140eab9vboxsync elif iMod == 2:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write('dword %d + ' % (offDisp,));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync else:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync assert iMod == 0;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if cAddrBits == 64:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(g_asGRegs64[iOp2]);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync elif cAddrBits == 32:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(g_asGRegs32[iOp2]);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync elif cAddrBits == 16:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync assert False; ## @todo implement 16-bit addressing.

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync else:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync assert False, str(cAddrBits);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.write(']\n');

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return True;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync def writeInstrGregSibLabel(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync """ Writes the instruction taking a register and a label (base only w/o reg), SIB form. """

fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync assert offDisp is None; assert iBaseReg in [5, 13]; assert iIndexReg == 4; assert cAddrBits != 16;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if cAddrBits == 64:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync # Note! Cannot test this in 64-bit mode in any sensible way because the disp is 32-bit

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync # and we cannot (yet) make assumtions about where we're loaded.

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync ## @todo Enable testing this in environments where we can make assumptions (boot sector).

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.write(' %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP]\n'

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync % ( self.sInstr, gregName(iOp1, cbEffOp * 8), cbEffOp * 8,));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync else:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(' altsibx%u %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP]\n'

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync % ( iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), cbEffOp * 8,));

0c94a8282c9042b02f022302a3d987746140eab9vboxsync return True;

0c94a8282c9042b02f022302a3d987746140eab9vboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync def writeInstrGregSibScaledReg(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):

0c94a8282c9042b02f022302a3d987746140eab9vboxsync """ Writes the instruction taking a register and disp+scaled register (no base reg), SIB form. """

0c94a8282c9042b02f022302a3d987746140eab9vboxsync assert iBaseReg in [5, 13]; assert iIndexReg != 4; assert cAddrBits != 16;

0c94a8282c9042b02f022302a3d987746140eab9vboxsync # Note! Using altsibxN to force scaled encoding. This is only really a

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync # necessity for iScale=1, but doesn't hurt for the rest.

0c94a8282c9042b02f022302a3d987746140eab9vboxsync oGen.write(' altsibx%u %s %s, [%s * %#x'

0c94a8282c9042b02f022302a3d987746140eab9vboxsync % (iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), gregName(iIndexReg, cAddrBits), iScale,));

0c94a8282c9042b02f022302a3d987746140eab9vboxsync if offDisp is not None:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync oGen.write(' + %#x' % (offDisp,));

0c94a8282c9042b02f022302a3d987746140eab9vboxsync oGen.write(']\n');

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync _ = iBaseReg;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return True;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync def writeInstrGregSibBase(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync """ Writes the instruction taking a register and base only (with reg), SIB form. """

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.write(' altsibx%u %s %s, [%s'

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync % (iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), gregName(iBaseReg, cAddrBits),));

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if offDisp is not None:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync oGen.write(' + %#x' % (offDisp,));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(']\n');

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync _ = iIndexReg;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return True;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync def writeInstrGregSibBaseAndScaledReg(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync """ Writes tinstruction taking a register and full featured SIB form address. """

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync # Note! From the looks of things, yasm will encode the following instructions the same way:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync # mov eax, [rsi*1 + rbx]

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync # mov eax, [rbx + rsi*1]

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync # So, when there are two registers involved, the '*1' selects

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync # which is index and which is base.

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(' %s %s, [%s + %s * %u'

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync % ( self.sInstr, gregName(iOp1, cbEffOp * 8),

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync gregName(iBaseReg, cAddrBits), gregName(iIndexReg, cAddrBits), iScale,));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if offDisp is not None:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(' + %#x' % (offDisp,));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(']\n');

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return True;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ## @}

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ## @name Memory setups

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ## @{

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync def generateMemSetupReadByLabel(self, oGen, cbEffOp, uInput):

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync """ Sets up memory for a memory read. """

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.pushConst(uInput);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return True;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync def generateMemSetupReadByReg(self, oGen, cAddrBits, cbEffOp, iReg1, uInput, offDisp = None):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync """ Sets up memory for a memory read indirectly addressed thru one register and optional displacement. """

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.pushConst(uInput);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(' call VBINSTST_NAME(%s)\n'

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iBaseReg = iReg1, offDisp = offDisp),));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iReg1],));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return True;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync def generateMemSetupReadByScaledReg(self, oGen, cAddrBits, cbEffOp, iIndexReg, iScale, uInput, offDisp = None):

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync """ Sets up memory for a memory read indirectly addressed thru one register and optional displacement. """

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.pushConst(uInput);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(' call VBINSTST_NAME(%s)\n'

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, offDisp = offDisp, iIndexReg = iIndexReg, iScale = iScale),));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iIndexReg],));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return True;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync def generateMemSetupReadByBaseAndScaledReg(self, oGen, cAddrBits, cbEffOp, iBaseReg, iIndexReg, iScale, uInput, offDisp):

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync """ Sets up memory for a memory read indirectly addressed thru two registers with optional displacement. """

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.pushConst(uInput);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(' call VBINSTST_NAME(%s)\n'

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iBaseReg = iBaseReg, offDisp = offDisp,

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync iIndexReg = iIndexReg, iScale = iScale),));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iIndexReg],));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iBaseReg],));

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return True;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync def generateMemSetupPureRM(self, oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp = None):

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync """ Sets up memory for a pure R/M addressed read, iOp2 being the R/M value. """

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.pushConst(uInput);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync assert offDisp is None or iMod != 0;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (iOp2 != 5 and iOp2 != 13) or iMod != 0:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.write(' call VBINSTST_NAME(%s)\n'

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iOp2, offDisp),));

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync else:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,));

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return True;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync ## @}

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync def generateOneStdTestGregGreg(self, oGen, cbEffOp, cbMaxOp, iOp1, iOp1X, iOp2, iOp2X, uInput, uResult):

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync """ Generate one standard instr greg,greg test. """

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2X], uInput,));

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if iOp1X != iOp2X:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2X],));

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync self.writeInstrGregGreg(cbEffOp, iOp1, iOp2, oGen);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.pushConst(uResult);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1X, iOp2X if iOp1X != iOp2X else None),));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync _ = cbMaxOp;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return True;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync def generateOneStdTestGregGreg8BitHighPain(self, oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput):

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync """ High 8-bit registers are a real pain! """

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync assert oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) or oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2);

fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync # Figure out the register indexes of the max op sized regs involved.

fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync iOp1X = iOp1 & 3;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync iOp2X = iOp2 & 3;

fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync oGen.write(' ; iOp1=%u iOp1X=%u iOp2=%u iOp2X=%u\n' % (iOp1, iOp1X, iOp2, iOp2X,));

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync # Calculate unshifted result.

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if iOp1X != iOp2X:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync uCur = oGen.auRegValues[iOp1X];

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync uCur = rotateRightUxx(cbMaxOp * 8, uCur, 8);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync else:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync uCur = uInput;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) != oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2):

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1):

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uCur = rotateRightUxx(cbMaxOp * 8, uCur, 8);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync else:

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uCur = rotateLeftUxx(cbMaxOp * 8, uCur, 8);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uResult = self.fnCalcResult(cbEffOp, uInput, uCur, oGen);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync # Rotate the input and/or result to match their max-op-sized registers.

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync uInput = rotateLeftUxx(cbMaxOp * 8, uInput, 8);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1):

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uResult = rotateLeftUxx(cbMaxOp * 8, uResult, 8);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync # Hand it over to an overridable worker method.

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync return self.generateOneStdTestGregGreg(oGen, cbEffOp, cbMaxOp, iOp1, iOp1X, iOp2, iOp2X, uInput, uResult);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync def generateOneStdTestGregMemNoSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iOp2, uInput, uResult):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync """ Generate mode 0, 1 and 2 test for the R/M=iOp2. """

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if cAddrBits == 16:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync _ = cbMaxOp;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync else:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync iMod = 0; # No disp, except for i=5.

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, None, oGen);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.pushConst(uResult);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if iOp2 != 5 and iOp2 != 13:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync iMod = 1;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync for offDisp in oGen.getDispForMod(iMod):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync oGen.pushConst(uResult);

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync iMod = 2;

19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync for offDisp in oGen.getDispForMod(iMod):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.pushConst(uResult);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

9c9db71d639cf066ed41d49629d46d48bff4be2fvboxsync return True;

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync def generateOneStdTestGregMemSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iMod, # pylint: disable=R0913

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync iBaseReg, iIndexReg, iScale, uInput, uResult):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync """ Generate one SIB variations. """

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync for offDisp in oGen.getDispForMod(iMod, cbEffOp):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if ((iBaseReg == 5 or iBaseReg == 13) and iMod == 0):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if iIndexReg == 4:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if cAddrBits == 64:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync continue; # skipping.

fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.generateMemSetupReadByLabel(oGen, cbEffOp, uInput);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.writeInstrGregSibLabel(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync sChecker = oGen.needGRegChecker(iOp1);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync else:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.generateMemSetupReadByScaledReg(oGen, cAddrBits, cbEffOp, iIndexReg, iScale, uInput, offDisp);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.writeInstrGregSibScaledReg(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync sChecker = oGen.needGRegChecker(iOp1, iIndexReg);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync else:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if iIndexReg == 4:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.generateMemSetupReadByReg(oGen, cAddrBits, cbEffOp, iBaseReg, uInput, offDisp);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.writeInstrGregSibBase(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync sChecker = oGen.needGRegChecker(iOp1, iBaseReg);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync else:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if iIndexReg == iBaseReg and iScale == 1 and offDisp is not None and (offDisp & 1):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if offDisp < 0: offDisp += 1;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync else: offDisp -= 1;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.generateMemSetupReadByBaseAndScaledReg(oGen, cAddrBits, cbEffOp, iBaseReg,

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync iIndexReg, iScale, uInput, offDisp);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.writeInstrGregSibBaseAndScaledReg(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync sChecker = oGen.needGRegChecker(iOp1, iBaseReg, iIndexReg);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.pushConst(uResult);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.write(' call VBINSTST_NAME(%s)\n' % (sChecker,));

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync _ = cbMaxOp;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return True;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync def generateStdTestGregMemSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, auInputs):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync """ Generate all SIB variations for the given iOp1 (reg) value. """

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync assert cAddrBits in [32, 64];

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync i = oGen.cSibBasePerRun;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync while i > 0:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync oGen.iSibBaseReg = (oGen.iSibBaseReg + 1) % oGen.oTarget.getGRegCount(cAddrBits / 8);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if oGen.iSibBaseReg == X86_GREG_xSP: # no RSP testing atm.

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync continue;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync j = oGen.getSibIndexPerRun();

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync while j > 0:

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync oGen.iSibIndexReg = (oGen.iSibIndexReg + 1) % oGen.oTarget.getGRegCount(cAddrBits / 8);

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync if oGen.iSibIndexReg == iOp1 and oGen.iSibIndexReg != 4 and cAddrBits != cbMaxOp:

9c9db71d639cf066ed41d49629d46d48bff4be2fvboxsync continue; # Don't know the high bit of the address ending up the result - skip it for now.

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync for iMod in [0, 1, 2]:

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if oGen.iSibBaseReg == iOp1 \

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync and ((oGen.iSibBaseReg != 5 and oGen.iSibBaseReg != 13) or iMod != 0) \

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync and cAddrBits != cbMaxOp:

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync continue; # Don't know the high bit of the address ending up the result - skip it for now.

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync for _ in oGen.oSibScaleRange:

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync oGen.iSibScale *= 2;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if oGen.iSibScale > 8:

9c9db71d639cf066ed41d49629d46d48bff4be2fvboxsync oGen.iSibScale = 1;

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync for uInput in auInputs:

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync oGen.newSubTest();

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[iOp1], oGen);

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync self.generateOneStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iMod,

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync oGen.iSibBaseReg, oGen.iSibIndexReg, oGen.iSibScale,

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync uInput, uResult);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync j -= 1;

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync i -= 1;

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync return True;

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync def generateStandardTests(self, oGen):

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync """ Generate standard tests. """

44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync # Parameters.

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync cbDefOp = oGen.oTarget.getDefOpBytes();

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync cbMaxOp = oGen.oTarget.getMaxOpBytes();

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync auShortInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync auLongInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen, fLong = True);

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync iLongOp1 = oGen.oTarget.randGRegNoSp();

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync iLongOp2 = oGen.oTarget.randGRegNoSp();

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync # Register tests

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if True:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync for cbEffOp in self.acbOpVars:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if cbEffOp > cbMaxOp:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync continue;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync oOp2Range = range(oGen.oTarget.getGRegCount(cbEffOp));

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync oOp2Range = [iLongOp2,];

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.write('; cbEffOp=%u\n' % (cbEffOp,));

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync for iOp1 in range(oGen.oTarget.getGRegCount(cbEffOp)):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if iOp1 == X86_GREG_xSP:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync continue; # Cannot test xSP atm.

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync for iOp2 in oOp2Range:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if (iOp2 >= 16 and iOp1 in range(4, 16)) \

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync or (iOp1 >= 16 and iOp2 in range(4, 16)):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync continue; # Any REX encoding turns AH,CH,DH,BH regs into SPL,BPL,SIL,DIL.

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if iOp2 == X86_GREG_xSP:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync continue; # Cannot test xSP atm.

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync oGen.write('; iOp2=%u cbEffOp=%u\n' % (iOp2, cbEffOp));

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync for uInput in (auLongInputs if iOp1 == iLongOp1 and iOp2 == iLongOp2 else auShortInputs):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync oGen.newSubTest();

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if not oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) and not oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync uCur = oGen.auRegValues[iOp1 & 15] if iOp1 != iOp2 else uInput;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync uResult = self.fnCalcResult(cbEffOp, uInput, uCur, oGen);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync self.generateOneStdTestGregGreg(oGen, cbEffOp, cbMaxOp, iOp1, iOp1 & 15, iOp2, iOp2 & 15,

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync uInput, uResult);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync else:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync self.generateOneStdTestGregGreg8BitHighPain(oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync # Memory test.

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if True:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync for cAddrBits in oGen.oTarget.getAddrModes():

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync for cbEffOp in self.acbOpVars:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if cbEffOp > cbMaxOp:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync continue;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync for _ in oGen.getModRegRange(cbEffOp):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.iModReg = (oGen.iModReg + 1) % oGen.oTarget.getGRegCount(cbEffOp);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if oGen.iModReg == X86_GREG_xSP:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync continue; # Cannot test xSP atm.

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if oGen.iModReg > 15:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync continue; ## TODO AH,CH,DH,BH

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync auInputs = auLongInputs if oGen.iModReg == iLongOp1 else auShortInputs;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync for _ in oGen.oModRmRange:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.iModRm = (oGen.iModRm + 1) % oGen.oTarget.getGRegCount(cAddrBits * 8);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if oGen.iModRm != 4 or cAddrBits == 16:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync for uInput in auInputs:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.newSubTest();

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if oGen.iModReg == oGen.iModRm and oGen.iModRm != 5 \

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync and oGen.iModRm != 13 and cbEffOp != cbMaxOp:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync continue; # Don't know the high bit of the address ending up the result - skip it for now.

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[oGen.iModReg & 15], oGen);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync self.generateOneStdTestGregMemNoSib(oGen, cAddrBits, cbEffOp, cbMaxOp,

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.iModReg, oGen.iModRm, uInput, uResult);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync else:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync # SIB - currently only short list of inputs or things may get seriously out of hand.

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync self.generateStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, oGen.iModReg, auShortInputs);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync #break;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync #break;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return True;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync def generateTest(self, oGen, sTestFnName):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.write('VBINSTST_BEGINPROC %s\n' % (sTestFnName,));

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync #oGen.write(' int3\n');

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync self.generateStandardTests(oGen);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync #oGen.write(' int3\n');

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.write(' ret\n');

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.write('VBINSTST_ENDPROC %s\n' % (sTestFnName,));

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return True;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncclass InstrTest_Mov_Gv_Ev(InstrTest_MemOrGreg_2_Greg):

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync """

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync def __init__(self):

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync InstrTest_MemOrGreg_2_Greg.__init__(self, 'mov Gv,Ev', self.calc_mov);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync @staticmethod

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync def calc_mov(cbEffOp, uInput, uCur, oGen):

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync """ Calculates the result of a mov instruction."""

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync if cbEffOp == 8:

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync return uInput & UINT64_MAX;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if cbEffOp == 4:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return uInput & UINT32_MAX;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if cbEffOp == 2:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return (uCur & 0xffffffffffff0000) | (uInput & UINT16_MAX);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync assert cbEffOp == 1; _ = oGen;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return (uCur & 0xffffffffffffff00) | (uInput & UINT8_MAX);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncclass InstrTest_MovSxD_Gv_Ev(InstrTest_MemOrGreg_2_Greg):

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync """

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync def __init__(self):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync InstrTest_MemOrGreg_2_Greg.__init__(self, 'movsxd Gv,Ev', self.calc_movsxd, acbOpVars = [ 8, 4, 2, ]);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if cbEffOp == 8:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs64[iOp1], g_asGRegs32[iOp2]));

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync elif cbEffOp == 4 or cbEffOp == 2:

fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync abInstr = [];

fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync if cbEffOp != oGen.oTarget.getDefOpBytes():

fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync abInstr.append(X86_OP_PRF_SIZE_OP);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync abInstr += calcRexPrefixForTwoModRmRegs(iOp1, iOp2);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync abInstr.append(0x63);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync abInstr += calcModRmForTwoRegs(iOp1, iOp2);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync oGen.writeInstrBytes(abInstr);

fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync else:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync assert False;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync assert False;

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync return True;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync def isApplicable(self, oGen):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return oGen.oTarget.is64Bit();

fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync @staticmethod

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync def calc_movsxd(cbEffOp, uInput, uCur, oGen):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync """

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync _ = oGen;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if cbEffOp == 8 and (uInput & RT_BIT_32(31)):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return (UINT32_MAX << 32) | (uInput & UINT32_MAX);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if cbEffOp == 2:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return (uCur & 0xffffffffffff0000) | (uInput & 0xffff);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync return uInput & UINT32_MAX;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncclass InstrTest_DivIDiv(InstrTestBase):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync """

fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync def __init__(self, fIsIDiv):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if not fIsIDiv:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync InstrTestBase.__init__(self, 'div Gv,Ev', 'div');

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync else:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync InstrTestBase.__init__(self, 'idiv Gv,Ev', 'idiv');

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync self.fIsIDiv = fIsIDiv;

e70bda5438c3582164d26f171a8bc8d3d7da1e12vboxsync

e70bda5438c3582164d26f171a8bc8d3d7da1e12vboxsync def generateInputsNoXcpt(self, cbEffOp, fLong = False):

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync """ Generate inputs for cbEffOp. Returns a list of pairs, dividen + divisor. """

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync # Test params.

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync uStep = 1 << (cbEffOp * 8);

f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync if self.fIsIDiv:

f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync uStep /= 2;

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync # edge tests

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync auRet = [];

c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync

e70bda5438c3582164d26f171a8bc8d3d7da1e12vboxsync uDivisor = 1 if fLong else 3;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync uDividend = uStep * uDivisor - 1;

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync for i in range(5 if fLong else 3):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync auRet.append([uDividend, uDivisor]);

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if self.fIsIDiv:

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync auRet.append([-uDividend, -uDivisor]);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync auRet.append([-(uDividend + uDivisor - 1), uDivisor]);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync auRet.append([ (uDividend + uDivisor - 1), -uDivisor]);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync if i <= 3 and fLong:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync auRet.append([uDividend - 1, uDivisor]);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync if self.fIsIDiv:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync auRet.append([-(uDividend - 1), -uDivisor]);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync uDivisor += 1;

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync uDividend += uStep;

fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync uDivisor = uStep - 1;

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync uDividend = uStep * uDivisor - 1;

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync for _ in range(3 if fLong else 1):

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync auRet.append([uDividend, uDivisor]);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync if self.fIsIDiv:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync auRet.append([-uDividend, -uDivisor]);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync uDivisor -= 1;

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync uDividend -= uStep;

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync if self.fIsIDiv:

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync uDivisor = -uStep;

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync for _ in range(3 if fLong else 1):

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync auRet.append([uDivisor * (uDivisor - 1) - 1, uDivisor]);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync uDivisor += 1

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync uDivisor = uStep - 1;

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync for _ in range(3 if fLong else 1):

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync auRet.append([-(uDivisor * (uDivisor + 1) - 1), uDivisor]);

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync uDivisor -= 1

661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync # random tests.

66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if self.fIsIDiv:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync for _ in range(6 if fLong else 2):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync while True:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uDivisor = randSxx(cbEffOp * 4);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if uDivisor == 0 or uDivisor >= uStep or uDivisor < -uStep:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync continue;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uDividend = randSxx(cbEffOp * 8);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uResult = uDividend / uDivisor;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if uResult >= uStep or uResult <= -uStep: # exclude difficulties

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync continue;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync break;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync auRet.append([uDividend, uDivisor]);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync else:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync for _ in range(6 if fLong else 2):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync while True:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uDivisor = randUxx(cbEffOp * 4);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if uDivisor == 0 or uDivisor >= uStep:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync continue;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uDividend = randUxx(cbEffOp * 8);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uResult = uDividend / uDivisor;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if uResult >= uStep:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync continue;

5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync break;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync auRet.append([uDividend, uDivisor]);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return auRet;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync def generateOneStdTestGreg(self, oGen, cbEffOp, iOp2, iDividend, iDivisor):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Generate code of one '[I]DIV rDX:rAX,<GREG>' test. """

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync cbMaxOp = oGen.oTarget.getMaxOpBytes();

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync fEffOp = ((1 << (cbEffOp *8) ) - 1);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync fMaxOp = UINT64_MAX if cbMaxOp == 8 else UINT32_MAX; assert cbMaxOp in [8, 4];

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync fTopOp = fMaxOp - fEffOp;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync fFullOp1 = ((1 << (cbEffOp*16)) - 1);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uAX = iDividend & fFullOp1; # full with unsigned

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uDX = uAX >> (cbEffOp*8);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uAX &= fEffOp;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uOp2Val = iDivisor & fEffOp;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync iQuotient = iDividend / iDivisor;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync iReminder = iDividend % iDivisor;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if iReminder != 0 and iQuotient < 0: # python has different rounding rules for negative division.

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync iQuotient += 1;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync iReminder -= iDivisor;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uAXResult = iQuotient & fEffOp;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uDXResult = iReminder & fEffOp;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if cbEffOp < cbMaxOp:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uAX |= randUxx(cbMaxOp * 8) & fTopOp;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uDX |= randUxx(cbMaxOp * 8) & fTopOp;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uOp2Val |= randUxx(cbMaxOp * 8) & fTopOp;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if cbEffOp < 4:

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uAXResult |= uAX & fTopOp;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uDXResult |= uDX & fTopOp;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync oGen.write(' ; iDividend=%#x (%d) iDivisor=%#x (%d)\n'

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ' ; iQuotient=%#x (%d) iReminder=%#x (%d)\n'

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync % ( iDividend & fFullOp1, iDividend, iDivisor & fEffOp, iDivisor,

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync iQuotient & fEffOp, iQuotient, iReminder & fEffOp, iReminder, ));

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xDX], uDX,));

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xAX], uAX,));

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2], uOp2Val,));

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

8f7ee9e453c60b3b699799538a45950b35266665vboxsync oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],));

8f7ee9e453c60b3b699799538a45950b35266665vboxsync oGen.pushConst(uDXResult);

8f7ee9e453c60b3b699799538a45950b35266665vboxsync oGen.pushConst(uAXResult);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync oGen.write(' %-4s %s\n' % (self.sInstr, gregName(iOp2, cbEffOp * 8),));

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(X86_GREG_xAX, X86_GREG_xDX, iOp2),));

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return True;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync def generateOneStdTestGreg8Bit(self, oGen, cbEffOp, iOp2, iDividend, iDivisor):

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync """ Generate code of one '[I]DIV AX,<GREG>' test (8-bit). """

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync cbMaxOp = oGen.oTarget.getMaxOpBytes();

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync fMaxOp = UINT64_MAX if cbMaxOp == 8 else UINT32_MAX; assert cbMaxOp in [8, 4];

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync iOp2X = (iOp2 & 3) if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2) else iOp2;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync assert iOp2X != X86_GREG_xAX;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uAX = iDividend & UINT16_MAX; # full with unsigned

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uOp2Val = iDivisor & UINT8_MAX;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync iQuotient = iDividend / iDivisor;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync iReminder = iDividend % iDivisor;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if iReminder != 0 and iQuotient < 0: # python has different rounding rules for negative division.

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync iQuotient += 1;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync iReminder -= iDivisor;

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uAXResult = (iQuotient & UINT8_MAX) | ((iReminder & UINT8_MAX) << 8);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uAX |= randUxx(cbMaxOp * 8) & (fMaxOp - UINT16_MAX);

0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uAXResult |= uAX & (fMaxOp - UINT16_MAX);

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync uOp2Val |= randUxx(cbMaxOp * 8) & (fMaxOp - UINT8_MAX);

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if iOp2X != iOp2:

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync uOp2Val = rotateLeftUxx(cbMaxOp * 8, uOp2Val, 8);

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync oGen.write(' ; iDividend=%#x (%d) iDivisor=%#x (%d)\n'

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync ' ; iQuotient=%#x (%d) iReminder=%#x (%d)\n'

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync % ( iDividend & UINT16_MAX, iDividend, iDivisor & UINT8_MAX, iDivisor,

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync iQuotient & UINT8_MAX, iQuotient, iReminder & UINT8_MAX, iReminder, ));

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xAX], uAX,));

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2X], uOp2Val,));

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2X],));

8f7ee9e453c60b3b699799538a45950b35266665vboxsync oGen.pushConst(uAXResult);

8f7ee9e453c60b3b699799538a45950b35266665vboxsync

8f7ee9e453c60b3b699799538a45950b35266665vboxsync oGen.write(' %-4s %s\n' % (self.sInstr, gregName(iOp2, cbEffOp * 8),));

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(X86_GREG_xAX, iOp2X),));

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync return;

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync def generateStandardTests(self, oGen):

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync """ Generates test that causes no exceptions. """

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync

38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync # Parameters.

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync iLongOp2 = oGen.oTarget.randGRegNoSp();

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync # Register tests

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if True:

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync for cbEffOp in ( 8, 4, 2, 1 ):

88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if cbEffOp > oGen.oTarget.getMaxOpBytes():