SELMInline.h revision a2c0b38648fa3620ea46f884eb614abbf00c6759
/* $Id$ */
/** @file
* SELM - Internal header file.
*/
/*
* Copyright (C) 2006-2012 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
#ifndef ___SELMInline_h
#define ___SELMInline_h
#ifdef VBOX_WITH_RAW_MODE_NOT_R0
/**
* Checks if a shadow descriptor table entry is good for the given segment
* register.
*
* @returns @c true if good, @c false if not.
* @param pSReg The segment register.
* @param pShwDesc The shadow descriptor table entry.
* @param iSReg The segment register index (X86_SREG_XXX).
* @param uCpl The CPL.
*/
DECLINLINE(bool) selmIsShwDescGoodForSReg(PCCPUMSELREG pSReg, PCX86DESC pShwDesc, uint32_t iSReg, uint32_t uCpl)
{
/*
* See iemMiscValidateNewSS, iemCImpl_LoadSReg and intel+amd manuals.
*/
{
Log(("selmIsShwDescGoodForSReg: Not present\n"));
return false;
}
{
Log(("selmIsShwDescGoodForSReg: System descriptor\n"));
return false;
}
if (iSReg == X86_SREG_SS)
{
{
Log(("selmIsShwDescGoodForSReg: Stack must be writable\n"));
return false;
}
{
Log(("selmIsShwDescGoodForSReg: CPL(%d) > DPL(%d)\n", uCpl, pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available));
return false;
}
}
else
{
if (iSReg == X86_SREG_CS)
{
{
Log(("selmIsShwDescGoodForSReg: CS needs code segment\n"));
return false;
}
}
{
return false;
}
{
return false;
}
}
return true;
}
/**
* Checks if a guest descriptor table entry is good for the given segment
* register.
*
* @returns @c true if good, @c false if not.
* @param pVCpu The current virtual CPU.
* @param pSReg The segment register.
* @param pGstDesc The guest descriptor table entry.
* @param iSReg The segment register index (X86_SREG_XXX).
* @param uCpl The CPL.
*/
DECLINLINE(bool) selmIsGstDescGoodForSReg(PVMCPU pVCpu, PCCPUMSELREG pSReg, PCX86DESC pGstDesc, uint32_t iSReg, uint32_t uCpl)
{
/*
* See iemMiscValidateNewSS, iemCImpl_LoadSReg and intel+amd manuals.
*/
{
Log(("selmIsGstDescGoodForSReg: Not present\n"));
return false;
}
{
Log(("selmIsGstDescGoodForSReg: System descriptor\n"));
return false;
}
if (iSReg == X86_SREG_SS)
{
{
Log(("selmIsGstDescGoodForSReg: Stack must be writable\n"));
return false;
}
{
return false;
}
}
else
{
if (iSReg == X86_SREG_CS)
{
{
Log(("selmIsGstDescGoodForSReg: CS needs code segment\n"));
return false;
}
}
{
return false;
}
|| !CPUMIsGuestInRawMode(pVCpu) ) )
)
)
{
return false;
}
}
return true;
}
/**
* Converts a guest GDT or LDT entry to a shadow table entry.
*
* @param pVM The VM handle.
* @param pDesc Guest entry on input, shadow entry on return.
*/
{
/*
* Code and data selectors are generally 1:1, with the
* 'little' adjustment we do for DPL 0 selectors.
*/
{
/*
* Hack for A-bit against Trap E on read-only GDT.
*/
/** @todo Fix this by loading ds and cs before turning off WP. */
/*
* All DPL 0 code and data segments are squeezed into DPL 1.
*
* We're skipping conforming segments here because those
* cannot give us any trouble.
*/
!= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
{
}
# ifdef VBOX_WITH_RAW_RING1
!= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
{
}
# endif
else
}
else
{
/*
* System type selectors are marked not present.
* Recompiler or special handling is required for these.
*/
/** @todo what about interrupt gates and rawr0? */
}
}
/**
* Checks if a segment register is stale given the shadow descriptor table
* entry.
*
* @returns @c true if stale, @c false if not.
* @param pSReg The segment register.
* @param pShwDesc The shadow descriptor entry.
* @param iSReg The segment register number (X86_SREG_XXX).
*/
{
{
Log(("selmIsSRegStale32: Attributes changed (%#x -> %#x)\n", pSReg->Attr.u, X86DESC_GET_HID_ATTR(pShwDesc)));
return true;
}
{
Log(("selmIsSRegStale32: base changed (%#llx -> %#llx)\n", pSReg->u64Base, X86DESC_BASE(pShwDesc)));
return true;
}
{
Log(("selmIsSRegStale32: limit changed (%#x -> %#x)\n", pSReg->u32Limit, X86DESC_LIMIT_G(pShwDesc)));
return true;
}
return false;
}
/**
* Loads the hidden bits of a selector register from a shadow descriptor table
* entry.
*
* @param pSReg The segment register in question.
* @param pShwDesc The shadow descriptor table entry.
*/
{
/** @todo VBOX_WITH_RAW_RING1 */
}
/**
* Loads the hidden bits of a selector register from a guest descriptor table
* entry.
*
* @param pVCpu The current virtual CPU.
* @param pSReg The segment register in question.
* @param pGstDesc The guest descriptor table entry.
*/
DECLINLINE(void) selmLoadHiddenSRegFromGuestDesc(PVMCPU pVCpu, PCPUMSELREG pSReg, PCX86DESC pGstDesc)
{
/** @todo VBOX_WITH_RAW_RING1 */
}
#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
/** @} */
#endif