SELMInline.h revision 7847c123aebebc6d3d5c1406619cfba1ab6457c1
64c02f1310b7747423957823ee09fb3608430f89nd/* $Id$ */
64c02f1310b7747423957823ee09fb3608430f89nd/** @file
64c02f1310b7747423957823ee09fb3608430f89nd * SELM - Internal header file.
64c02f1310b7747423957823ee09fb3608430f89nd */
64c02f1310b7747423957823ee09fb3608430f89nd
64c02f1310b7747423957823ee09fb3608430f89nd/*
64c02f1310b7747423957823ee09fb3608430f89nd * Copyright (C) 2006-2012 Oracle Corporation
96ad5d81ee4a2cc66a4ae19893efc8aa6d06fae7jailletc *
64c02f1310b7747423957823ee09fb3608430f89nd * This file is part of VirtualBox Open Source Edition (OSE), as
64c02f1310b7747423957823ee09fb3608430f89nd * available from http://www.virtualbox.org. This file is free software;
d29d9ab4614ff992b0e8de6e2b88d52b6f1f153erbowen * you can redistribute it and/or modify it under the terms of the GNU
2e545ce2450a9953665f701bb05350f0d3f26275nd * General Public License (GPL) as published by the Free Software
d29d9ab4614ff992b0e8de6e2b88d52b6f1f153erbowen * Foundation, in version 2 as it comes in the "COPYING" file of the
d29d9ab4614ff992b0e8de6e2b88d52b6f1f153erbowen * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
64c02f1310b7747423957823ee09fb3608430f89nd * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
64c02f1310b7747423957823ee09fb3608430f89nd */
64c02f1310b7747423957823ee09fb3608430f89nd
af33a4994ae2ff15bc67d19ff1a7feb906745bf8rbowen#ifndef ___SELMInline_h
3f08db06526d6901aa08c110b5bc7dde6bc39905nd#define ___SELMInline_h
64c02f1310b7747423957823ee09fb3608430f89nd
64c02f1310b7747423957823ee09fb3608430f89nd#ifdef VBOX_WITH_RAW_MODE_NOT_R0
64c02f1310b7747423957823ee09fb3608430f89nd
3f08db06526d6901aa08c110b5bc7dde6bc39905nd/**
64c02f1310b7747423957823ee09fb3608430f89nd * Checks if a shadow descriptor table entry is good for the given segment
64c02f1310b7747423957823ee09fb3608430f89nd * register.
3b3b7fc78d1f5bfc2769903375050048ff41ff26nd *
a78048ccbdb6256da15e6b0e7e95355e480c2301nd * @returns @c true if good, @c false if not.
0066eddda7203f6345b56f77d146a759298dc635gryzor * @param pSReg The segment register.
7f5b59ccc63c0c0e3e678a168f09ee6a2f51f9d0nd * @param pShwDesc The shadow descriptor table entry.
f086b4b402fa9a2fefc7dda85de2a3cc1cd0a654rjung * @param iSReg The segment register index (X86_SREG_XXX).
3b3b7fc78d1f5bfc2769903375050048ff41ff26nd * @param uCpl The CPL.
64c02f1310b7747423957823ee09fb3608430f89nd */
64c02f1310b7747423957823ee09fb3608430f89ndDECLINLINE(bool) selmIsShwDescGoodForSReg(PCCPUMSELREG pSReg, PCX86DESC pShwDesc, uint32_t iSReg, uint32_t uCpl)
64c02f1310b7747423957823ee09fb3608430f89nd{
b09fcdfc59ada4712150e7bcc7b502bb9e4601d8rjung /*
64c02f1310b7747423957823ee09fb3608430f89nd * See iemMiscValidateNewSS, iemCImpl_LoadSReg and intel+amd manuals.
64c02f1310b7747423957823ee09fb3608430f89nd */
64c02f1310b7747423957823ee09fb3608430f89nd
64c02f1310b7747423957823ee09fb3608430f89nd if (!pShwDesc->Gen.u1Present)
64c02f1310b7747423957823ee09fb3608430f89nd {
64c02f1310b7747423957823ee09fb3608430f89nd Log(("selmIsShwDescGoodForSReg: Not present\n"));
64c02f1310b7747423957823ee09fb3608430f89nd return false;
64c02f1310b7747423957823ee09fb3608430f89nd }
8e0c9984e1432c934dacca53efc92cde30d0fe53rbowen
64c02f1310b7747423957823ee09fb3608430f89nd if (!pShwDesc->Gen.u1DescType)
64c02f1310b7747423957823ee09fb3608430f89nd {
64c02f1310b7747423957823ee09fb3608430f89nd Log(("selmIsShwDescGoodForSReg: System descriptor\n"));
64c02f1310b7747423957823ee09fb3608430f89nd return false;
64c02f1310b7747423957823ee09fb3608430f89nd }
64c02f1310b7747423957823ee09fb3608430f89nd
64c02f1310b7747423957823ee09fb3608430f89nd if (iSReg == X86_SREG_SS)
64c02f1310b7747423957823ee09fb3608430f89nd {
64c02f1310b7747423957823ee09fb3608430f89nd if ((pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
64c02f1310b7747423957823ee09fb3608430f89nd {
64c02f1310b7747423957823ee09fb3608430f89nd Log(("selmIsShwDescGoodForSReg: Stack must be writable\n"));
64c02f1310b7747423957823ee09fb3608430f89nd return false;
64c02f1310b7747423957823ee09fb3608430f89nd }
64c02f1310b7747423957823ee09fb3608430f89nd if (uCpl > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available)
64c02f1310b7747423957823ee09fb3608430f89nd {
64c02f1310b7747423957823ee09fb3608430f89nd Log(("selmIsShwDescGoodForSReg: CPL(%d) > DPL(%d)\n", uCpl, pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available));
64c02f1310b7747423957823ee09fb3608430f89nd return false;
64c02f1310b7747423957823ee09fb3608430f89nd }
64c02f1310b7747423957823ee09fb3608430f89nd }
64c02f1310b7747423957823ee09fb3608430f89nd else
64c02f1310b7747423957823ee09fb3608430f89nd {
64c02f1310b7747423957823ee09fb3608430f89nd if (iSReg == X86_SREG_CS)
64c02f1310b7747423957823ee09fb3608430f89nd {
64c02f1310b7747423957823ee09fb3608430f89nd if (!(pShwDesc->Gen.u4Type & X86_SEL_TYPE_CODE))
64c02f1310b7747423957823ee09fb3608430f89nd {
64c02f1310b7747423957823ee09fb3608430f89nd Log(("selmIsShwDescGoodForSReg: CS needs code segment\n"));
64c02f1310b7747423957823ee09fb3608430f89nd return false;
64c02f1310b7747423957823ee09fb3608430f89nd }
64c02f1310b7747423957823ee09fb3608430f89nd }
64c02f1310b7747423957823ee09fb3608430f89nd else if ((pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
8951c7d73bfa2ae5a2c8fe5bd27f3e677be02564noirin {
8951c7d73bfa2ae5a2c8fe5bd27f3e677be02564noirin Log(("selmIsShwDescGoodForSReg: iSReg=%u execute only\n", iSReg));
64c02f1310b7747423957823ee09fb3608430f89nd return false;
64c02f1310b7747423957823ee09fb3608430f89nd }
64c02f1310b7747423957823ee09fb3608430f89nd
64c02f1310b7747423957823ee09fb3608430f89nd if ( (pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
64c02f1310b7747423957823ee09fb3608430f89nd != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)
9335f6d807d76d60e54af4ededdebebddb3e3d13noodl && ( ( (pSReg->Sel & X86_SEL_RPL) > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available
30471a4650391f57975f60bbb6e4a90be7b284bfhumbedooh && (pSReg->Sel & X86_SEL_RPL) != pShwDesc->Gen.u1Available )
64c02f1310b7747423957823ee09fb3608430f89nd || uCpl > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available ) )
64c02f1310b7747423957823ee09fb3608430f89nd {
64c02f1310b7747423957823ee09fb3608430f89nd Log(("selmIsShwDescGoodForSReg: iSReg=%u DPL=%u CPL=%u RPL=%u\n", iSReg,
64c02f1310b7747423957823ee09fb3608430f89nd pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available, uCpl, pSReg->Sel & X86_SEL_RPL));
67c026fea89b4faf173772b5944b6aa006ca6eb0nd return false;
64c02f1310b7747423957823ee09fb3608430f89nd }
64c02f1310b7747423957823ee09fb3608430f89nd }
64c02f1310b7747423957823ee09fb3608430f89nd
64c02f1310b7747423957823ee09fb3608430f89nd return true;
64c02f1310b7747423957823ee09fb3608430f89nd}
64c02f1310b7747423957823ee09fb3608430f89nd
64c02f1310b7747423957823ee09fb3608430f89nd
64c02f1310b7747423957823ee09fb3608430f89nd/**
64c02f1310b7747423957823ee09fb3608430f89nd * Checks if a guest descriptor table entry is good for the given segment
64c02f1310b7747423957823ee09fb3608430f89nd * register.
4aa603e6448b99f9371397d439795c91a93637eand *
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic * @returns @c true if good, @c false if not.
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic * @param pVCpu The current virtual CPU.
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic * @param pSReg The segment register.
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic * @param pGstDesc The guest descriptor table entry.
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic * @param iSReg The segment register index (X86_SREG_XXX).
4aa603e6448b99f9371397d439795c91a93637eand * @param uCpl The CPL.
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic */
64c02f1310b7747423957823ee09fb3608430f89ndDECLINLINE(bool) selmIsGstDescGoodForSReg(PVMCPU pVCpu, PCCPUMSELREG pSReg, PCX86DESC pGstDesc, uint32_t iSReg, uint32_t uCpl)
64c02f1310b7747423957823ee09fb3608430f89nd{
67c026fea89b4faf173772b5944b6aa006ca6eb0nd /*
64c02f1310b7747423957823ee09fb3608430f89nd * See iemMiscValidateNewSS, iemCImpl_LoadSReg and intel+amd manuals.
64c02f1310b7747423957823ee09fb3608430f89nd */
64c02f1310b7747423957823ee09fb3608430f89nd
64c02f1310b7747423957823ee09fb3608430f89nd if (!pGstDesc->Gen.u1Present)
64c02f1310b7747423957823ee09fb3608430f89nd {
64c02f1310b7747423957823ee09fb3608430f89nd Log(("selmIsGstDescGoodForSReg: Not present\n"));
64c02f1310b7747423957823ee09fb3608430f89nd return false;
64c02f1310b7747423957823ee09fb3608430f89nd }
64c02f1310b7747423957823ee09fb3608430f89nd
64c02f1310b7747423957823ee09fb3608430f89nd if (!pGstDesc->Gen.u1DescType)
64c02f1310b7747423957823ee09fb3608430f89nd {
4aa603e6448b99f9371397d439795c91a93637eand Log(("selmIsGstDescGoodForSReg: System descriptor\n"));
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic return false;
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic }
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic if (iSReg == X86_SREG_SS)
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic {
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic if ((pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic {
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic Log(("selmIsGstDescGoodForSReg: Stack must be writable\n"));
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic return false;
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic }
4aa603e6448b99f9371397d439795c91a93637eand if (uCpl > pGstDesc->Gen.u2Dpl)
f0fa55ff14fa0bf8fd72d989f6625de6dc3260c8igalic {
64c02f1310b7747423957823ee09fb3608430f89nd Log(("selmIsGstDescGoodForSReg: CPL(%d) > DPL(%d)\n", uCpl, pGstDesc->Gen.u2Dpl));
64c02f1310b7747423957823ee09fb3608430f89nd return false;
64c02f1310b7747423957823ee09fb3608430f89nd }
3b3b7fc78d1f5bfc2769903375050048ff41ff26nd }
a78048ccbdb6256da15e6b0e7e95355e480c2301nd else
0066eddda7203f6345b56f77d146a759298dc635gryzor {
7f5b59ccc63c0c0e3e678a168f09ee6a2f51f9d0nd if (iSReg == X86_SREG_CS)
f086b4b402fa9a2fefc7dda85de2a3cc1cd0a654rjung {
727872d18412fc021f03969b8641810d8896820bhumbedooh if (!(pGstDesc->Gen.u4Type & X86_SEL_TYPE_CODE))
0d0ba3a410038e179b695446bb149cce6264e0abnd {
727872d18412fc021f03969b8641810d8896820bhumbedooh Log(("selmIsGstDescGoodForSReg: CS needs code segment\n"));
cc7e1025de9ac63bd4db6fe7f71c158b2cf09fe4humbedooh return false;
0d0ba3a410038e179b695446bb149cce6264e0abnd }
cc7e1025de9ac63bd4db6fe7f71c158b2cf09fe4humbedooh }
727872d18412fc021f03969b8641810d8896820bhumbedooh else if ((pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
0d0ba3a410038e179b695446bb149cce6264e0abnd {
0d0ba3a410038e179b695446bb149cce6264e0abnd Log(("selmIsGstDescGoodForSReg: iSReg=%u execute only\n", iSReg));
0d0ba3a410038e179b695446bb149cce6264e0abnd return false;
ac082aefa89416cbdc9a1836eaf3bed9698201c8humbedooh }
0d0ba3a410038e179b695446bb149cce6264e0abnd
0d0ba3a410038e179b695446bb149cce6264e0abnd if ( (pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
0d0ba3a410038e179b695446bb149cce6264e0abnd != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)
727872d18412fc021f03969b8641810d8896820bhumbedooh && ( ( (pSReg->Sel & X86_SEL_RPL) > pGstDesc->Gen.u2Dpl
0d0ba3a410038e179b695446bb149cce6264e0abnd && ( (pSReg->Sel & X86_SEL_RPL) != 1
0d0ba3a410038e179b695446bb149cce6264e0abnd || !CPUMIsGuestInRawMode(pVCpu) ) )
30471a4650391f57975f60bbb6e4a90be7b284bfhumbedooh || uCpl > (unsigned)pGstDesc->Gen.u2Dpl
07dc96d063d49299da433f84b5c5681da9bbdf68rbowen )
af33a4994ae2ff15bc67d19ff1a7feb906745bf8rbowen )
0d0ba3a410038e179b695446bb149cce6264e0abnd {
7fec19672a491661b2fe4b29f685bc7f4efa64d4nd Log(("selmIsGstDescGoodForSReg: iSReg=%u DPL=%u CPL=%u RPL=%u InRawMode=%u\n", iSReg,
7fec19672a491661b2fe4b29f685bc7f4efa64d4nd pGstDesc->Gen.u2Dpl, uCpl, pSReg->Sel & X86_SEL_RPL, CPUMIsGuestInRawMode(pVCpu)));
7fec19672a491661b2fe4b29f685bc7f4efa64d4nd return false;
64c02f1310b7747423957823ee09fb3608430f89nd }
}
return true;
}
/**
* Converts a guest GDT or LDT entry to a shadow table entry.
*
* @param pVM The VM handle.
* @param pDesc Guest entry on input, shadow entry on return.
*/
DECL_FORCE_INLINE(void) selmGuestToShadowDesc(PVM pVM, PX86DESC pDesc)
{
/*
* Code and data selectors are generally 1:1, with the
* 'little' adjustment we do for DPL 0 selectors.
*/
if (pDesc->Gen.u1DescType)
{
/*
* Hack for A-bit against Trap E on read-only GDT.
*/
/** @todo Fix this by loading ds and cs before turning off WP. */
pDesc->Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
/*
* All DPL 0 code and data segments are squeezed into DPL 1.
*
* We're skipping conforming segments here because those
* cannot give us any trouble.
*/
if ( pDesc->Gen.u2Dpl == 0
&& (pDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
!= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
{
pDesc->Gen.u2Dpl = 1;
pDesc->Gen.u1Available = 1;
}
# ifdef VBOX_WITH_RAW_RING1
else if ( pDesc->Gen.u2Dpl == 1
&& EMIsRawRing1Enabled(pVM)
&& (pDesc->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
!= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
{
pDesc->Gen.u2Dpl = 2;
pDesc->Gen.u1Available = 1;
}
# endif
else
pDesc->Gen.u1Available = 0;
}
else
{
/*
* System type selectors are marked not present.
* Recompiler or special handling is required for these.
*/
/** @todo what about interrupt gates and rawr0? */
pDesc->Gen.u1Present = 0;
}
}
/**
* Checks if a segment register is stale given the shadow descriptor table
* entry.
*
* @returns @c true if stale, @c false if not.
* @param pSReg The segment register.
* @param pShwDesc The shadow descriptor entry.
* @param iSReg The segment register number (X86_SREG_XXX).
*/
DECLINLINE(bool) selmIsSRegStale32(PCCPUMSELREG pSReg, PCX86DESC pShwDesc, uint32_t iSReg)
{
if ( pSReg->Attr.n.u1Present != pShwDesc->Gen.u1Present
|| pSReg->Attr.n.u4Type != pShwDesc->Gen.u4Type
|| pSReg->Attr.n.u1DescType != pShwDesc->Gen.u1DescType
|| pSReg->Attr.n.u1DefBig != pShwDesc->Gen.u1DefBig
|| pSReg->Attr.n.u1Granularity != pShwDesc->Gen.u1Granularity
|| pSReg->Attr.n.u2Dpl != pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available)
{
Log(("selmIsSRegStale32: Attributes changed (%#x -> %#x)\n", pSReg->Attr.u, X86DESC_GET_HID_ATTR(pShwDesc)));
return true;
}
if (pSReg->u64Base != X86DESC_BASE(pShwDesc))
{
Log(("selmIsSRegStale32: base changed (%#llx -> %#llx)\n", pSReg->u64Base, X86DESC_BASE(pShwDesc)));
return true;
}
if (pSReg->u32Limit != X86DESC_LIMIT_G(pShwDesc))
{
Log(("selmIsSRegStale32: limit changed (%#x -> %#x)\n", pSReg->u32Limit, X86DESC_LIMIT_G(pShwDesc)));
return true;
}
return false;
}
/**
* Loads the hidden bits of a selector register from a shadow descriptor table
* entry.
*
* @param pSReg The segment register in question.
* @param pShwDesc The shadow descriptor table entry.
*/
DECLINLINE(void) selmLoadHiddenSRegFromShadowDesc(PCPUMSELREG pSReg, PCX86DESC pShwDesc)
{
pSReg->Attr.u = X86DESC_GET_HID_ATTR(pShwDesc);
pSReg->Attr.n.u2Dpl -= pSReg->Attr.n.u1Available;
Assert(pSReg->Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
pSReg->u32Limit = X86DESC_LIMIT_G(pShwDesc);
pSReg->u64Base = X86DESC_BASE(pShwDesc);
pSReg->ValidSel = pSReg->Sel;
if (pSReg->Attr.n.u1Available)
pSReg->ValidSel &= ~(RTSEL)1;
pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
}
/**
* Loads the hidden bits of a selector register from a guest descriptor table
* entry.
*
* @param pVCpu The current virtual CPU.
* @param pSReg The segment register in question.
* @param pGstDesc The guest descriptor table entry.
*/
DECLINLINE(void) selmLoadHiddenSRegFromGuestDesc(PVMCPU pVCpu, PCPUMSELREG pSReg, PCX86DESC pGstDesc)
{
pSReg->Attr.u = X86DESC_GET_HID_ATTR(pGstDesc);
pSReg->Attr.n.u4Type |= X86_SEL_TYPE_ACCESSED;
pSReg->u32Limit = X86DESC_LIMIT_G(pGstDesc);
pSReg->u64Base = X86DESC_BASE(pGstDesc);
pSReg->ValidSel = pSReg->Sel;
if ((pSReg->ValidSel & 1) && CPUMIsGuestInRawMode(pVCpu))
pSReg->ValidSel &= ~(RTSEL)1;
pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
}
#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
/** @} */
#endif