IEMInternal.h revision a2c0b38648fa3620ea46f884eb614abbf00c6759
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * IEM - Internal header file.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * Copyright (C) 2011-2012 Oracle Corporation
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * available from http://www.virtualbox.org. This file is free software;
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * you can redistribute it and/or modify it under the terms of the GNU
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * General Public License (GPL) as published by the Free Software
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** @defgroup grp_iem_int Internals
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * @ingroup grp_iem
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * @internal
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** @def IEM_VERIFICATION_MODE_FULL
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * Shorthand for:
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * defined(IEM_VERIFICATION_MODE) && !defined(IEM_VERIFICATION_MODE_MINIMAL)
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync#if defined(IEM_VERIFICATION_MODE) && !defined(IEM_VERIFICATION_MODE_MINIMAL) && !defined(IEM_VERIFICATION_MODE_FULL)
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Finish and move to types.h */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsynctypedef union
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * Operand or addressing mode.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * Extended operand mode that includes a representation of 8-bit.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * This is used for packing down modes when invoking some C instruction
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * implementations.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * Branch types.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * A FPU result.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsynctypedef struct IEMFPURESULT
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The output value. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The output status. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Pointer to a FPU result. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Pointer to a const FPU result. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * A FPU result consisting of two output values and FSW.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The first output value. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The output status. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The second output value. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsyncAssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsyncAssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Pointer to a FPU result consisting of two output values and FSW. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Pointer to a const FPU result consisting of two output values and FSW. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * Verification event type.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Checks if the event type is a RAM read or write. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync# define IEMVERIFYEVENT_IS_RAM(a_enmType) ((a_enmType) == IEMVERIFYEVENT_RAM_WRITE || (a_enmType) == IEMVERIFYEVENT_RAM_READ)
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * Verification event record.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Pointer to the next record in the list. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The event type. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The event data. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** IEMVERIFYEVENT_IOPORT_READ */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** IEMVERIFYEVENT_IOPORT_WRITE */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** IEMVERIFYEVENT_RAM_READ */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** IEMVERIFYEVENT_RAM_WRITE */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Pointer to an IEM event verification records. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync#endif /* IEM_VERIFICATION_MODE_FULL */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * The per-CPU IEM state.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsynctypedef struct IEMCPU
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Pointer to the CPU context - ring-3 contex. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Pointer to the CPU context - ring-0 contex. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Pointer to the CPU context - raw-mode contex. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Offset of the VMCPU structure relative to this structure (negative). */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Offset of the VM structure relative to this structure (negative). */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Whether to bypass access handlers or not. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Indicates that we're interpreting patch code - RC only! */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Explicit alignment padding. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The flags of the current exception / interrupt. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The current exception / interrupt. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Exception / interrupt recursion depth. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Explicit alignment padding. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The CPL. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The current CPU execution mode (CS). */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Info status code that needs to be propagated to the IEM caller.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * This cannot be passed internally, as it would complicate all success
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * checks within the interpreter making the code larger and almost impossible
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * to get right. Instead, we'll store status codes to pass on here. Each
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * source of these codes will perform appropriate sanity checks. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** @name Statistics
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The number of instructions we've executed. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The number of potential exits. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The number of bytes data or stack written (mostly for IEMExecOneEx).
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * This may contain uncommitted writes. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Counts informational statuses returned (other than VINF_SUCCESS). */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Counts other error statuses returned. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Number of times rcPassUp has been used. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The Number of I/O port reads that has been performed. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The Number of I/O port writes that has been performed. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Set if no comparison to REM is currently performed.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * This is used to skip past really slow bits. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Indicates that RAX and RDX differences should be ignored since RDTSC
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * and RDTSCP are timing sensitive. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Indicates that a MOVS instruction with overlapping source and destination
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * was executed, causing the memory write records to be incorrrect. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** This is used to communicate a CPL changed caused by IEMInjectTrap that
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * CPUM doesn't yet reflect. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Mask of undefined eflags.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * The verifier will any difference in these flags. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The CS of the instruction being interpreted. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The RIP of the instruction being interpreted. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The physical address corresponding to abOpcodes[0]. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** @name Decoder state.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The default addressing mode . */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The effective addressing mode . */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The default operand mode . */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The effective operand mode . */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The prefix mask (IEM_OP_PRF_XXX). */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The extra REX ModR/M register field bit (REX.R << 3). */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The extra REX ModR/M r/m field, SIB base and opcode reg bit
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * (REX.B << 3). */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The extra REX SIB index field bit (REX.X << 3). */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The effective segment register (X86_SREG_XXX). */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The current offset into abOpcodes. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The size of what has currently been fetched into abOpcodes. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The opcode bytes. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Offset into abOpcodes where the FPU instruction starts.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * Only set by the FPU escape opcodes (0xd8-0xdf) and used later on when the
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * instruction result is committed. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Alignment padding for aMemMappings. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The number of active guest memory mappings. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The next unused mapping index. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Records for tracking guest memory mappings. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The address of the mapped bytes. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The access flags (IEM_ACCESS_XXX).
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * IEM_ACCESS_INVALID if the entry is unused. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Locking records for the mapped memory. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Bounce buffer info.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * This runs in parallel to aMemMappings. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The physical address of the first byte. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The physical address of the second page. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The number of bytes in the first page. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The number of bytes in the second page. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Whether it's unassigned memory. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Explicit alignment padding. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Bounce buffer storage.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * This runs in parallel to aMemMappings and aMemBbMappings. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The event verification records for what IEM did (LIFO). */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Insertion point for pIemEvtRecHead. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** The event verification records for what the other party did (FIFO). */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** Insertion point for pOtherEvtRecHead. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync /** List of free event records. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Pointer to the per-CPU IEM state. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Converts a IEMCPU pointer to a VMCPU pointer.
99f33ab590a3a65e0cd082dd8d67779efb9cc6c9vboxsync * @returns VMCPU pointer.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * @param a_pIemCpu The IEM per CPU instance data.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync#define IEMCPU_TO_VMCPU(a_pIemCpu) ((PVMCPU)( (uintptr_t)(a_pIemCpu) + a_pIemCpu->offVMCpu ))
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Converts a IEMCPU pointer to a VM pointer.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * @returns VM pointer.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * @param a_pIemCpu The IEM per CPU instance data.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync#define IEMCPU_TO_VM(a_pIemCpu) ((PVM)( (uintptr_t)(a_pIemCpu) + a_pIemCpu->offVM ))
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** @name IEM_ACCESS_XXX - Access details.
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** The writes are partial, so if initialize the bounce buffer with the
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync * orignal RAM content. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Used in aMemMappings to indicate that the entry is bounce buffered. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
99f33ab590a3a65e0cd082dd8d67779efb9cc6c9vboxsync/** Read+write data alias. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA)
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Write data alias. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA)
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Read data alias. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA)
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Instruction fetch alias. */
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC | IEM_ACCESS_WHAT_CODE)
a1a825a2fcd6b32bd63d40a0705ef68fcbf1ed16vboxsync/** Stack write alias. */
#define IEM_OP_PRF_REX_R RT_BIT_32(25) /**< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). */
#define IEM_OP_PRF_REX_B RT_BIT_32(26) /**< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). */
#define IEM_OP_PRF_REX_X RT_BIT_32(27) /**< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). */
#ifdef IEM_VERIFICATION_MODE_FULL
#ifdef IEM_VERIFICATION_MODE_FULL
#if (defined(IEM_VERIFICATION_MODE_FULL) || defined(IEM_VERIFICATION_MODE_MINIMAL)) && !defined(IEM_VERIFICATION_MODE)
# define IEM_VERIFICATION_MODE
#ifdef IEM_VERIFICATION_MODE_FULL
# define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { pIemCpu->fUndefinedEFlags |= (a_fEfl); } while (0)
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t *pu8Dst, uint8_t u8Src, uint32_t *pEFlags));
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t *pu16Dst, uint16_t u16Src, uint32_t *pEFlags));
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t *pu32Dst, uint32_t u32Src, uint32_t *pEFlags));
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t *pu64Dst, uint64_t u64Src, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t *pu16Dst, uint16_t *pu16Reg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t *pu32Dst, uint32_t *pu32Reg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t *pu64Dst, uint64_t *pu64Reg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t *pu8Dst, uint8_t *pu8Reg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t *pu16Dst, uint16_t *pu16Reg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t *pu32Dst, uint32_t *pu32Reg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t *pu64Dst, uint64_t *pu64Reg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags));
#ifdef RT_ARCH_X86
IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags));
IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U *pu128Dst, PRTUINT128U pu64RaxRdx, PRTUINT128U pu64RbxRcx,
IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U *pu128Dst, PRTUINT128U pu64RaxRdx, PRTUINT128U pu64RbxRcx,
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t *pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t *pEFlags));
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t *pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t *pEFlags));
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t *pEFlags));
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t *pu8Dst, uint8_t cShift, uint32_t *pEFlags));
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t *pu16Dst, uint8_t cShift, uint32_t *pEFlags));
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t *pu32Dst, uint8_t cShift, uint32_t *pEFlags));
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t *pu64Dst, uint8_t cShift, uint32_t *pEFlags));
typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t *pu16AX, uint8_t u8FactorDivisor, uint32_t *pEFlags));
typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t *pu16AX, uint16_t *pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t *pu32EAX, uint32_t *pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t *pu32Dst)); /* Yes, 32-bit register access. */
IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
typedef struct IEMOPBINSIZES
typedef struct IEMOPUNARYSIZES
typedef struct IEMOPSHIFTSIZES
typedef struct IEMOPMULDIVSIZES
typedef struct IEMOPSHIFTDBLSIZES
IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PIEMCPU pIemCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PIEMCPU pIemCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PIEMCPU pIemCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PIEMCPU pIemCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PIEMCPU pIemCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PIEMCPU pIemCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \