GIMHvInternal.h revision eca46116c06b850c8c6be84678ba1f9dbdb3f9dd
/** Virtual system reset MSR available. */ /** Statistic pages MSRs available. */ /** Paritition reference TSC MSR available. */ /** Virtual guest idle state MSR available. */ /** Timer frequency MSRs (TSC and APIC) available. */ /** Debug MSRs available. */ /** @name Hyper-V partition-creation feature identification. * Indicates flags specified during partition creation. /** Create partitions. */ /** Access partition Id. */ /** Access memory pool. */ /** Adjust message buffers. */ /** Access statistics. */ /** Enable expanded stack walking. */ /** @name Hyper-V power management feature identification. /** Maximum CPU power state C0. */ /** Maximum CPU power state C1. */ /** Maximum CPU power state C2. */ /** Maximum CPU power state C3. */ /** HPET is required to enter C3 power state. */ /** @name Hyper-V miscellaneous feature identification. * Miscellaneous features available for the current partition. /** MWAIT instruction available. */ /** Guest debugging support available. */ /** Performance monitor support is available. */ /** Support for physical CPU dynamic partitioning events. */ /** Support for passing hypercall input parameter block via XMM registers. */ /** Support for virtual guest idle state. */ /** Support for hypervisor sleep state. */ /** Support for querying NUMA distances. */ /** Support for determining timer frequencies. */ /** Support for injecting synthetic machine checks. */ /** Support for guest crash MSRs. */ /** Support for debug MSRs. */ /** Npiep1 Available */ /** @todo What the heck is this? */ /** Disable hypervisor available. */ /** @name Hyper-V implementation recommendations. * Recommendations from the hypervisor for the guest for optimal performance. /** Use hypercall for address space switches rather than MOV CR3. */ /** Use hypercall for local TLB flushes rather than INVLPG/MOV CR3. */ /** Use hypercall for inter-CPU TLB flushes rather than IPIs. */ /** Use MSRs for APIC access (EOI, ICR, TPR) rather than MMIO. */ /** Use hypervisor provided MSR for a system reset. */ * timely deliver of external interrupts. */ /** Use DMA remapping. */ /** Use interrupt remapping. */ /** Use X2APIC MSRs rather than MMIO. */ /** Deprecate Auto EOI (end of interrupt). */ /** @name Hyper-V implementation hardware features. * Which hardware features are in use by the hypervisor. /** APIC overlay is used. */ /** MSR bitmaps is used. */ /** Architectural performance counter supported. */ /** Nested paging is used. */ /** DMA remapping is used. */ /** Interrupt remapping is used. */ /** Memory patrol scrubber is present. */ /** Guest OS identification (R/W) */ /** Enable hypercall interface (R/W) */ /** Virtual processor's (VCPU) index (R) */ /** Reset operation (R/W) */ /** Virtual processor's (VCPU) runtime (R) */ /** Per-VM reference counter (R) */ /** Per-VM TSC page (R/W) */ /** Frequency of TSC in Hz as reported by the hypervisor (R) */ /** Frequency of LAPIC in Hz as reported by the hypervisor (R) */ /** Access to APIC EOI (End-Of-Interrupt) register (W) */ /** Access to APIC ICR (Interrupt Command) register (R/W) */ /** Access to APIC TPR (Task Priority) register (R/W) */ /** Enables lazy EOI processing (R/W) */ /** Control behaviour of synthetic interrupt controller (R/W) */ /** Synthetic interrupt controller version (R) */ /** Base address of synthetic interrupt event flag (R/W) */ /** Base address of synthetic interrupt parameter page (R/W) */ /** End-Of-Message in synthetic interrupt parameter page (W) */ /** Configures synthetic interrupt source 0 (R/W) */ /** Configures synthetic interrupt source 1 (R/W) */ /** Configures synthetic interrupt source 2 (R/W) */ /** Configures synthetic interrupt source 3 (R/W) */ /** Configures synthetic interrupt source 4 (R/W) */ /** Configures synthetic interrupt source 5 (R/W) */ /** Configures synthetic interrupt source 6 (R/W) */ /** Configures synthetic interrupt source 7 (R/W) */ /** Configures synthetic interrupt source 8 (R/W) */ /** Configures synthetic interrupt source 9 (R/W) */ /** Configures synthetic interrupt source 10 (R/W) */ /** Configures synthetic interrupt source 11 (R/W) */ /** Configures synthetic interrupt source 12 (R/W) */ /** Configures synthetic interrupt source 13 (R/W) */ /** Configures synthetic interrupt source 14 (R/W) */ /** Configures synthetic interrupt source 15 (R/W) */ /** Configures register for synthetic timer 0 (R/W) */ /** Expiration time or period for synthetic timer 0 (R/W) */ /** Configures register for synthetic timer 1 (R/W) */ /** Expiration time or period for synthetic timer 1 (R/W) */ /** Configures register for synthetic timer 2 (R/W) */ /** Expiration time or period for synthetic timer 2 (R/W) */ /** Configures register for synthetic timer 3 (R/W) */ /** Expiration time or period for synthetic timer 3 (R/W) */ /** Trigger to transition to power state C1 (R) */ /** Trigger to transition to power state C2 (R) */ /** Trigger to transition to power state C3 (R) */ /** Configure the recipe for power state transitions to C1 (R/W) */ /** Configure the recipe for power state transitions to C2 (R/W) */ /** Configure the recipe for power state transitions to C3 (R/W) */ /** Map the guest's retail partition stats page (R/W) */ /** Map the guest's internal partition stats page (R/W) */ /** Map the guest's retail VP stats page (R/W) */ /** Map the guest's internal VP stats page (R/W) */ /** Start of range 10. */ /** Trigger the guest's transition to idle power state (R) */ /** Synthetic debug control. */ /** Synthetic debug status. */ /** Synthetic debug send buffer. */ /** Synthetic debug receive buffer. */ /** Synthetic debug pending buffer. */ /** Start of range 11. */ /** Guest crash MSR 0. */ /** Guest crash MSR 1. */ /** Guest crash MSR 2. */ /** Guest crash MSR 3. */ /** Guest crash MSR 4. */ /** Guest crash control. */ /** @name Hyper-V MSR - Hypercall (MSR_GIM_HV_HYPERCALL). /** Guest-physical page frame number of the hypercall-page. */ /** The hypercall enable bit. */ /** Whether the hypercall-page is enabled or not. */ /** @name Hyper-V MSR - Reference TSC (MSR_GIM_HV_REF_TSC). /** Guest-physical page frame number of the TSC-page. */ /** The TSC-page enable bit. */ /** Whether the TSC-page is enabled or not. */ /** Hyper-V page size. */ /** The hypercall page region. */ /** The TSC page region. */ /** The maximum region index (must be <= UINT8_MAX). */ * Hyper-V TSC (HV_REFERENCE_TSC_PAGE) structure placed in the TSC reference /** Pointer to GIM VMCPU instance data. */ * GIM Hyper-V VM Instance data. * Changes to this must checked against the padding of the gim union in VM! /** Guest OS identity MSR. */ /** Reference TSC page MSR. */ /** Power management features. */ /** Miscellaneous features. */ /** Alignment padding. */ /** Array of MMIO2 regions. */ /** Pointer to per-VM GIM Hyper-V instance data. */ /** Pointer to const per-VM GIM Hyper-V instance data. */ #
endif /* ___GIMHvInternal_h */