GIMHvInternal.h revision bc5cd42756b3f98351040bbfccc08dd9bacd103a
/* $Id$ */
/** @file
* GIM - Hyper-V, Internal header file.
*/
/*
* Copyright (C) 2014 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
#ifndef ___GIMHvInternal_h
#define ___GIMHvInternal_h
/** @name Hyper-V base feature identification.
* Base features based on current partition privileges.
* @{
*/
/** Virtual processor runtime MSR available. */
#define GIM_HV_BASE_FEAT_VP_RUNTIME_MSR RT_BIT(0)
/** Partition reference counter MSR available. */
/** Basic Synthetic Interrupt Controller MSRs available. */
/** Synthetic Timer MSRs available. */
/** APIC access MSRs (EOI, ICR, TPR) available. */
/** Hypercall MSRs available. */
/** Access to VCPU index MSR available. */
/** Virtual system reset MSR available. */
/** Statistic pages MSRs available. */
/** Paritition reference TSC MSR available. */
/** Virtual guest idle state MSR available. */
/** Timer frequency MSRs available. */
/** Debug MSRs available. */
/** @} */
/** @name Hyper-V partition-creation feature identification.
* Indicates flags specified during partition creation.
* @{
*/
/** Create partitions. */
#define GIM_HV_PART_FLAGS_CREATE_PART RT_BIT(0)
/** Access partition Id. */
/** Access memory pool. */
/** Adjust message buffers. */
/** Post messages. */
/** Signal events. */
/** Create port. */
/** Connect port. */
/** Access statistics. */
/** Debugging.*/
/** CPU management. */
/** CPU profiler. */
/** Enable expanded stack walking. */
/** @} */
/** @name Hyper-V power management feature identification.
* @{
*/
/** Maximum CPU power state C0. */
#define GIM_HV_PM_MAX_CPU_POWER_STATE_C0 RT_BIT(0)
/** Maximum CPU power state C1. */
/** Maximum CPU power state C2. */
/** Maximum CPU power state C3. */
/** HPET is required to enter C3 power state. */
/** @} */
/** @name Hyper-V miscellaneous feature identification.
* Miscellaneous features available for the current partition.
* @{
*/
/** MWAIT instruction available. */
#define GIM_HV_MISC_FEAT_MWAIT RT_BIT(0)
/** Guest debugging support available. */
/** Performance monitor support is available. */
/** Support for physical CPU dynamic partitioning events. */
/** Support for passing hypercall input parameter block via XMM registers. */
/** Support for virtual guest idle state. */
/** Support for hypervisor sleep state. */
/** Support for querying NUMA distances. */
/** Support for determining timer frequencies. */
/** Support for injecting synthetic machine checks. */
/** Support for guest crash MSRs. */
/** Support for debug MSRs. */
/** Npiep1 Available */ /** @todo What the heck is this? */
/** Disable hypervisor available. */
/** @} */
/** @name Hyper-V implementation recommendations.
* Recommendations from the hypervisor for the guest for optimal performance.
* @{
*/
/** Use hypercall for address space switches rather than MOV CR3. */
#define GIM_HV_HINT_HYPERCALL_FOR_PROCESS_SWITCH RT_BIT(0)
/** Use hypercall for inter-CPU TLB flushes rather than IPIs. */
/** Use MSRs for APIC access (EOI, ICR, TPR) rather than MMIO. */
/** Use hypervisor provided MSR for a system reset. */
* timely deliver of external interrupts. */
/** Use DMA remapping. */
/** Use interrupt remapping. */
/** Use X2APIC MSRs rather than MMIO. */
/** Deprecate Auto EOI (end of interrupt). */
/** @} */
/** @name Hyper-V implementation hardware features.
* Which hardware features are in use by the hypervisor.
* @{
*/
/** APIC overlay is used. */
#define GIM_HV_HOST_FEAT_AVIC RT_BIT(0)
/** MSR bitmaps is used. */
/** Architectural performance counter supported. */
/** Nested paging is used. */
/** DMA remapping is used. */
/** Interrupt remapping is used. */
/** Memory patrol scrubber is present. */
/** @} */
/** @name Hyper-V MSRs.
* @{
*/
/** Start of range 0. */
/** Guest OS identification (R/W) */
/** Enable hypercall interface (R/W) */
/** Virtual processor's (VCPU) index (R) */
/** Reset operation (R/W) */
/** End of range 0. */
/** Start of range 1. */
/** Virtual processor's (VCPU) runtime (R) */
/** End of range 1. */
/** Start of range 2. */
/** Per-VM reference counter (R) */
/** Per-VM TSC (R) */
/** Frequency of TSC in Hz as reported by the hypervisor (R) */
/** Frequency of LAPIC in Hz as reported by the hypervisor (R) */
/** End of range 2. */
/** Start of range 3. */
/** Access to APIC EOI (End-Of-Interrupt) register (W) */
/** Access to APIC ICR (Interrupt Command) register (R/W) */
/** Access to APIC TPR (Task Priority) register (R/W) */
/** Enables lazy EOI processing (R/W) */
/** End of range 3. */
/** Start of range 4. */
/** Control behaviour of synthetic interrupt controller (R/W) */
/** Synthetic interrupt controller version (R) */
/** Base address of synthetic interrupt event flag (R/W) */
/** Base address of synthetic interrupt parameter page (R/W) */
/** End-Of-Message in synthetic interrupt parameter page (W) */
/** End of range 4. */
#define MSR_GIM_HV_RANGE4_END MSR_GIM_HV_EOM
/** Start of range 5. */
/** Configures synthetic interrupt source 0 (R/W) */
/** Configures synthetic interrupt source 1 (R/W) */
/** Configures synthetic interrupt source 2 (R/W) */
/** Configures synthetic interrupt source 3 (R/W) */
/** Configures synthetic interrupt source 4 (R/W) */
/** Configures synthetic interrupt source 5 (R/W) */
/** Configures synthetic interrupt source 6 (R/W) */
/** Configures synthetic interrupt source 7 (R/W) */
/** Configures synthetic interrupt source 8 (R/W) */
/** Configures synthetic interrupt source 9 (R/W) */
/** Configures synthetic interrupt source 10 (R/W) */
/** Configures synthetic interrupt source 11 (R/W) */
/** Configures synthetic interrupt source 12 (R/W) */
/** Configures synthetic interrupt source 13 (R/W) */
/** Configures synthetic interrupt source 14 (R/W) */
/** Configures synthetic interrupt source 15 (R/W) */
/** End of range 5. */
/** Start of range 6. */
/** Configures register for synthetic timer 0 (R/W) */
/** Expiration time or period for synthetic timer 0 (R/W) */
/** Configures register for synthetic timer 1 (R/W) */
/** Expiration time or period for synthetic timer 1 (R/W) */
/** Configures register for synthetic timer 2 (R/W) */
/** Expiration time or period for synthetic timer 2 (R/W) */
/** Configures register for synthetic timer 3 (R/W) */
/** Expiration time or period for synthetic timer 3 (R/W) */
/** End of range 6. */
/** Start of range 7. */
/** Trigger to transition to power state C1 (R) */
/** Trigger to transition to power state C2 (R) */
/** Trigger to transition to power state C3 (R) */
/** End of range 7. */
/** Start of range 8. */
/** Configure the recipe for power state transitions to C1 (R/W) */
/** Configure the recipe for power state transitions to C2 (R/W) */
/** Configure the recipe for power state transitions to C3 (R/W) */
/** End of range 8. */
/** Start of range 9. */
/** Map the guest's retail partition stats page (R/W) */
/** Map the guest's internal partition stats page (R/W) */
/** Map the guest's retail VP stats page (R/W) */
/** Map the guest's internal VP stats page (R/W) */
/** End of range 9. */
/** Start of range 10. */
/** Trigger the guest's transition to idle power state (R) */
/** Synthetic debug control. */
/** Synthetic debug status. */
/** Synthetic debug send buffer. */
/** Synthetic debug receive buffer. */
/** Synthetic debug pending buffer. */
/** End of range 10. */
/** Start of range 11. */
/** Guest crash MSR 0. */
/** Guest crash MSR 1. */
/** Guest crash MSR 2. */
/** Guest crash MSR 3. */
/** Guest crash MSR 4. */
/** Guest crash control. */
/** End of range 11. */
/** @} */
#ifdef IN_RING3
#endif /* IN_RING3 */
VMMDECL(int) GIMHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
#endif /* ___GIMHvInternal_h */