CPUMInternal.h revision ff308c5c63cf562048295f83638429a925415a10
/* $Id$ */
/** @file
* CPUM - Internal header file.
*/
/*
* Copyright (C) 2006-2015 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
#ifndef ___CPUMInternal_h
#define ___CPUMInternal_h
#ifndef VBOX_FOR_DTRACE_LIB
#else
/* Some fudging. */
typedef uint32_t CPUMMICROARCH;
typedef uint32_t CPUMUNKNOWNCPUID;
typedef struct CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
typedef struct CPUMMSRRANGE *PCPUMMSRRANGE;
typedef uint64_t STAMCOUNTER;
#endif
/** @defgroup grp_cpum_int Internals
* @ingroup grp_cpum
* @internal
* @{
*/
/** Flags and types for CPUM fault handlers
* @{ */
/** Type: Load DS */
#define CPUM_HANDLER_DS 1
/** Type: Load ES */
#define CPUM_HANDLER_ES 2
/** Type: Load FS */
#define CPUM_HANDLER_FS 3
/** Type: Load GS */
#define CPUM_HANDLER_GS 4
/** Type: IRET */
#define CPUM_HANDLER_IRET 5
/** Type mask. */
#define CPUM_HANDLER_TYPEMASK 0xff
/** If set EBP points to the CPUMCTXCORE that's being used. */
/** @} */
/** Use flags (CPUM::fUseFlags).
* (Don't forget to sync this with CPUMInternal.mac !)
* @{ */
/** Used the FPU, SSE or such stuff. */
#define CPUM_USED_FPU RT_BIT(0)
/** Used the FPU, SSE or such stuff since last we were in REM.
* REM syncing is clearing this, lazy FPU is setting it. */
/** The XMM state was manually restored. (AMD only) */
/** Host OS is using SYSENTER and we must NULL the CS. */
/** Host OS is using SYSENTER and we must NULL the CS. */
/** Debug registers are used by host and that DR7 and DR6 must be saved and
* disabled when switching to raw-mode. */
/** Records that we've saved the host DRx registers.
* In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
* since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
* registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
/** Used in ring-0 to indicate that we have loaded the hypervisor debug
* registers. */
/** Used in ring-0 to indicate that we have loaded the guest debug
* registers (DR0-3 and maybe DR6) for direct use by the guest.
* DR7 (and AMD-V DR6) are handled via the VMCB. */
/** Sync the FPU state on next entry (32->64 switcher only). */
/** Sync the debug state on next entry (32->64 switcher only). */
/** Sync the debug state on next entry (32->64 switcher only).
* Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
/** Set if the VM supports long-mode. */
/** @} */
/* Sanity check. */
#ifndef VBOX_FOR_DTRACE_LIB
# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
#endif
#endif
/** @name CPUM Saved State Version.
* @{ */
/** The current saved state version. */
#define CPUM_SAVED_STATE_VERSION 16
/** CPUID changes with explode forgetting to update the leaf count on
* restore, resulting in garbage being saved restoring+saving old states). */
#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
/** The saved state version before the CPUIDs changes. */
#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
/** The saved state version before using SSMR3PutStruct. */
#define CPUM_SAVED_STATE_VERSION_MEM 13
/** The saved state version before introducing the MSR size field. */
#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
#define CPUM_SAVED_STATE_VERSION_VER3_2 11
/** The saved state version of 3.0 and 3.1 trunk before the teleportation
* changes. */
#define CPUM_SAVED_STATE_VERSION_VER3_0 10
/** The saved state version for the 2.1 trunk before the MSR changes. */
#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
/** The saved state version of 2.0, used for backwards compatibility. */
#define CPUM_SAVED_STATE_VERSION_VER2_0 8
/** The saved state version of 1.6, used for backwards compatibility. */
#define CPUM_SAVED_STATE_VERSION_VER1_6 6
/** @} */
/**
* CPU features and quirks.
* This is mostly exploded CPUID info.
*/
typedef struct CPUMFEATURES
{
/** The CPU vendor (CPUMCPUVENDOR). */
/** The CPU family. */
/** The CPU model. */
/** The CPU stepping. */
/** The microarchitecture. */
#ifndef VBOX_FOR_DTRACE_LIB
#else
#endif
/** The maximum physical address with of the CPU. */
/** Alignment padding. */
/** Max size of the extended state (or FPU state if no XSAVE). */
/** Supports MSRs. */
/** Supports the page size extension (4/2 MB pages). */
/** Supports 36-bit page size extension (4 MB pages can map memory above
* 4GB). */
/** Supports physical address extension (PAE). */
/** Page attribute table (PAT) support (page level cache control). */
/** Supports the FXSAVE and FXRSTOR instructions. */
/** Supports the XSAVE and XRSTOR instructions. */
/** Supports MMX. */
/** Supports SSE. */
/** Supports SSE2. */
/** Supports SSE3. */
/** Supports SSSE3. */
/** Supports SSE4.1. */
/** Supports SSE4.2. */
/** Supports AVX. */
/** Supports AVX2. */
/** Supports AVX512 foundation. */
/** Supports RDTSC. */
/** First generation APIC. */
/** Second generation APIC. */
/** Hypervisor present. */
/** MWAIT & MONITOR instructions supported. */
/** MWAIT Extensions present. */
/** AMD64: Supports long mode. */
/** AMD64: No-execute page table bit. */
/** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
/** AMD64: Supports RDTSCP. */
/** Indicates that FPU instruction and data pointers may leak.
* This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
* is only saved and restored if an exception is pending. */
/** Alignment padding / reserved for future use. */
} CPUMFEATURES;
#ifndef VBOX_FOR_DTRACE_LIB
#endif
/** Pointer to a CPU feature structure. */
typedef CPUMFEATURES *PCPUMFEATURES;
/** Pointer to a const CPU feature structure. */
typedef CPUMFEATURES const *PCCPUMFEATURES;
/**
* CPU info
*/
typedef struct CPUMINFO
{
/** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
* instruction. Older hardware has been observed to ignore higher bits. */
/** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
/** The index of the first extended CPUID leaf in the array.
* Set to cCpuIdLeaves if none present. */
/** Alignment padding. */
/** How to handle unknown CPUID leaves. */
/** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
* CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
/** Scalable bus frequency used for reporting other frequencies. */
/** Pointer to the MSR ranges (ring-0 pointer). */
/** Pointer to the CPUID leaves (ring-0 pointer). */
/** Pointer to the MSR ranges (ring-3 pointer). */
/** Pointer to the CPUID leaves (ring-3 pointer). */
/** Pointer to the MSR ranges (raw-mode context pointer). */
/** Pointer to the CPUID leaves (raw-mode context pointer). */
} CPUMINFO;
/** Pointer to a CPU info structure. */
/** Pointer to a const CPU info structure. */
typedef CPUMINFO const *CPCPUMINFO;
/**
* The saved host CPU state.
*
* @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
* of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
*/
typedef struct CPUMHOSTCTX
{
/** General purpose register, selectors, flags and more
* @{ */
/** General purpose register ++
* { */
/*uint64_t rax; - scratch*/
/*uint64_t rcx; - scratch*/
/*uint64_t rdx; - scratch*/
/*uint64_t r8; - scratch*/
/*uint64_t r9; - scratch*/
/*uint64_t rip; - scratch*/
#endif
#if HC_ARCH_BITS == 32
/*uint32_t eax; - scratch*/
/*uint32_t ecx; - scratch*/
/*uint32_t edx; - scratch*/
/*uint32_t eip; - scratch*/
/* lss pair! */
#endif
/** @} */
/** Selector registers
* @{ */
/** @} */
/** Control registers.
* @{ */
/*uint32_t cr2; - scratch*/
/** @} */
/** Debug registers.
* @{ */
/** @} */
/** Global Descriptor Table register. */
/** Interrupt Descriptor Table register. */
/** The task register. */
/** The task register. */
/** The sysenter msr registers.
* This member is not used by the hypervisor context. */
/** MSRs
* @{ */
/** @} */
/* padding to get 64byte aligned size */
/** Control registers.
* @{ */
/*uint64_t cr2; - scratch*/
/** @} */
/** Debug registers.
* @{ */
/** @} */
/** Global Descriptor Table register. */
/** Interrupt Descriptor Table register. */
/** The task register. */
/** The task register. */
/** MSRs
* @{ */
/** @} */
/* padding to get 32byte aligned size */
# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
# else
# endif
#else
#endif
/** The XCR0 register. */
} CPUMHOSTCTX;
/** Pointer to the saved host CPU state. */
typedef CPUMHOSTCTX *PCPUMHOSTCTX;
/**
* CPUM Data (part of VM)
*/
typedef struct CPUM
{
/** Offset from CPUM to CPUMCPU for the first CPU. */
/** Use flags.
* These flags indicates which CPU features the host uses.
*/
/** CR4 mask */
struct
{
uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
} CR4;
/** The (more) portable CPUID level. */
/** Indicates that a state restore is pending.
* This is used to verify load order dependencies (PGM). */
bool fPendingRestore;
/** The standard set of CpuId leaves. */
/** The extended set of CpuId leaves. */
/** The centaur set of CpuId leaves. */
#if HC_ARCH_BITS == 32
#endif
/** Guest CPU info. */
/** Guest CPU feature information. */
/** Host CPU feature information. */
/** @name MSR statistics.
* @{ */
/** @} */
} CPUM;
/** Pointer to the CPUM instance data residing in the shared VM structure. */
/**
* CPUM Data (part of VMCPU)
*/
typedef struct CPUMCPU
{
/**
* Guest context.
* Aligned on a 64-byte boundary.
*/
/**
* Guest context - misc MSRs
* Aligned on a 64-byte boundary.
*/
/** Use flags.
* These flags indicates both what is to be used and what has been used.
*/
/** Changed flags.
* These flags indicates to REM (and others) which important guest
* registers which has been changed since last time the flags were cleared.
* See the CPUM_CHANGED_* defines for what we keep track of.
*/
/** Offset from CPUM to CPUMCPU. */
/** Temporary storage for the return code of the function called in the
* 32-64 switcher. */
/** The address of the APIC mapping, NULL if no APIC.
* Call CPUMR0SetLApic to update this before doing a world switch. */
/** Used by the world switcher code to store which vectors needs restoring on
* the way back. */
/** Set if the CPU has the X2APIC mode enabled.
* Call CPUMR0SetLApic to update this before doing a world switch. */
bool fX2Apic;
#else
#endif
/** Have we entered raw-mode? */
bool fRawEntered;
/** Have we entered the recompiler? */
bool fRemEntered;
/** Align the next member on a 64-bit boundrary. */
/** Saved host context. Only valid while inside RC or HM contexts.
* Must be aligned on a 64-byte boundary. */
/** Hypervisor context. Must be aligned on a 64-byte boundary. */
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
#endif
} CPUMCPU;
/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
#ifndef VBOX_FOR_DTRACE_LIB
PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
#ifdef IN_RING3
int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
int cpumR3MsrStrictInitChecks(void);
#endif
#ifdef IN_RC
#endif
#ifdef IN_RING0
#endif
#endif /* !VBOX_FOR_DTRACE_LIB */
/** @} */
#endif