HM.cpp revision 7dd6af5ec00fd26b42e750bc0fd6e97250b11cf2
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier * HM - Intel/AMD VM Hardware Support Manager.
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier * Copyright (C) 2006-2015 Oracle Corporation
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier * This file is part of VirtualBox Open Source Edition (OSE), as
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier * available from http://www.virtualbox.org. This file is free software;
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier * you can redistribute it and/or modify it under the terms of the GNU
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier * General Public License (GPL) as published by the Free Software
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier * Foundation, in version 2 as it comes in the "COPYING" file of the
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier/*******************************************************************************
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier* Header Files *
3b653205cf7bd3851befd0a9f6a3ded6e267c173Lennart Poettering*******************************************************************************/
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier/*******************************************************************************
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier* Global Variables *
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier*******************************************************************************/
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier# define EXIT_REASON(def, val, str) #def " - " #val " - " str
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier/** Exit reason descriptions for VT-x, used to describe statistics. */
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalierstatic const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold (MOV to CR8)."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR using LGDT, LIDT, SGDT, or SIDT."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR using LLDT, LTR, SLDT, or STR."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction.")
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier/** Exit reason descriptions for AMD-V, used to describe statistics. */
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalierstatic const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt-window exit."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
eda8090ba9abc7d00f30e2b4cb34273cde799704Thomas Hindoe Paaboel Andersen EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
eda8090ba9abc7d00f30e2b4cb34273cde799704Thomas Hindoe Paaboel Andersen EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
eda8090ba9abc7d00f30e2b4cb34273cde799704Thomas Hindoe Paaboel Andersen EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "Legacy FPU handling enabled; processor is frozen in an x87/mmx instruction waiting for an interrupt"),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_MWAIT ,139, "MWAIT instruction."),
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging fault."),
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier#endif /* VBOX_WITH_STATISTICS */
c182135d3af7a662739d16353e3cc630199aac24Ronny Chevalier#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek LogRel(("HM: " #featflag " (must be cleared)\n")); \
b31f535c9a7af9b5f5c4f5d4e52be9159af72127Zbigniew Jędrzejewski-Szmek if ((disallowed0) & (featflag)) \
059f6c42b744a18d0deec0c79a9e0730ec6c1c76Lennart Poettering LogRel(("HM: " #featflag " (must be set)\n")); \
return rc;
bool fHMForced;
#ifdef VBOX_WITH_RAW_MODE
AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
# if defined(RT_OS_DARWIN)
fHMForced = true;
AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
fHMForced = true;
fHMForced = true;
/** @cfgm{/HM/EnableNestedPaging, bool, false}
/** @cfgm{/HM/EnableLargePages, bool, false}
/** @cfgm{/HM/EnableVPID, bool, false}
/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
#ifdef VBOX_ENABLE_64_BITS_GUESTS
/** @cfgm{/HM/MaxResumeLoops, uint32_t}
rc = CFGMR3QueryU32Def(pCfgHM, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
/** @cfgm{/HM/UseVmxPreemptTimer, bool}
#ifdef RT_OS_LINUX
if (fHMForced)
LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
const char *pszMsg;
switch (rc)
case VERR_UNSUPPORTED_CPU:
case VERR_VMX_NO_VMX:
case VERR_SVM_NO_SVM:
case VERR_SVM_DISABLED:
if (!pszMsg)
return VINF_SUCCESS;
return VINF_SUCCESS;
#ifdef VBOX_WITH_STATISTICS
STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
int rc;
#ifdef VBOX_WITH_STATISTICS
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"/PROF/CPU%d/HM/PokeWaitFailed", i);
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"/PROF/CPU%d/HM/SwitchFromGC_1", i);
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"/PROF/CPU%d/HM/SwitchFromGC_2", i);
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"/PROF/CPU%d/HM/StatLoadGuestState", i);
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
"/PROF/CPU%d/HM/Switcher3264", i);
# ifdef HM_PROFILE_EXIT_DISPATCH
"/PROF/CPU%d/HM/ExitDispatch", i);
rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
#ifdef VBOX_WITH_STATISTICS
HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
#ifdef VBOX_WITH_STATISTICS
HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception back to the guest.");
HM_REG_COUNTER(&pVCpu->hm.s.StatPreemptPreempting, "/HM/CPU%d/Preempt/Preempting", "EMT has been preempted while in HM context.");
HM_REG_COUNTER(&pVCpu->hm.s.StatPreemptSaveHostState, "/HM/CPU%d/Preempt/SaveHostState", "Preemption caused us to resave host state.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
for (int j = 0; j < MAX_EXITREASON_STAT; j++)
if (papszDesc[j])
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
(j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
return VINF_SUCCESS;
switch (enmWhat)
case VMINITCOMPLETED_RING3:
case VMINITCOMPLETED_RING0:
return VINF_SUCCESS;
int rc;
return VINF_SUCCESS;
case VERR_VMX_NO_VMX:
case VERR_SVM_IN_USE:
case VERR_SVM_NO_SVM:
case VERR_SVM_DISABLED:
return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
return rc;
return rc;
int rc;
LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BOOL(MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo))));
LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BOOL(MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo))));
LogRel(("HM: MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
LogRel(("HM: MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
LogRel(("HM: MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
LogRel(("HM: MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
if (val)
* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
| X86_PDE4M_G;
rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
LogRel(("HM: VMX-preemption timer enabled (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
return VINF_SUCCESS;
LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
if (fSvmFeatures)
return VINF_SUCCESS;
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
case PGMMODE_32_BIT:
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
AssertFailed();
VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
#ifdef VMX_USE_CACHED_VMCS_ACCESSES
#ifdef VBOX_WITH_STATISTICS
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
return VINF_SUCCESS;
int rc;
#ifdef LOG_ENABLED
rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
#ifdef LOG_ENABLED
rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
return VINF_SUCCESS;
int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
return VINF_SUCCESS;
/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
return rc;
return VINF_SUCCESS;
return VINF_SUCCESS;
if (pPatch)
return VINF_SUCCESS;
return VINF_SUCCESS;
/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
return VINF_SUCCESS;
return VINF_SUCCESS;
return VINF_SUCCESS;
if (pPatch)
return VINF_SUCCESS;
return VINF_SUCCESS;
bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
if (!fUsesEax)
if (!fUsesEax)
if (!fUsesEax)
*(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
#ifdef LOG_ENABLED
rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
*(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
return VINF_SUCCESS;
return VINF_SUCCESS;
return rc;
AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P | X86DESCATTR_UNUSABLE))
AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
return VINF_EM_RESCHEDULE_REM;
return VINF_SUCCESS;
/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
* The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
if (fSupportsRealMode)
if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
|| CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
/* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
if (fSupportsRealMode)
/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
return VERR_NOT_FOUND;
switch (enmType)
case HMPENDINGIO_PORT_READ:
&u32Val,
case HMPENDINGIO_PORT_WRITE:
return rcStrict;
switch (iStatusCode)
else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
case VERR_VMX_UNEXPECTED_EXIT:
case VERR_SVM_UNKNOWN_EXIT:
case VERR_SVM_UNEXPECTED_EXIT:
LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
int rc;
/** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
#ifdef VBOX_HM_WITH_GUEST_PATCHING
return VINF_SUCCESS;
int rc;
#ifdef VBOX_HM_WITH_GUEST_PATCHING
return VINF_SUCCESS;