HM.cpp revision 56fd905bdc111f69ed81917abc2bb0aa0c6edb80
/* $Id$ */
/** @file
*/
/*
* Copyright (C) 2006-2013 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_HM
#ifdef VBOX_WITH_REM
#endif
#include "HMInternal.h"
#include <iprt/asm-amd64-x86.h>
/*******************************************************************************
* Global Variables *
*******************************************************************************/
#ifdef VBOX_WITH_STATISTICS
# define EXIT_REASON_NIL() NULL
/** Exit reason descriptions for VT-x, used to describe statistics. */
static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
{
EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold. Guest attempted to execute MOV to CR8."),
EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest attempted to access memory at a physical address on the APIC-access page."),
EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest attempted to execute LGDT, LIDT, SGDT, or SIDT."),
EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest attempted to execute LLDT, LTR, SLDT, or STR."),
EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
};
/** Exit reason descriptions for AMD-V, used to describe statistics. */
static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
{
EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "Legacy FPU handling enabled; processor is frozen in an x87/mmx instruction waiting for an interrupt"),
};
#endif /* VBOX_WITH_STATISTICS */
do { \
else \
if ((disallowed0) & (featflag)) \
} while (0)
do { \
else \
} while (0)
do { \
} while (0)
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
/**
* Initializes the HM.
*
* This reads the config and check whether VT-x or AMD-V hardware is available
* if configured to use it. This is one of the very first components to be
* initialized after CFGM, so that we can fall back to raw-mode early in the
* initialization process.
*
* Note that a lot of the set up work is done in ring-0 and thus postponed till
* the ring-3 and ring-0 callback to HMR3InitCompleted.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*
* @remarks Be careful with what we call here, since most of the VMM components
* are uninitialized.
*/
{
LogFlow(("HMR3Init\n"));
/*
* Assert alignment and sizes.
*/
/*
* Register the saved state data unit.
*/
if (RT_FAILURE(rc))
return rc;
/*
* Misc initialisation.
*/
//pVM->hm.s.vmx.fSupported = false;
//pVM->hm.s.svm.fSupported = false;
//pVM->hm.s.vmx.fEnabled = false;
//pVM->hm.s.svm.fEnabled = false;
//pVM->hm.s.fNestedPaging = false;
/*
* Read configuration.
*/
* Forces hardware virtualization, no falling back on raw-mode. HM must be
* enabled, i.e. /HMEnabled must be true. */
bool fHMForced;
#ifdef VBOX_WITH_RAW_MODE
AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
# if defined(RT_OS_DARWIN)
if (pVM->fHMEnabled)
fHMForced = true;
# endif
AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
fHMForced = true;
#else /* !VBOX_WITH_RAW_MODE */
fHMForced = true;
#endif /* !VBOX_WITH_RAW_MODE */
/** @cfgm{/HM/EnableNestedPaging, bool, false}
* Enables nested paging (aka extended page tables). */
* Enables the VT-x unrestricted execution feature. */
/** @cfgm{/HM/EnableLargePages, bool, false}
* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
* page table walking and maybe better TLB hit rate in some cases. */
/** @cfgm{/HM/EnableVPID, bool, false}
* Enables the VT-x VPID feature. */
/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
* Enables TPR patching for 32-bit windows guests with IO-APIC. */
/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
* Enables AMD64 cpu features.
* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
* already have the support. */
#ifdef VBOX_ENABLE_64_BITS_GUESTS
#else
#endif
* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
* global init for each host CPU. If false, we do local init each time we wish
* to execute guest code.
*
* Default is false for Mac OS X and Windows due to the higher risk of conflicts
* with other hypervisors.
*/
#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
false
#else
true
#endif
);
/** @cfgm{/HM/MaxResumeLoops, uint32_t}
* The number of times to resume guest execution before we forcibly return to
* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
* determines the default value. */
rc = CFGMR3QueryU32Def(pCfgHM, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
/*
* Check if VT-x or AMD-v support according to the users wishes.
*/
/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
* VERR_SVM_IN_USE. */
if (pVM->fHMEnabled)
{
if (RT_SUCCESS(rc))
{
if (fCaps & SUPVTCAPS_AMD_V)
else if (fCaps & SUPVTCAPS_VT_X)
{
rc = SUPR3QueryVTxSupported();
if (RT_SUCCESS(rc))
else
{
#ifdef RT_OS_LINUX
const char *pszMinReq = " Linux 2.6.13 or newer required!";
#else
const char *pszMinReq = "";
#endif
if (fHMForced)
/* Fall back to raw-mode. */
LogRel(("HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
pVM->fHMEnabled = false;
}
}
else
AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
/*
* Do we require a little bit or raw-mode for 64-bit guest execution?
*/
&& pVM->fHMEnabled
}
else
{
const char *pszMsg;
switch (rc)
{
case VERR_UNSUPPORTED_CPU:
pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained.";
break;
case VERR_VMX_NO_VMX:
pszMsg = "VT-x is not available.";
break;
pszMsg = "VT-x is disabled in the BIOS (or by the host OS).";
break;
case VERR_SVM_NO_SVM:
pszMsg = "AMD-V is not available.";
break;
case VERR_SVM_DISABLED:
pszMsg = "AMD-V is disabled in the BIOS (or by the host OS).";
break;
default:
break;
}
if (!pszMsg)
/* Fall back to raw-mode. */
pVM->fHMEnabled = false;
}
}
/* It's now OK to use the predicate function. */
pVM->fHMEnabledFixed = true;
return VINF_SUCCESS;
}
/**
* Initializes the per-VCPU HM.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
LogFlow(("HMR3InitCPU\n"));
if (!HMIsEnabled(pVM))
return VINF_SUCCESS;
{
}
#ifdef VBOX_WITH_STATISTICS
STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
#endif
/*
* Statistics.
*/
{
int rc;
#ifdef VBOX_WITH_STATISTICS
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Profiling of RTMpPokeCpu",
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Profiling of poke wait",
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Profiling of poke wait when RTMpPokeCpu fails",
"/PROF/CPU%d/HM/PokeWaitFailed", i);
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Profiling of VMXR0RunGuestCode entry",
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Profiling of VMXR0RunGuestCode exit part 1",
"/PROF/CPU%d/HM/SwitchFromGC_1", i);
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Profiling of VMXR0RunGuestCode exit part 2",
"/PROF/CPU%d/HM/SwitchFromGC_2", i);
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"I/O",
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"MOV CRx",
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Exceptions, NMIs",
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Profiling of VMXR0LoadGuestState",
"/PROF/CPU%d/HM/StatLoadGuestState", i);
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
"/PROF/CPU%d/HM/Switcher3264", i);
# endif
# ifdef HM_PROFILE_EXIT_DISPATCH
STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
"/PROF/CPU%d/HM/ExitDispatch", i);
# endif
#endif
# define HM_REG_COUNTER(a, b, desc) \
rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
#ifdef VBOX_WITH_STATISTICS
HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) execption.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume", "Maximum VMRESUME inner-loop counter reached.");
#endif
#ifdef VBOX_WITH_STATISTICS
HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception back to the guest.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Guest is in catchup mode, intercept TSC accesses.");
HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow", "TSC offset overflow, fallback to intercept TSC accesses.");
HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
#endif
{
STAMUNIT_OCCURENCES, "Profiling of CRx writes",
STAMUNIT_OCCURENCES, "Profiling of CRx reads",
}
if (RT_SUCCESS(rc))
{
const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
for (int j = 0; j < MAX_EXITREASON_STAT; j++)
{
if (papszDesc[j])
{
}
}
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
}
# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
# else
# endif
rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
# else
# endif
for (unsigned j = 0; j < 255; j++)
{
STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
"Injected event.",
(j < 0x20) ? "/HM/CPU%d/EventInject/Event/Trap/%02X" : "/HM/CPU%d/EventInject/Event/IRQ/%02X", i, j);
}
#endif /* VBOX_WITH_STATISTICS */
}
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
/*
* Magic marker for searching in crash dumps.
*/
{
}
#endif
return VINF_SUCCESS;
}
/**
* Called when a init phase has completed.
*
* @returns VBox status code.
* @param pVM The VM.
* @param enmWhat The phase that completed.
*/
{
switch (enmWhat)
{
case VMINITCOMPLETED_RING3:
return hmR3InitCPU(pVM);
case VMINITCOMPLETED_RING0:
return hmR3InitFinalizeR0(pVM);
default:
return VINF_SUCCESS;
}
}
/**
* Turns off normal raw mode features.
*
* @param pVM Pointer to the VM.
*/
{
/* Reinit the paging mode to force the new shadow mode. */
{
}
}
/**
* Initialize VT-x or AMD-V.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
int rc;
if (!HMIsEnabled(pVM))
return VINF_SUCCESS;
/*
* Hack to allow users to work around broken BIOSes that incorrectly set
* EFER.SVME, which makes us believe somebody else is already using AMD-V.
*/
&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
{
LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
}
/*
* Report ring-0 init errors.
*/
{
{
case VERR_VMX_NO_VMX:
case VERR_SVM_IN_USE:
case VERR_SVM_NO_SVM:
case VERR_SVM_DISABLED:
}
return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
}
/*
* Enable VT-x or AMD-V on all host CPUs.
*/
if (RT_FAILURE(rc))
{
return rc;
}
/*
* No TPR patching is required when the IO-APIC is not enabled for this VM.
* (Main should have taken care of this already)
*/
{
}
/*
* Do the vendor specific initalization .
* .
* Note! We disable release log buffering here since we're doing relatively .
* lot of logging and doesn't want to hit the disk with each LogRel .
* statement.
*/
else
return rc;
}
/**
* Finish VT-x initialization (after ring-0 init).
*
* @returns VBox status code.
* @param pVM The cross context VM structure.
*/
{
int rc;
LogRel(("HM: Using VT-x implementation 2.0!\n"));
LogRel(("HM: VMCS size = %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
LogRel(("HM: Dual-monitor treatment support = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.msr.vmx_basic_info)));
{
}
{
}
if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
{
LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x\n",
}
else
{
LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
}
LogRel(("HM: MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT = %RTbool\n", !!MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(pVM->hm.s.vmx.msr.vmx_misc)));
LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
LogRel(("HM: MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM = %RTbool\n", !!MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(pVM->hm.s.vmx.msr.vmx_misc)));
LogRel(("HM: MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2 = %RTbool\n", !!MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(pVM->hm.s.vmx.msr.vmx_misc)));
LogRel(("HM: MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO = %RTbool\n", !!MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(pVM->hm.s.vmx.msr.vmx_misc)));
LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
/* Paranoia */
LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(pVM->hm.s.vmx.msr.vmx_vmcs_enum)));
if (val)
{
}
{
}
/*
* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
*/
if ( !(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
{
LogRel(("HM: RDTSCP disabled.\n"));
}
/* Unrestricted guest execution also requires EPT. */
{
}
{
/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
if (RT_SUCCESS(rc))
{
/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
esp. Figure 20-5.*/
/* Bit set to 0 means software interrupts are redirected to the
8086 program interrupt handler rather than switching to
protected-mode handler. */
memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
/* Allow all port IO, so that port IO instructions do not cause
exceptions and would instead cause a VM-exit (based on VT-x's
IO bitmap which we currently configure to always cause an exit). */
/*
* Construct a 1024 element page directory with 4 MB pages for
* the identity mapped page table used in real and protected mode
* without paging with EPT.
*/
pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
{
| X86_PDE4M_G;
}
/* We convert it here every time as pci regions could be reconfigured. */
}
else
{
/** @todo This cannot possibly work, there are other places which assumes
* this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
* a failure case. */
}
}
/*
* Call ring-0 to set up the VM.
*/
if (rc != VINF_SUCCESS)
{
{
}
}
LogRel(("HM: VMX enabled!\n"));
/*
* Change the CPU features.
*/
{
#if 0 /** @todo r=bird: This ain't making any sense whatsoever. */
#if RT_ARCH_X86
LogRel(("NX is only supported for 64-bit guests!\n"));
#endif
#endif
}
/* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
(we reuse the host EFER in the switcher). */
/** @todo this needs to be fixed properly!! */
else
LogRel(("HM: NX not supported by the host.\n"));
/*
* Log configuration details.
*/
? "HM: Guest support: 32-bit and 64-bit.\n"
: "HM: Guest support: 32-bit only.\n"));
{
LogRel(("HM: Nested paging enabled!\n"));
LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
else
LogRel(("HM: Unrestricted guest execution enabled!\n"));
#if HC_ARCH_BITS == 64
{
/* Use large (2 MB) pages for our EPT PDEs where possible. */
PGMSetLargePageUsage(pVM, true);
LogRel(("HM: Large page support enabled!\n"));
}
#endif
}
else
{
LogRel(("HM: VPID enabled!\n"));
LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n"));
LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
else
}
LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
/*
* Check for preemption timer config override and log the state of it.
*/
{
}
LogRel(("HM: VMX-preemption timer enabled (cPreemptTimerShift=%u).\n", pVM->hm.s.vmx.cPreemptTimerShift));
else
LogRel(("HM: VMX-preemption timer disabled.\n"));
return VINF_SUCCESS;
}
/**
* Finish AMD-V initialization (after ring-0 init).
*
* @returns VBox status code.
* @param pVM The cross context VM structure.
*/
{
LogRel(("HM: Using AMD-V implementation 2.0!\n"));
LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
/*
* Enumerate AMD-V features.
*/
{
};
for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
{
}
if (fSvmFeatures)
/*
* Adjust feature(s).
*/
/*
* Call ring-0 to set up the VM.
*/
if (rc != VINF_SUCCESS)
{
}
LogRel(("HM: AMD-V enabled!\n"));
{
LogRel(("HM: Nested paging enabled!\n"));
/*
* Enable large pages (2 MB) if applicable.
*/
#if HC_ARCH_BITS == 64
{
PGMSetLargePageUsage(pVM, true);
LogRel(("HM: Large page support enabled!\n"));
}
#endif
}
/*
* Change the CPU features.
*/
{
}
/* Turn on NXE if PAE has been enabled. */
? "HM: Guest support: 32-bit and 64-bit.\n"
: "HM: Guest support: 32-bit only.\n"));
return VINF_SUCCESS;
}
/**
* Applies relocations to data and code managed by this
* component. This function will be called at init and
* whenever the VMM need to relocate it self inside the GC.
*
* @param pVM The VM.
*/
{
/* Fetch the current paging mode during the relocate callback during state loading. */
{
{
}
}
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
if (HMIsEnabled(pVM))
{
switch (PGMGetHostMode(pVM))
{
case PGMMODE_32_BIT:
break;
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
break;
default:
AssertFailed();
break;
}
}
#endif
return;
}
/**
* Notification callback which is called whenever there is a chance that a CR3
* value might have changed.
*
* This is called by PGM.
*
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param enmShadowMode New shadow paging mode.
* @param enmGuestMode New guest paging mode.
*/
VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
{
/* Ignore page mode changes during state loading. */
return;
/*
* If the guest left protected mode VMX execution, we'll have to be
*/
if (enmGuestMode == PGMMODE_REAL)
{
Log(("HMR3PagingModeChanged indicates real mode execution\n"));
}
/** @todo r=ramshankar: Disabling for now. If nothing breaks remove it
* eventually. (Test platforms that use the cache ofc). */
#if 0
#ifdef VMX_USE_CACHED_VMCS_ACCESSES
/* Reset the contents of the read cache. */
#endif
#endif
}
/**
* Terminates the HM.
*
* Termination means cleaning up and freeing all resources,
* the VM itself is, at this point, powered off or suspended.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
{
}
return 0;
}
/**
* Terminates the per-VCPU HM.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
{
#ifdef VBOX_WITH_STATISTICS
{
}
{
}
#endif
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
#endif
}
return 0;
}
/**
* Resets a virtual CPU.
*
* Used by HMR3Reset and CPU hot plugging.
*
* @param pVCpu The CPU to reset.
*/
{
/* On first entry we'll sync everything. */
/* Reset the contents of the read cache. */
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
/* Magic marker for searching in crash dumps. */
#endif
}
/**
* The VM is being reset.
*
* needs to be removed.
*
* @param pVM Pointer to the VM.
*/
{
LogFlow(("HMR3Reset:\n"));
if (HMIsEnabled(pVM))
{
}
/* Clear all patch information. */
}
/**
* Callback to patch a TPR instruction (vmmcall or mov cr8).
*
* @returns VBox strict status code.
* @param pVM Pointer to the VM.
* @param pVCpu The VMCPU for the EMT we're being called on.
* @param pvUser Unused.
*/
{
/* Only execute the handler on the VCPU the original patch request was issued. */
return VINF_SUCCESS;
Log(("hmR3RemovePatches\n"));
{
int rc;
#ifdef LOG_ENABLED
char szOutput[256];
rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
if (RT_SUCCESS(rc))
#endif
/* Check if the instruction is still the same. */
if (rc != VINF_SUCCESS)
{
continue; /* swapped out or otherwise removed; skip it. */
}
{
continue; /* skip it. */
}
#ifdef LOG_ENABLED
rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
if (RT_SUCCESS(rc))
#endif
}
return VINF_SUCCESS;
}
/**
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param idCpu VCPU to execute hmR3RemovePatches on.
* @param pPatchMem Patch memory range.
* @param cbPatchMem Size of the memory range.
*/
{
int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
return VINF_SUCCESS;
}
/**
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pPatchMem Patch memory range.
* @param cbPatchMem Size of the memory range.
*/
{
{
/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
return rc;
}
}
/**
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pPatchMem Patch memory range.
* @param cbPatchMem Size of the memory range.
*/
{
/* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
return VINF_SUCCESS;
}
/**
* Callback to patch a TPR instruction (vmmcall or mov cr8).
*
* @returns VBox strict status code.
* @param pVM Pointer to the VM.
* @param pVCpu The VMCPU for the EMT we're being called on.
* @param pvUser User specified CPU context.
*
*/
{
/*
* Only execute the handler on the VCPU the original patch request was
* issued. (The other CPU(s) might not yet have switched to protected
* mode, nor have the correct memory context.)
*/
return VINF_SUCCESS;
/*
* We're racing other VCPUs here, so don't try patch the instruction twice
* and make sure there is still room for our patch record.
*/
if (pPatch)
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
/*
* Disassembler the instruction and get cracking.
*/
if ( rc == VINF_SUCCESS
&& cbOp >= 3)
{
{
/* write. */
{
}
else
{
}
}
else
{
/*
* TPR Read.
*
* Found:
* mov eax, dword [fffe0080] (5 bytes)
* Check if next instruction is:
* shr eax, 4
*/
if ( rc == VINF_SUCCESS
{
/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
access CR8 in 32-bit mode and not cause a #VMEXIT. */
/* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
abInstr[0] = 0xF0;
}
else
{
}
}
return VINF_SUCCESS;
}
/*
* Save invalid patch, so we will not try again.
*/
Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
return VINF_SUCCESS;
}
/**
* Callback to patch a TPR instruction (jump to generated code).
*
* @returns VBox strict status code.
* @param pVM Pointer to the VM.
* @param pVCpu The VMCPU for the EMT we're being called on.
* @param pvUser User specified CPU context.
*
*/
{
/*
* Only execute the handler on the VCPU the original patch request was
* issued. (The other CPU(s) might not yet have switched to protected
* mode, nor have the correct memory context.)
*/
return VINF_SUCCESS;
/*
* We're racing other VCPUs here, so don't try patch the instruction twice
* and make sure there is still room for our patch record.
*/
if (pPatch)
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
/*
* Disassemble the instruction and get cracking.
*/
if ( rc == VINF_SUCCESS
&& cbOp >= 5)
{
{
/*
* TPR write:
*
* push ECX [51]
* push EDX [52]
* push EAX [50]
* xor EDX,EDX [31 D2]
* mov EAX,EAX [89 C0]
* or
* mov EAX,0000000CCh [B8 CC 00 00 00]
* mov ECX,0C0000082h [B9 82 00 00 C0]
* wrmsr [0F 30]
* pop EAX [58]
* pop EDX [5A]
* pop ECX [59]
* jmp return_address [E9 return_address]
*
*/
bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
if (!fUsesEax)
{
if (!fUsesEax)
{
}
}
else
{
}
if (!fUsesEax)
}
else
{
/*
* TPR read:
*
* push ECX [51]
* push EDX [52]
* push EAX [50]
* mov ECX,0C0000082h [B9 82 00 00 C0]
* rdmsr [0F 32]
* mov EAX,EAX [89 C0]
* pop EAX [58]
* pop EDX [5A]
* pop ECX [59]
* jmp return_address [E9 return_address]
*
*/
{
}
}
*(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
off += sizeof(RTRCUINTPTR);
{
/* Write new code to the patch buffer. */
#ifdef LOG_ENABLED
{
char szOutput[256];
rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
if (RT_SUCCESS(rc))
else
}
#endif
*(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
/* Overwrite the TPR instruction with a jump. */
return VINF_SUCCESS;
}
Log(("Ran out of space in our patch buffer!\n"));
}
else
Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
/*
* Save invalid patch, so we will not try again.
*/
return VINF_SUCCESS;
}
/**
* Attempt to patch TPR mmio instructions.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest CPU context.
*/
{
return rc;
}
/**
* Checks if a code selector (CS) is suitable for execution
* within VMX when unrestricted execution isn't available.
*
* @returns true if selector is suitable for VMX, otherwise
* false.
* @param pSel Pointer to the selector to check (CS).
* uStackDpl The DPL of the stack segment.
*/
{
bool rc = false;
do
{
/* Segment must be accessed. */
break;
/* Segment must be a code segment. */
break;
/* The S bit must be set. */
break;
{
/* For conforming segments, CS.DPL must be <= SS.DPL. */
break;
}
else
{
/* For non-conforming segments, CS.DPL must equal SS.DPL. */
break;
}
/* Segment must be present. */
break;
/* G bit must be set if any high limit bits are set. */
break;
/* G bit must be clear if any low limit bits are clear. */
break;
rc = true;
} while (0);
return rc;
}
/**
* execution within VMX when unrestricted execution isn't
* available.
*
* @returns true if selector is suitable for VMX, otherwise
* false.
* @param pSel Pointer to the selector to check
*/
{
bool rc = false;
/* If attributes are all zero, consider the segment unusable and therefore OK.
* This logic must be in sync with HMVMXR0.cpp!
*/
return true;
do
{
/* Segment must be accessed. */
break;
/* Code segments must also be readable. */
break;
/* The S bit must be set. */
break;
/* Except for conforming segments, DPL >= RPL. */
break;
/* Segment must be present. */
break;
/* G bit must be set if any high limit bits are set. */
break;
/* G bit must be clear if any low limit bits are clear. */
break;
rc = true;
} while (0);
return rc;
}
/**
* Checks if the stack selector (SS) is suitable for execution
* within VMX when unrestricted execution isn't available.
*
* @returns true if selector is suitable for VMX, otherwise
* false.
* @param pSel Pointer to the selector to check (SS).
*/
{
bool rc = false;
/* If attributes are all zero, consider the segment unusable and therefore OK.
* This logic must be in sync with HMVMXR0.cpp!
*/
return true;
do
{
/* Segment must be accessed. */
break;
/* Segment must be writable. */
break;
/* Segment must not be a code segment. */
break;
/* The S bit must be set. */
break;
/* DPL must equal RPL. */
break;
/* Segment must be present. */
break;
/* G bit must be set if any high limit bits are set. */
break;
/* G bit must be clear if any low limit bits are clear. */
break;
rc = true;
} while (0);
return rc;
}
/**
* Force execution of the current IO code in the recompiler.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pCtx Partial VM execution context.
*/
{
Log(("HMR3EmulateIoBlock\n"));
/* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
if (HMCanEmulateIoBlockEx(pCtx))
{
Log(("HMR3EmulateIoBlock -> enabled\n"));
return VINF_EM_RESCHEDULE_REM;
}
return VINF_SUCCESS;
}
/**
* Checks if we can currently use hardware accelerated raw mode.
*
* @returns true if we can currently use hardware acceleration, otherwise false.
* @param pVM Pointer to the VM.
* @param pCtx Partial VM execution context.
*/
{
/* If we're still executing the IO code, then return false. */
return false;
/* AMD-V supports real & protected mode with or without paging. */
{
return true;
}
/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
{
/*
* The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
* guest execution feature i missing (VT-x only).
*/
if (fSupportsRealMode)
{
if (CPUMIsGuestInRealModeEx(pCtx))
{
/* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
* bases and limits, i.e. limit must be 64K and base must be selector * 16.
* If this is not true, we cannot execute real mode as V86 and have to fall
* back to emulation.
*/
{
return false;
}
{
return false;
}
}
else
{
/* Verify the requirements for executing code in protected
mode. VT-x can't handle the CPU state right after a switch
from real to protected mode. (all sorts of RPL & DPL assumptions). */
{
/** @todo If guest is in V86 mode, these checks should be different! */
{
return false;
}
{
return false;
}
}
/* VT-x also chokes on invalid TR or LDTR selectors (minix). */
{
{
return false;
}
{
return false;
}
}
}
}
else
{
if ( !CPUMIsGuestInLongModeEx(pCtx)
{
if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
|| CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
return false;
/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
return false;
/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
/* Windows XP; switch to protected mode; all selectors are marked not present in the
* hidden registers (possible recompiler bug; see load_seg_vm) */
return false;
return false;
/* Windows XP: possible same as above, but new recompiler requires new heuristics?
VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
/** @todo This check is actually wrong, it doesn't take the direction of the
* stack segment into account. But, it does the job for now. */
return false;
}
}
}
{
/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
/* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
mask &= ~X86_CR0_NE;
if (fSupportsRealMode)
{
/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
}
else
{
/* We support protected mode without paging using identity mapping. */
mask &= ~X86_CR0_PG;
}
return false;
/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
return false;
/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
mask &= ~X86_CR4_VMXE;
return false;
/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
return false;
return true;
}
return false;
}
/**
* Checks if we need to reschedule due to VMM device heap changes.
*
* @returns true if a reschedule is required, otherwise false.
* @param pVM Pointer to the VM.
* @param pCtx VM execution context.
*/
{
/*
* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
* when the unrestricted guest execution feature is missing (VT-x only).
*/
&& !PDMVmmDevHeapIsEnabled(pVM))
{
return true;
}
return false;
}
/**
* Notification from EM about a rescheduling into hardware assisted execution
* mode.
*
* @param pVCpu Pointer to the current VMCPU.
*/
{
}
/**
* Notification from EM about returning from instruction emulation (REM / EM).
*
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* Checks if we are currently using hardware accelerated raw mode.
*
* @returns true if hardware acceleration is being used, otherwise false.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* External interface for querying whether hardware accelerated raw mode is
* enabled.
*
* @returns true if VT-x or AMD-V is being used, otherwise false.
* @param pUVM The user mode VM handle.
* @sa HMIsEnabled, HMIsEnabledNotMacro.
*/
{
UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
VM_ASSERT_VALID_EXT_RETURN(pVM, false);
}
/**
* External interface for querying whether VT-x is being used.
*
* @returns true if VT-x is being used, otherwise false.
* @param pUVM The user mode VM handle.
* @sa HMR3IsSvmEnabled, HMIsEnabled
*/
{
UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
VM_ASSERT_VALID_EXT_RETURN(pVM, false);
&& pVM->fHMEnabled;
}
/**
* External interface for querying whether AMD-V is being used.
*
* @returns true if VT-x is being used, otherwise false.
* @param pUVM The user mode VM handle.
* @sa HMR3IsVmxEnabled, HMIsEnabled
*/
{
UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
VM_ASSERT_VALID_EXT_RETURN(pVM, false);
&& pVM->fHMEnabled;
}
/**
* Checks if we are currently using nested paging.
*
* @returns true if nested paging is being used, otherwise false.
* @param pUVM The user mode VM handle.
*/
{
UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
VM_ASSERT_VALID_EXT_RETURN(pVM, false);
}
/**
* Checks if we are currently using VPID in VT-x mode.
*
* @returns true if VPID is being used, otherwise false.
* @param pUVM The user mode VM handle.
*/
{
UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
VM_ASSERT_VALID_EXT_RETURN(pVM, false);
}
/**
* Checks if we are currently using VT-x unrestricted execution,
* aka UX.
*
* @returns true if UX is being used, otherwise false.
* @param pUVM The user mode VM handle.
*/
{
UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
VM_ASSERT_VALID_EXT_RETURN(pVM, false);
}
/**
* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
*
* @returns true if an internal event is pending, otherwise false.
* @param pVM Pointer to the VM.
*/
{
}
/**
* Checks if the VMX-preemption timer is being used.
*
* @returns true if the VMX-preemption timer is being used, otherwise false.
* @param pVM Pointer to the VM.
*/
{
return HMIsEnabled(pVM)
}
/**
* Restart an I/O instruction that was refused in ring-0
*
* @returns Strict VBox status code. Informational status codes other than the one documented
* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
* @retval VINF_SUCCESS Success.
* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
* status code must be passed on to EM.
* @retval VERR_NOT_FOUND if no pending I/O instruction.
*
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest CPU context.
*/
{
|| enmType == HMPENDINGIO_INVALID)
return VERR_NOT_FOUND;
switch (enmType)
{
case HMPENDINGIO_PORT_READ:
{
&u32Val,
if (IOM_SUCCESS(rcStrict))
{
/* Write back to the EAX register. */
}
break;
}
case HMPENDINGIO_PORT_WRITE:
if (IOM_SUCCESS(rcStrict))
break;
default:
}
if (IOM_SUCCESS(rcStrict))
{
/*
* Check for I/O breakpoints.
*/
if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
|| DBGFBpIsHwIoArmed(pVM))
{
if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
/* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
}
}
return rcStrict;
}
/**
* log release message.
*
* @param pVM Pointer to the VM.
* @param iStatusCode VBox status code.
*/
{
{
switch (iStatusCode)
{
break;
LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
break;
LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
{
}
else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
{
#endif
}
/** @todo Log VM-entry event injection control fields
* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
break;
break;
case VERR_SVM_UNKNOWN_EXIT:
case VERR_SVM_UNEXPECTED_EXIT:
{
break;
}
}
}
{
LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
}
}
/**
* Execute state save operation.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pSSM SSM operation handle.
*/
{
int rc;
Log(("hmR3Save:\n"));
{
/*
* Save the basic bits - fortunately all the other things can be resynced on load.
*/
/** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
* perhaps not even that (the initial value of @c true is safe. */
}
#ifdef VBOX_HM_WITH_GUEST_PATCHING
/* Store all the guest patch records too. */
{
}
#endif
return VINF_SUCCESS;
}
/**
* Execute state load operation.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pSSM SSM operation handle.
* @param uVersion Data layout version.
* @param uPass The data pass.
*/
{
int rc;
Log(("hmR3Load:\n"));
/*
* Validate version.
*/
if ( uVersion != HM_SSM_VERSION
&& uVersion != HM_SSM_VERSION_2_0_X)
{
}
{
if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
{
/** @todo See note in hmR3Save(). */
}
}
#ifdef VBOX_HM_WITH_GUEST_PATCHING
{
/* Fetch all TPR patch records. */
{
Log(("hmR3Load: patch %d\n", i));
}
}
#endif
return VINF_SUCCESS;
}