HM.cpp revision 4a368ed512042f7f15953926ba5614172e91c969
/* $Id$ */
/** @file
*/
/*
* Copyright (C) 2006-2013 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_HM
#ifdef VBOX_WITH_REM
#endif
#include "HMInternal.h"
#include <iprt/asm-amd64-x86.h>
/*******************************************************************************
* Global Variables *
*******************************************************************************/
#ifdef VBOX_WITH_STATISTICS
# define EXIT_REASON_NIL() NULL
/** Exit reason descriptions for VT-x, used to describe statistics. */
static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
{
EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold. Guest software executed MOV to CR8."),
EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
};
/** Exit reason descriptions for AMD-V, used to describe statistics. */
static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
{
EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
};
#endif /* VBOX_WITH_STATISTICS */
do { \
else \
if ((disallowed0) & (featflag)) \
} while (0)
do { \
} while (0)
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
/**
* Initializes the HM.
*
* This reads the config and check whether VT-x or AMD-V hardware is available
* if configured to use it. This is one of the very first components to be
* initialized after CFGM, so that we can fall back to raw-mode early in the
* initialization process.
*
* Note that a lot of the set up work is done in ring-0 and thus postponed till
* the ring-3 and ring-0 callback to HMR3InitCompleted.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*
* @remarks Be careful with what we call here, since most of the VMM components
* are uninitialized.
*/
{
LogFlow(("HMR3Init\n"));
/*
* Assert alignment and sizes.
*/
/* Some structure checks. */
/*
* Register the saved state data unit.
*/
if (RT_FAILURE(rc))
return rc;
/*
* Misc initialisation.
*/
//pVM->hm.s.vmx.fSupported = false;
//pVM->hm.s.svm.fSupported = false;
//pVM->hm.s.vmx.fEnabled = false;
//pVM->hm.s.svm.fEnabled = false;
//pVM->hm.s.fNestedPaging = false;
/*
* Read configuration.
*/
* Forces hardware virtualization, no falling back on raw-mode. HM must be
* enabled, i.e. /HMEnabled must be true. */
bool fHMForced;
#ifdef VBOX_WITH_RAW_MODE
AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
# if defined(RT_OS_DARWIN)
if (pVM->fHMEnabled)
fHMForced = true;
# endif
AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
fHMForced = true;
#else /* !VBOX_WITH_RAW_MODE */
fHMForced = true;
#endif /* !VBOX_WITH_RAW_MODE */
/** @cfgm{/HM/EnableNestedPaging, bool, false}
* Enables nested paging (aka extended page tables). */
/** @cfgm{/HM/EnableUnrestrictedExec, bool, true}
* Enables the VT-x unrestricted execution feature. */
/** @cfgm{/HM/EnableLargePages, bool, false}
* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
* page table walking and maybe better TLB hit rate in some cases. */
/** @cfgm{/HM/EnableVPID, bool, false}
* Enables the VT-x VPID feature. */
/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
* Enables TPR patching for 32-bit windows guests with IO-APIC. */
/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
* Enables AMD64 cpu features.
* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
* already have the support. */
#ifdef VBOX_ENABLE_64_BITS_GUESTS
#else
#endif
* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
* global init for each host CPU. If false, we do local init each time we wish
* to execute guest code.
*
* Default is false for Mac OS X and Windows due to the higher risk of conflicts
* with other hypervisors.
*/
#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
false
#else
true
#endif
);
/** @cfgm{/HM/MaxResumeLoops, uint32_t}
* The number of times to resume guest execution before we forcibly return to
* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
* determins the default value. */
rc = CFGMR3QueryU32Def(pCfgHM, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
/*
* Check if VT-x or AMD-v support according to the users wishes.
*/
/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
* VERR_SVM_IN_USE. */
if (pVM->fHMEnabled)
{
if (RT_SUCCESS(rc))
{
if (fCaps & SUPVTCAPS_AMD_V)
else if (fCaps & SUPVTCAPS_VT_X)
{
rc = SUPR3QueryVTxSupported();
if (RT_SUCCESS(rc))
else
{
#ifdef RT_OS_LINUX
const char *pszMinReq = " Linux 2.6.13 or newer required!";
#else
const char *pszMinReq = "";
#endif
if (fHMForced)
/* Fall back to raw-mode. */
LogRel(("HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
pVM->fHMEnabled = false;
}
}
else
AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
/*
* Do we require a little bit or raw-mode for 64-bit guest execution?
*/
&& pVM->fHMEnabled
}
else
{
const char *pszMsg;
switch (rc)
{
case VERR_UNSUPPORTED_CPU:
pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained.";
break;
case VERR_VMX_NO_VMX:
pszMsg = "VT-x is not available.";
break;
pszMsg = "VT-x is disabled in the BIOS (or by the host OS).";
break;
case VERR_SVM_NO_SVM:
pszMsg = "AMD-V is not available.";
break;
case VERR_SVM_DISABLED:
pszMsg = "AMD-V is disabled in the BIOS (or by the host OS).";
break;
default:
break;
}
if (!pszMsg)
/* Fall back to raw-mode. */
pVM->fHMEnabled = false;
}
}
/* It's now OK to use the predicate function. */
pVM->fHMEnabledFixed = true;
return VINF_SUCCESS;
}
/**
* Initializes the per-VCPU HM.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
LogFlow(("HMR3InitCPU\n"));
if (!HMIsEnabled(pVM))
return VINF_SUCCESS;
{
}
#ifdef VBOX_WITH_STATISTICS
STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
/*
* Statistics.
*/
{
int rc;
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Profiling of RTMpPokeCpu",
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Profiling of poke wait",
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Profiling of poke wait when RTMpPokeCpu fails",
"/PROF/CPU%d/HM/PokeWaitFailed", i);
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Profiling of VMXR0RunGuestCode entry",
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Profiling of VMXR0RunGuestCode exit part 1",
"/PROF/CPU%d/HM/SwitchFromGC_1", i);
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Profiling of VMXR0RunGuestCode exit part 2",
"/PROF/CPU%d/HM/SwitchFromGC_2", i);
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"I/O",
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"MOV CRx",
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Exceptions, NMIs",
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
"Profiling of VMXR0LoadGuestState",
"/PROF/CPU%d/HM/StatLoadGuestState", i);
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
"/PROF/CPU%d/HM/Switcher3264", i);
# endif
# ifdef HM_PROFILE_EXIT_DISPATCH
STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers",
"/PROF/CPU%d/HM/ExitDispatch", i);
# endif
# define HM_REG_COUNTER(a, b) \
rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of HM", b, i); \
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
#endif
{
STAMUNIT_OCCURENCES, "Profiling of CRx writes",
STAMUNIT_OCCURENCES, "Profiling of CRx reads",
}
if (RT_SUCCESS(rc))
{
const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
for (int j = 0; j < MAX_EXITREASON_STAT; j++)
{
if (papszDesc[j])
{
}
}
rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
}
# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
# else
# endif
rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
# else
# endif
for (unsigned j = 0; j < 255; j++)
{
STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
"Forwarded interrupts.",
}
}
#endif /* VBOX_WITH_STATISTICS */
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
/*
* Magic marker for searching in crash dumps.
*/
{
}
#endif
return VINF_SUCCESS;
}
/**
* Called when a init phase has completed.
*
* @returns VBox status code.
* @param pVM The VM.
* @param enmWhat The phase that completed.
*/
{
switch (enmWhat)
{
case VMINITCOMPLETED_RING3:
return hmR3InitCPU(pVM);
case VMINITCOMPLETED_RING0:
return hmR3InitFinalizeR0(pVM);
default:
return VINF_SUCCESS;
}
}
/**
* Turns off normal raw mode features.
*
* @param pVM Pointer to the VM.
*/
{
/* Reinit the paging mode to force the new shadow mode. */
{
}
}
/**
* Initialize VT-x or AMD-V.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
int rc;
if (!HMIsEnabled(pVM))
return VINF_SUCCESS;
/*
* Hack to allow users to work around broken BIOSes that incorrectly set
* EFER.SVME, which makes us believe somebody else is already using AMD-V.
*/
&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
{
LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
}
/*
* Report ring-0 init errors.
*/
{
{
case VERR_VMX_NO_VMX:
case VERR_SVM_IN_USE:
case VERR_SVM_NO_SVM:
case VERR_SVM_DISABLED:
}
return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
}
/*
* Enable VT-x or AMD-V on all host CPUs.
*/
if (RT_FAILURE(rc))
{
return rc;
}
/*
* No TPR patching is required when the IO-APIC is not enabled for this VM.
* (Main should have taken care of this already)
*/
{
}
/*
* Do the vendor specific initalization .
* .
* Note! We disable release log buffering here since we're doing relatively .
* lot of logging and doesn't want to hit the disk with each LogRel .
* statement.
*/
else
return rc;
}
/**
* Finish VT-x initialization (after ring-0 init).
*
* @returns VBox status code.
* @param pVM The cross context VM structure.
*/
{
int rc;
#ifndef VBOX_WITH_OLD_VTX_CODE
LogRel(("HM: Using VT-x implementation 2.0!\n"));
#endif
LogRel(("HM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
LogRel(("HM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
LogRel(("HM: Dual-monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
{
}
{
}
if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
else
LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x - erratum detected, using %x instead\n",
LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
/* Paranoia */
{
}
/*
* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
*/
{
LogRel(("HM: Disabled RDTSCP\n"));
}
/* Unrestricted guest execution also requires EPT. */
{
/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
if (RT_SUCCESS(rc))
{
/* The I/O bitmap starts right after the virtual interrupt redirection bitmap.
Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
esp. Figure 20-5.*/
/* Bit set to 0 means software interrupts are redirected to the
8086 program interrupt handler rather than switching to
protected-mode handler. */
memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
/* Allow all port IO, so that port IO instructions do not cause
exceptions and would instead cause a VM-exit (based on VT-x's
IO bitmap which we currently configure to always cause an exit). */
/*
* Construct a 1024 element page directory with 4 MB pages for
* the identity mapped page table used in real and protected mode
* without paging with EPT.
*/
pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
{
| X86_PDE4M_G;
}
/* We convert it here every time as pci regions could be reconfigured. */
}
else
{
/** @todo This cannot possibly work, there are other places which assumes
* this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
* a failure case. */
}
}
/*
* Call ring-0 to set up the VM.
*/
if (rc != VINF_SUCCESS)
{
LogRel(("HM: CPU[%ld] Last instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
}
LogRel(("HM: VMX enabled!\n"));
/*
* Change the CPU features.
*/
{
#if 0 /** @todo r=bird: This ain't making any sense whatsoever. */
#if RT_ARCH_X86
LogRel(("NX is only supported for 64-bit guests!\n"));
#endif
#endif
}
/* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
(we reuse the host EFER in the switcher). */
/** @todo this needs to be fixed properly!! */
else
LogRel(("HM: NX not supported by the host\n"));
/*
* Log configuration details.
*/
? "HM: Guest support: 32-bit and 64-bit.\n"
: "HM: Guest support: 32-bit only.\n"));
{
LogRel(("HM: Nested paging enabled!\n"));
LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
else
LogRel(("HM: Unrestricted guest execution enabled!\n"));
#if HC_ARCH_BITS == 64
{
/* Use large (2 MB) pages for our EPT PDEs where possible. */
PGMSetLargePageUsage(pVM, true);
LogRel(("HM: Large page support enabled!\n"));
}
#endif
}
else
{
LogRel(("HM: VPID enabled!\n"));
LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n"));
LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
else
}
LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
/*
* TPR patching status logging.
*/
{
{
LogRel(("HM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
}
else
{
/* TPR patching needs access to the MSR_K8_LSTAR msr. */
if ( u32Eax < 0x80000001
{
LogRel(("HM: TPR patching disabled (long mode not supported).\n"));
}
}
}
/*
* Check for preemption timer config override and log the state of it.
*/
{
}
LogRel(("HM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
return VINF_SUCCESS;
}
/**
* Finish AMD-V initialization (after ring-0 init).
*
* @returns VBox status code.
* @param pVM The cross context VM structure.
*/
{
/* Erratum 170 which requires a forced TLB flush for each world switch:
*
* All BH-G1/2 and DH-G1/2 models include a fix:
* Athlon X2: 0x6b 1/2
* 0x68 1/2
* Athlon 64: 0x7f 1
* 0x6f 2
* Sempron: 0x7f 1/2
* 0x6f 2
* 0x6c 2
* 0x7c 2
* Turion 64: 0x68 2
*
*/
if ( u32Family == 0xf
{
LogRel(("HM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
}
{
};
for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
{
}
if (fSvmFeatures)
/*
* Adjust feature(s).
*/
/*
* Call ring-0 to set up the VM.
*/
if (rc != VINF_SUCCESS)
{
}
LogRel(("HM: AMD-V enabled!\n"));
{
LogRel(("HM: Enabled nested paging!\n"));
/*
* Enable large pages (2 MB) if applicable.
*/
#if HC_ARCH_BITS == 64
{
PGMSetLargePageUsage(pVM, true);
LogRel(("HM: Large page support enabled!\n"));
}
#endif
}
/*
* Change the CPU features.
*/
{
}
/* Turn on NXE if PAE has been enabled. */
? "HM: 32-bit and 64-bit guest supported.\n"
: "HM: 32-bit guest supported.\n"));
return VINF_SUCCESS;
}
/**
* Applies relocations to data and code managed by this
* component. This function will be called at init and
* whenever the VMM need to relocate it self inside the GC.
*
* @param pVM The VM.
*/
{
/* Fetch the current paging mode during the relocate callback during state loading. */
{
{
#ifdef VBOX_WITH_OLD_VTX_CODE
#endif
}
}
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
if (HMIsEnabled(pVM))
{
switch (PGMGetHostMode(pVM))
{
case PGMMODE_32_BIT:
break;
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
break;
default:
AssertFailed();
break;
}
}
#endif
return;
}
/**
* Notification callback which is called whenever there is a chance that a CR3
* value might have changed.
*
* This is called by PGM.
*
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param enmShadowMode New shadow paging mode.
* @param enmGuestMode New guest paging mode.
*/
VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
{
/* Ignore page mode changes during state loading. */
return;
#ifdef VBOX_WITH_OLD_VTX_CODE
&& HMIsEnabled(pVM))
{
&& enmGuestMode >= PGMMODE_PROTECTED)
{
/* After a real mode switch to protected mode we must force
CPL to 0. Our real mode emulation had to set it to 3. */
}
}
{
/* Keep track of paging mode changes. */
/* Did we miss a change, because all code was executed in the recompiler? */
{
Log(("HMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hm.s.vmx.enmPrevGuestMode),
PGMGetModeName(pVCpu->hm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hm.s.vmx.enmLastSeenGuestMode)));
}
}
#else
/* If the guest left protected mode VMX execution, we'll have to be extra
*/
if (enmGuestMode == PGMMODE_REAL)
{
Log(("HMR3PagingModeChanged indicates real mode execution\n"));
}
#endif
/** @todo r=ramshankar: Why do we need to do this? Most likely
* VBOX_WITH_OLD_VTX_CODE only. */
/* Reset the contents of the read cache. */
}
/**
* Terminates the HM.
*
* Termination means cleaning up and freeing all resources,
* the VM itself is, at this point, powered off or suspended.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
{
}
return 0;
}
/**
* Terminates the per-VCPU HM.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
{
#ifdef VBOX_WITH_STATISTICS
{
}
{
}
#endif
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
#endif
}
return 0;
}
/**
* Resets a virtual CPU.
*
* Used by HMR3Reset and CPU hot plugging.
*
* @param pVCpu The CPU to reset.
*/
{
/* On first entry we'll sync everything. */
#ifdef VBOX_WITH_OLD_VTX_CODE
/* Reset state information for real-mode emulation in VT-x. */
#else
#endif
/* Reset the contents of the read cache. */
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
/* Magic marker for searching in crash dumps. */
#endif
}
/**
* The VM is being reset.
*
* needs to be removed.
*
* @param pVM Pointer to the VM.
*/
{
LogFlow(("HMR3Reset:\n"));
if (HMIsEnabled(pVM))
{
}
/* Clear all patch information. */
}
/**
* Callback to patch a TPR instruction (vmmcall or mov cr8).
*
* @returns VBox strict status code.
* @param pVM Pointer to the VM.
* @param pVCpu The VMCPU for the EMT we're being called on.
* @param pvUser Unused.
*/
{
/* Only execute the handler on the VCPU the original patch request was issued. */
return VINF_SUCCESS;
Log(("hmR3RemovePatches\n"));
{
int rc;
#ifdef LOG_ENABLED
char szOutput[256];
rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
if (RT_SUCCESS(rc))
#endif
/* Check if the instruction is still the same. */
if (rc != VINF_SUCCESS)
{
continue; /* swapped out or otherwise removed; skip it. */
}
{
continue; /* skip it. */
}
#ifdef LOG_ENABLED
rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
if (RT_SUCCESS(rc))
#endif
}
return VINF_SUCCESS;
}
/**
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param idCpu VCPU to execute hmR3RemovePatches on.
* @param pPatchMem Patch memory range.
* @param cbPatchMem Size of the memory range.
*/
{
int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
return VINF_SUCCESS;
}
/**
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pPatchMem Patch memory range.
* @param cbPatchMem Size of the memory range.
*/
{
{
/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
return rc;
}
}
/**
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pPatchMem Patch memory range.
* @param cbPatchMem Size of the memory range.
*/
{
/* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
return VINF_SUCCESS;
}
/**
* Callback to patch a TPR instruction (vmmcall or mov cr8).
*
* @returns VBox strict status code.
* @param pVM Pointer to the VM.
* @param pVCpu The VMCPU for the EMT we're being called on.
* @param pvUser User specified CPU context.
*
*/
{
/*
* Only execute the handler on the VCPU the original patch request was
* issued. (The other CPU(s) might not yet have switched to protected
* mode, nor have the correct memory context.)
*/
return VINF_SUCCESS;
/*
* We're racing other VCPUs here, so don't try patch the instruction twice
* and make sure there is still room for our patch record.
*/
if (pPatch)
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
/*
* Disassembler the instruction and get cracking.
*/
if ( rc == VINF_SUCCESS
&& cbOp >= 3)
{
{
/* write. */
{
}
else
{
}
}
else
{
/*
* TPR Read.
*
* Found:
* mov eax, dword [fffe0080] (5 bytes)
* Check if next instruction is:
* shr eax, 4
*/
if ( rc == VINF_SUCCESS
{
/* Replacing two instructions now. */
/* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
abInstr[0] = 0xF0;
}
else
{
}
}
return VINF_SUCCESS;
}
/*
* Save invalid patch, so we will not try again.
*/
Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
return VINF_SUCCESS;
}
/**
* Callback to patch a TPR instruction (jump to generated code).
*
* @returns VBox strict status code.
* @param pVM Pointer to the VM.
* @param pVCpu The VMCPU for the EMT we're being called on.
* @param pvUser User specified CPU context.
*
*/
{
/*
* Only execute the handler on the VCPU the original patch request was
* issued. (The other CPU(s) might not yet have switched to protected
* mode, nor have the correct memory context.)
*/
return VINF_SUCCESS;
/*
* We're racing other VCPUs here, so don't try patch the instruction twice
* and make sure there is still room for our patch record.
*/
if (pPatch)
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
/*
* Disassemble the instruction and get cracking.
*/
if ( rc == VINF_SUCCESS
&& cbOp >= 5)
{
{
/*
* TPR write:
*
* push ECX [51]
* push EDX [52]
* push EAX [50]
* xor EDX,EDX [31 D2]
* mov EAX,EAX [89 C0]
* or
* mov EAX,0000000CCh [B8 CC 00 00 00]
* mov ECX,0C0000082h [B9 82 00 00 C0]
* wrmsr [0F 30]
* pop EAX [58]
* pop EDX [5A]
* pop ECX [59]
* jmp return_address [E9 return_address]
*
*/
bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
if (!fUsesEax)
{
if (!fUsesEax)
{
}
}
else
{
}
if (!fUsesEax)
}
else
{
/*
* TPR read:
*
* push ECX [51]
* push EDX [52]
* push EAX [50]
* mov ECX,0C0000082h [B9 82 00 00 C0]
* rdmsr [0F 32]
* mov EAX,EAX [89 C0]
* pop EAX [58]
* pop EDX [5A]
* pop ECX [59]
* jmp return_address [E9 return_address]
*
*/
{
}
}
*(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
off += sizeof(RTRCUINTPTR);
{
/* Write new code to the patch buffer. */
#ifdef LOG_ENABLED
{
char szOutput[256];
rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
if (RT_SUCCESS(rc))
else
}
#endif
*(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
/* Overwrite the TPR instruction with a jump. */
return VINF_SUCCESS;
}
Log(("Ran out of space in our patch buffer!\n"));
}
else
Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
/*
* Save invalid patch, so we will not try again.
*/
return VINF_SUCCESS;
}
/**
* Attempt to patch TPR mmio instructions.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest CPU context.
*/
{
return rc;
}
/**
* Checks if a code selector (CS) is suitable for execution
* within VMX when unrestricted execution isn't available.
*
* @returns true if selector is suitable for VMX, otherwise
* false.
* @param pSel Pointer to the selector to check (CS).
* uStackDpl The DPL of the stack segment.
*/
{
bool rc = false;
do
{
/* Segment must be accessed. */
break;
/* Segment must be a code segment. */
break;
/* The S bit must be set. */
break;
{
/* For conforming segments, CS.DPL must be <= SS.DPL. */
break;
}
else
{
/* For non-conforming segments, CS.DPL must equal SS.DPL. */
break;
}
/* Segment must be present. */
break;
/* G bit must be set if any high limit bits are set. */
break;
/* G bit must be clear if any low limit bits are clear. */
break;
rc = true;
} while (0);
return rc;
}
/**
* execution within VMX when unrestricted execution isn't
* available.
*
* @returns true if selector is suitable for VMX, otherwise
* false.
* @param pSel Pointer to the selector to check
*/
{
bool rc = false;
/* If attributes are all zero, consider the segment unusable and therefore OK.
* This logic must be in sync with HMVMXR0.cpp!
*/
return true;
do
{
/* Segment must be accessed. */
break;
/* Code segments must also be readable. */
break;
/* The S bit must be set. */
break;
/* Except for conforming segments, DPL >= RPL. */
break;
/* Segment must be present. */
break;
/* G bit must be set if any high limit bits are set. */
break;
/* G bit must be clear if any low limit bits are clear. */
break;
rc = true;
} while (0);
return rc;
}
/**
* Checks if the stack selector (SS) is suitable for execution
* within VMX when unrestricted execution isn't available.
*
* @returns true if selector is suitable for VMX, otherwise
* false.
* @param pSel Pointer to the selector to check (SS).
*/
{
bool rc = false;
/* If attributes are all zero, consider the segment unusable and therefore OK.
* This logic must be in sync with HMVMXR0.cpp!
*/
return true;
do
{
/* Segment must be accessed. */
break;
/* Segment must be writable. */
break;
/* Segment must not be a code segment. */
break;
/* The S bit must be set. */
break;
/* DPL must equal RPL. */
break;
/* Segment must be present. */
break;
/* G bit must be set if any high limit bits are set. */
break;
/* G bit must be clear if any low limit bits are clear. */
break;
rc = true;
} while (0);
return rc;
}
/**
* Force execution of the current IO code in the recompiler.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pCtx Partial VM execution context.
*/
{
Log(("HMR3EmulateIoBlock\n"));
/* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
if (HMCanEmulateIoBlockEx(pCtx))
{
Log(("HMR3EmulateIoBlock -> enabled\n"));
return VINF_EM_RESCHEDULE_REM;
}
return VINF_SUCCESS;
}
/**
* Checks if we can currently use hardware accelerated raw mode.
*
* @returns true if we can currently use hardware acceleration, otherwise false.
* @param pVM Pointer to the VM.
* @param pCtx Partial VM execution context.
*/
{
/* If we're still executing the IO code, then return false. */
return false;
/* AMD-V supports real & protected mode with or without paging. */
{
return true;
}
/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
{
/*
* The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
* guest execution feature i missing (VT-x only).
*/
if (fSupportsRealMode)
{
if (CPUMIsGuestInRealModeEx(pCtx))
{
/* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
* bases and limits, i.e. limit must be 64K and base must be selector * 16.
* If this is not true, we cannot execute real mode as V86 and have to fall
* back to emulation.
*/
{
return false;
}
}
else
{
/* Verify the requirements for executing code in protected
mode. VT-x can't handle the CPU state right after a switch
from real to protected mode. (all sorts of RPL & DPL assumptions) */
&& enmGuestMode >= PGMMODE_PROTECTED)
#else
#endif
{
//@todo: If guest is in V86 mode, these checks should be different!
#else
#endif
{
return false;
}
}
/* VT-x also chokes on invalid tr or ldtr selectors (minix) */
{
return false;
}
}
}
else
{
if ( !CPUMIsGuestInLongModeEx(pCtx)
{
/** @todo This should (probably) be set on every excursion to the REM,
* however it's too risky right now. So, only apply it when we go
* back to REM for real mode execution. (The XP hack below doesn't
* work reliably without this.)
* Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HM. */
if ( !pVM->hm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
|| CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
return false;
/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
return false;
/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
/* Windows XP; switch to protected mode; all selectors are marked not present in the
* hidden registers (possible recompiler bug; see load_seg_vm) */
return false;
return false;
/* Windows XP: possible same as above, but new recompiler requires new heuristics?
VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
/** @todo This check is actually wrong, it doesn't take the direction of the
* stack segment into account. But, it does the job for now. */
return false;
#if 0
return false;
#endif
}
}
}
{
/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
/* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
mask &= ~X86_CR0_NE;
if (fSupportsRealMode)
{
/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
}
else
{
/* We support protected mode without paging using identity mapping. */
mask &= ~X86_CR0_PG;
}
return false;
/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
return false;
/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
mask &= ~X86_CR4_VMXE;
return false;
/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
return false;
return true;
}
return false;
}
/**
* Checks if we need to reschedule due to VMM device heap changes.
*
* @returns true if a reschedule is required, otherwise false.
* @param pVM Pointer to the VM.
* @param pCtx VM execution context.
*/
{
/*
* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
* when the unrestricted guest execution feature is missing (VT-x only).
*/
#ifdef VBOX_WITH_OLD_VTX_CODE
return true;
#else
&& !PDMVmmDevHeapIsEnabled(pVM))
return true;
#endif
return false;
}
/**
* Notification from EM about a rescheduling into hardware assisted execution
* mode.
*
* @param pVCpu Pointer to the current VMCPU.
*/
{
}
/**
* Notification from EM about returning from instruction emulation (REM / EM).
*
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* Checks if we are currently using hardware accelerated raw mode.
*
* @returns true if hardware acceleration is being used, otherwise false.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* External interface for querying whether hardware accelerated raw mode is
* enabled.
*
* @returns true if nested paging is being used, otherwise false.
* @param pUVM The user mode VM handle.
* @sa HMIsEnabled, HMIsEnabledNotMacro.
*/
{
UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
VM_ASSERT_VALID_EXT_RETURN(pVM, false);
}
/**
* Checks if we are currently using nested paging.
*
* @returns true if nested paging is being used, otherwise false.
* @param pUVM The user mode VM handle.
*/
{
UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
VM_ASSERT_VALID_EXT_RETURN(pVM, false);
}
/**
* Checks if we are currently using VPID in VT-x mode.
*
* @returns true if VPID is being used, otherwise false.
* @param pUVM The user mode VM handle.
*/
{
UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
VM_ASSERT_VALID_EXT_RETURN(pVM, false);
}
/**
* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
*
* @returns true if an internal event is pending, otherwise false.
* @param pVM Pointer to the VM.
*/
{
}
/**
* Checks if the VMX-preemption timer is being used.
*
* @returns true if the VMX-preemption timer is being used, otherwise false.
* @param pVM Pointer to the VM.
*/
{
return HMIsEnabled(pVM)
}
/**
* Restart an I/O instruction that was refused in ring-0
*
* @returns Strict VBox status code. Informational status codes other than the one documented
* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
* @retval VINF_SUCCESS Success.
* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
* status code must be passed on to EM.
* @retval VERR_NOT_FOUND if no pending I/O instruction.
*
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest CPU context.
*/
{
|| enmType == HMPENDINGIO_INVALID)
return VERR_NOT_FOUND;
switch (enmType)
{
case HMPENDINGIO_PORT_READ:
{
&u32Val,
if (IOM_SUCCESS(rcStrict))
{
/* Write back to the EAX register. */
}
break;
}
case HMPENDINGIO_PORT_WRITE:
if (IOM_SUCCESS(rcStrict))
break;
default:
}
return rcStrict;
}
/**
* log release message.
*
* @param pVM Pointer to the VM.
* @param iStatusCode VBox status code.
*/
{
{
switch (iStatusCode)
{
break;
LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
LogRel(("HM: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
LogRel(("HM: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32VMCSRevision));
break;
LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
{
#endif
}
/** @todo Log VM-entry event injection control fields
* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
break;
break;
}
}
{
LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
}
}
/**
* Execute state save operation.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pSSM SSM operation handle.
*/
{
int rc;
Log(("hmR3Save:\n"));
{
/*
* Save the basic bits - fortunately all the other things can be resynced on load.
*/
#else
//@todo: We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
// perhaps not even that (the initial value of 'true' is safe).
#endif
}
#ifdef VBOX_HM_WITH_GUEST_PATCHING
/* Store all the guest patch records too. */
{
}
#endif
return VINF_SUCCESS;
}
/**
* Execute state load operation.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pSSM SSM operation handle.
* @param uVersion Data layout version.
* @param uPass The data pass.
*/
{
int rc;
Log(("hmR3Load:\n"));
/*
* Validate version.
*/
if ( uVersion != HM_SSM_VERSION
&& uVersion != HM_SSM_VERSION_2_0_X)
{
}
{
if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
{
#ifdef VBOX_WITH_OLD_VTX_CODE
#else
//@todo: See note above re saving enmLastSeenGuestMode
#endif
}
}
#ifdef VBOX_HM_WITH_GUEST_PATCHING
{
/* Fetch all TPR patch records. */
{
Log(("hmR3Load: patch %d\n", i));
}
}
#endif
/* Recheck all VCPUs if we can go straight into hm execution mode. */
if (HMIsEnabled(pVM))
{
{
}
}
return VINF_SUCCESS;
}