HM.cpp revision 2e45fa7cb386512a0c01f8504b116f9f8577a910
b450d7a1747c5f4fb7c917a8ec1f9ce8440d7ffevboxsync * HM - Intel/AMD VM Hardware Support Manager.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Copyright (C) 2006-2014 Oracle Corporation
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * available from http://www.virtualbox.org. This file is free software;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * you can redistribute it and/or modify it under the terms of the GNU
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * General Public License (GPL) as published by the Free Software
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync/*******************************************************************************
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync* Header Files *
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync*******************************************************************************/
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync/*******************************************************************************
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync* Global Variables *
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync*******************************************************************************/
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync# define EXIT_REASON(def, val, str) #def " - " #val " - " str
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync/** Exit reason descriptions for VT-x, used to describe statistics. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
6a795f9e75e30c7f1d75cd45e5de233c71662f58vboxsync EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
6a795f9e75e30c7f1d75cd45e5de233c71662f58vboxsync EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
6a795f9e75e30c7f1d75cd45e5de233c71662f58vboxsync EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
6a795f9e75e30c7f1d75cd45e5de233c71662f58vboxsync EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold (MOV to CR8)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR using LGDT, LIDT, SGDT, or SIDT."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR using LLDT, LTR, SLDT, or STR."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction.")
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync/** Exit reason descriptions for AMD-V, used to describe statistics. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt-window exit."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "Legacy FPU handling enabled; processor is frozen in an x87/mmx instruction waiting for an interrupt"),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_MWAIT ,139, "MWAIT instruction."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging fault."),
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync#endif /* VBOX_WITH_STATISTICS */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: " #featflag " (must be cleared)\n")); \
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync } while (0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, featflag) \
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync } while (0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync } while (0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync/*******************************************************************************
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync* Internal Functions *
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync*******************************************************************************/
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Initializes the HM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * This reads the config and check whether VT-x or AMD-V hardware is available
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * if configured to use it. This is one of the very first components to be
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * initialized after CFGM, so that we can fall back to raw-mode early in the
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * initialization process.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Note that a lot of the set up work is done in ring-0 and thus postponed till
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync * the ring-3 and ring-0 callback to HMR3InitCompleted.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @remarks Be careful with what we call here, since most of the VMM components
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * are uninitialized.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Assert alignment and sizes.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Register the saved state data unit.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Misc initialisation.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Read configuration.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync PCFGMNODE pCfgHM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @cfgm{/HM/HMForced, bool, false}
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Forces hardware virtualization, no falling back on raw-mode. HM must be
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * enabled, i.e. /HMEnabled must be true. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = CFGMR3QueryBoolDef(pCfgHM, "HMForced", &fHMForced, false);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#else /* !VBOX_WITH_RAW_MODE */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#endif /* !VBOX_WITH_RAW_MODE */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @cfgm{/HM/EnableNestedPaging, bool, false}
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Enables nested paging (aka extended page tables). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = CFGMR3QueryBoolDef(pCfgHM, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @cfgm{/HM/EnableUX, bool, true}
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Enables the VT-x unrestricted execution feature. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = CFGMR3QueryBoolDef(pCfgHM, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @cfgm{/HM/EnableLargePages, bool, false}
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * page table walking and maybe better TLB hit rate in some cases. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = CFGMR3QueryBoolDef(pCfgHM, "EnableLargePages", &pVM->hm.s.fLargePages, false);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @cfgm{/HM/EnableVPID, bool, false}
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Enables the VT-x VPID feature. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = CFGMR3QueryBoolDef(pCfgHM, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Enables TPR patching for 32-bit windows guests with IO-APIC. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = CFGMR3QueryBoolDef(pCfgHM, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Enables AMD64 cpu features.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * already have the support. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = CFGMR3QueryBoolDef(pCfgHM, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @cfgm{/HM/Exclusive, bool}
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * global init for each host CPU. If false, we do local init each time we wish
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * to execute guest code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Default is false for Mac OS X and Windows due to the higher risk of conflicts
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * with other hypervisors.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = CFGMR3QueryBoolDef(pCfgHM, "Exclusive", &pVM->hm.s.fGlobalInit,
415d16c5ec8565fd576a042d180e8494471ed548vboxsync /** @cfgm{/HM/MaxResumeLoops, uint32_t}
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync * The number of times to resume guest execution before we forcibly return to
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * determines the default value. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = CFGMR3QueryU32Def(pCfgHM, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Check if VT-x or AMD-v support according to the users wishes.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * VERR_SVM_IN_USE. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HMR3Init: VT-x%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync const char *pszMinReq = " Linux 2.6.13 or newer required!";
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync /* Fall back to raw-mode. */
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync LogRel(("HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Do we require a little bit or raw-mode for 64-bit guest execution?
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync const char *pszMsg;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained.";
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pszMsg = "VT-x is disabled in the BIOS for all CPU modes.";
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pszMsg = "Failed to enable and lock VT-x features.";
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pszMsg = "AMD-V is disabled in the BIOS (or by the host OS).";
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Fall back to raw-mode. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* It's now OK to use the predicate function. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Initializes the per-VCPU HM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Statistics.
8b82f5ce032cb07de31804c998483b0988530aebvboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
8b82f5ce032cb07de31804c998483b0988530aebvboxsync "Profiling of RTMpPokeCpu",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync "Profiling of poke wait",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync "Profiling of poke wait when RTMpPokeCpu fails",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync "Profiling of VMXR0RunGuestCode entry",
9083f76e8c5709604766d0215a380de516e781eevboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
ad8fb8c920c36650d5ead020ef8e05b681dd4375vboxsync "Profiling of VMXR0RunGuestCode exit part 1",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync "Profiling of VMXR0RunGuestCode exit part 2",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync "Exceptions, NMIs",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync "Profiling of VMXR0LoadGuestState",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync "Profiling of VMLAUNCH/VMRESUME.",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume", "Maximum VMRESUME inner-loop counter reached.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccessToR3, "/HM/CPU%d/Exit/ApicAccessToR3", "APIC access causing us to go to ring-3.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception back to the guest.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatPreemptPreempting, "/HM/CPU%d/Preempt/Preempting", "EMT has been preempted while in HM context.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatPreemptSaveHostState, "/HM/CPU%d/Preempt/SaveHostState", "Preemption caused us to resave host state.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffsetAdjusted, "/HM/CPU%d/TSC/OffsetAdjusted", "TSC offset overflowed for paravirt. TSC. Fudged.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Guest is in catchup mode, intercept TSC accesses.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow", "TSC offset overflow, fallback to intercept TSC accesses.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync for (int j = 0; j < MAX_EXITREASON_STAT; j++)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync for (unsigned j = 0; j < 255; j++)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync "Injected event.",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#endif /* VBOX_WITH_STATISTICS */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Magic marker for searching in crash dumps.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Called when a init phase has completed.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM The VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param enmWhat The phase that completed.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Turns off normal raw mode features.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Reinit the paging mode to force the new shadow mode. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Initialize VT-x or AMD-V.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Hack to allow users to work around broken BIOSes that incorrectly set
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * EFER.SVME, which makes us believe somebody else is already using AMD-V.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Report ring-0 init errors.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is disabled in the BIOS.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is disabled in the BIOS for all CPU modes.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "Failed to enable and lock VT-x features.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Enable VT-x or AMD-V on all host CPUs.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * No TPR patching is required when the IO-APIC is not enabled for this VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * (Main should have taken care of this already)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Do the vendor specific initalization .
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Note! We disable release log buffering here since we're doing relatively .
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * lot of logging and doesn't want to hit the disk with each LogRel .
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * statement.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Finish VT-x initialization (after ring-0 init).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM The cross context VM structure.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BOOL(MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo))));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BOOL(MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo))));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Paranoia */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: MSR_A32_VMX_VMFUNC = %#RX64\n", val));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMVMX_REPORT_ALLOWED_FEATURE(val, VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Unrestricted guest execution also requires EPT. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync esp. Figure 20-5.*/
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Bit set to 0 means software interrupts are redirected to the
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync 8086 program interrupt handler rather than switching to
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync protected-mode handler. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Allow all port IO, so that port IO instructions do not cause
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync exceptions and would instead cause a VM-exit (based on VT-x's
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync IO bitmap which we currently configure to always cause an exit). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Construct a 1024 element page directory with 4 MB pages for
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * the identity mapped page table used in real and protected mode
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * without paging with EPT.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* We convert it here every time as pci regions could be reconfigured. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ? "HM: Guest support: 32-bit and 64-bit\n"
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync : "HM: Guest support: 32-bit only\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Call ring-0 to set up the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR3DisableRawMode(pVM); /** @todo make this go away! */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Change the CPU features.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync (we reuse the host EFER in the switcher). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo this needs to be fixed properly!! */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync * Log configuration details.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_SINGLE_CONTEXT)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: EPT flush type = VMXFLUSHEPT_SINGLE_CONTEXT\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_ALL_CONTEXTS)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: EPT flush type = VMXFLUSHEPT_ALL_CONTEXTS\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_NOT_SUPPORTED)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: EPT flush type = VMXFLUSHEPT_NOT_SUPPORTED\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: Unrestricted guest execution enabled!\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Use large (2 MB) pages for our EPT PDEs where possible. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_INDIV_ADDR)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VPID flush type = VMXFLUSHVPID_INDIV_ADDR\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VPID flush type = VMXFLUSHVPID_ALL_CONTEXTS\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_NOT_SUPPORTED)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Check for preemption timer config override and log the state of it.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: VMX-preemption timer enabled (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Finish AMD-V initialization (after ring-0 init).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM The cross context VM structure.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Enumerate AMD-V features.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#define HMSVM_REPORT_FEATURE(a_Define) { a_Define, #a_Define }
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_AVIC),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Adjust feature(s).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Call ring-0 to set up the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Enable large pages (2 MB) if applicable.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Change the CPU features.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Turn on NXE if PAE has been enabled. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: TPR patching %s\n", (pVM->hm.s.fTprPatchingAllowed) ? "enabled" : "disabled"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ? "HM: Guest support: 32-bit and 64-bit\n"
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync : "HM: Guest support: 32-bit only\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Applies relocations to data and code managed by this
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * component. This function will be called at init and
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * whenever the VMM need to relocate it self inside the GC.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM The VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Fetch the current paging mode during the relocate callback during state loading. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Notification callback which is called whenever there is a chance that a CR3
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * value might have changed.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * This is called by PGM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param enmShadowMode New shadow paging mode.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param enmGuestMode New guest paging mode.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Ignore page mode changes during state loading. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * If the guest left protected mode VMX execution, we'll have to be
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * extra careful if/when the guest switches back to protected mode.
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync Log(("HMR3PagingModeChanged indicates real mode execution\n"));
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync /** @todo r=ramshankar: Disabling for now. If nothing breaks remove it
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync * eventually. (Test platforms that use the cache ofc). */
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync /* Reset the contents of the read cache. */
2d8894b1c178c9f1199cac84059ca66aa5dee6b3vboxsync for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync * Terminates the HM.
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync * Termination means cleaning up and freeing all resources,
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync * the VM itself is, at this point, powered off or suspended.
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync * @returns VBox status code.
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Terminates the per-VCPU HM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Resets a virtual CPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Used by HMR3Reset and CPU hot plugging.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu The CPU to reset.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Sync. entire state on VM reset R0-reentry. It's safe to reset
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMCPU_CF_RESET_TO(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Reset the contents of the read cache. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Magic marker for searching in crash dumps. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * The VM is being reset.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * For the HM component this means that any GDT/LDT/TSS monitors
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * needs to be removed.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Clear all patch information. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Callback to patch a TPR instruction (vmmcall or mov cr8).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox strict status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu The VMCPU for the EMT we're being called on.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pvUser Unused.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncDECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Only execute the handler on the VCPU the original patch request was issued. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Check if the instruction is still the same. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync continue; /* swapped out or otherwise removed; skip it. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync continue; /* skip it. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Worker for enabling patching in a VT-x/AMD-V guest.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param idCpu VCPU to execute hmR3RemovePatches on.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pPatchMem Patch memory range.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param cbPatchMem Size of the memory range.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Enable patching in a VT-x/AMD-V guest
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pPatchMem Patch memory range.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param cbPatchMem Size of the memory range.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Disable patching in a VT-x/AMD-V guest.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pPatchMem Patch memory range.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param cbPatchMem Size of the memory range.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Callback to patch a TPR instruction (vmmcall or mov cr8).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox strict status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu The VMCPU for the EMT we're being called on.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pvUser User specified CPU context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncDECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Only execute the handler on the VCPU the original patch request was
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * issued. (The other CPU(s) might not yet have switched to protected
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * mode, nor have the correct memory context.)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * We're racing other VCPUs here, so don't try patch the instruction twice
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * and make sure there is still room for our patch record.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Disassembler the instruction and get cracking.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* write. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * TPR Read.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * mov eax, dword [fffe0080] (5 bytes)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Check if next instruction is:
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * shr eax, 4
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync access CR8 in 32-bit mode and not cause a #VMEXIT. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Save invalid patch, so we will not try again.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Callback to patch a TPR instruction (jump to generated code).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox strict status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu The VMCPU for the EMT we're being called on.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pvUser User specified CPU context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncDECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Only execute the handler on the VCPU the original patch request was
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * issued. (The other CPU(s) might not yet have switched to protected
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * mode, nor have the correct memory context.)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * We're racing other VCPUs here, so don't try patch the instruction twice
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * and make sure there is still room for our patch record.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Disassemble the instruction and get cracking.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * TPR write:
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * push ECX [51]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * push EDX [52]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * push EAX [50]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * xor EDX,EDX [31 D2]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * mov EAX,EAX [89 C0]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * mov EAX,0000000CCh [B8 CC 00 00 00]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * mov ECX,0C0000082h [B9 82 00 00 C0]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * wrmsr [0F 30]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * pop EAX [58]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * pop EDX [5A]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * pop ECX [59]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * jmp return_address [E9 return_address]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * TPR read:
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * push ECX [51]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * push EDX [52]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * push EAX [50]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * mov ECX,0C0000082h [B9 82 00 00 C0]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * rdmsr [0F 32]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * mov EAX,EAX [89 C0]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * pop EAX [58]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * pop EDX [5A]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * pop ECX [59]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * jmp return_address [E9 return_address]
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Write new code to the patch buffer. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Overwrite the TPR instruction with a jump. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Save invalid patch, so we will not try again.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Attempt to patch TPR mmio instructions.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Pointer to the guest CPU context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Checks if a code selector (CS) is suitable for execution
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * within VMX when unrestricted execution isn't available.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns true if selector is suitable for VMX, otherwise
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pSel Pointer to the selector to check (CS).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * uStackDpl The CPL, aka the DPL of the stack segment.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Segment must be an accessed code segment, it must be present and it must
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * be usable.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Note! These are all standard requirements and if CS holds anything else
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * we've got buggy code somewhere!
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P | X86DESCATTR_UNUSABLE))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync must equal SS.DPL for non-confroming segments.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Note! This is also a hard requirement like above. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * The following two requirements are VT-x specific:
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * - G bit must be set if any high limit bits are set.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * - G bit must be clear if any low limit bits are clear.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return true;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Checks if a data selector (DS/ES/FS/GS) is suitable for
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * execution within VMX when unrestricted execution isn't
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * available.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns true if selector is suitable for VMX, otherwise
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pSel Pointer to the selector to check
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Unusable segments are OK. These days they should be marked as such, as
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * but as an alternative we for old saved states and AMD<->VT-x migration
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * we also treat segments with all the attributes cleared as unusable.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return true;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo tighten these checks. Will require CPUM load adjusting. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Segment must be accessed. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Code segments must also be readable. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* The S bit must be set. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Except for conforming segments, DPL >= RPL. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Segment must be present. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * The following two requirements are VT-x specific:
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * - G bit must be set if any high limit bits are set.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * - G bit must be clear if any low limit bits are clear.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return true;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Checks if the stack selector (SS) is suitable for execution
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * within VMX when unrestricted execution isn't available.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns true if selector is suitable for VMX, otherwise
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pSel Pointer to the selector to check (SS).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Unusable segments are OK. These days they should be marked as such, as
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * but as an alternative we for old saved states and AMD<->VT-x migration
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * we also treat segments with all the attributes cleared as unusable.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo r=bird: actually all zeros isn't gonna cut it... SS.DPL == CPL. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return true;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Segment must be an accessed writable segment, it must be present.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Note! These are all standard requirements and if SS holds anything else
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * we've got buggy code somewhere!
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* DPL must equal RPL.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Note! This is also a hard requirement like above. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * The following two requirements are VT-x specific:
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * - G bit must be set if any high limit bits are set.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * - G bit must be clear if any low limit bits are clear.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return true;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Force execution of the current IO code in the recompiler.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Partial VM execution context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Checks if we can currently use hardware accelerated raw mode.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns true if we can currently use hardware acceleration, otherwise false.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Partial VM execution context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* If we're still executing the IO code, then return false. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* AMD-V supports real & protected mode with or without paging. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return true;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * guest execution feature is missing (VT-x only).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * bases and limits, i.e. limit must be 64K and base must be selector * 16.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * If this is not true, we cannot execute real mode as V86 and have to fall
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * back to emulation.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Verify the requirements for executing code in protected
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync mode. VT-x can't handle the CPU state right after a switch
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync from real to protected mode. (all sorts of RPL & DPL assumptions). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo If guest is in V86 mode, these checks should be different! */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ((pCtx->tr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if ((pCtx->ldtr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Windows XP; switch to protected mode; all selectors are marked not present in the
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * hidden registers (possible recompiler bug; see load_seg_vm) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Windows XP: possible same as above, but new recompiler requires new heuristics?
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo This check is actually wrong, it doesn't take the direction of the
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * stack segment into account. But, it does the job for now. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* We support protected mode without paging using identity mapping. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return true;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Checks if we need to reschedule due to VMM device heap changes.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns true if a reschedule is required, otherwise false.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx VM execution context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * when the unrestricted guest execution feature is missing (VT-x only).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return true;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Notification from EM about a rescheduling into hardware assisted execution
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the current VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Notification from EM about returning from instruction emulation (REM / EM).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Checks if we are currently using hardware acceleration.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns true if hardware acceleration is being used, otherwise false.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * External interface for querying whether hardware acceleration is enabled.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns true if VT-x or AMD-V is being used, otherwise false.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pUVM The user mode VM handle.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @sa HMIsEnabled, HMIsEnabledNotMacro.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * External interface for querying whether VT-x is being used.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns true if VT-x is being used, otherwise false.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pUVM The user mode VM handle.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @sa HMR3IsSvmEnabled, HMIsEnabled
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * External interface for querying whether AMD-V is being used.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns true if VT-x is being used, otherwise false.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pUVM The user mode VM handle.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @sa HMR3IsVmxEnabled, HMIsEnabled
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Checks if we are currently using nested paging.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns true if nested paging is being used, otherwise false.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pUVM The user mode VM handle.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Checks if we are currently using VPID in VT-x mode.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns true if VPID is being used, otherwise false.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pUVM The user mode VM handle.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Checks if we are currently using VT-x unrestricted execution,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns true if UX is being used, otherwise false.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pUVM The user mode VM handle.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns true if an internal event is pending, otherwise false.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Checks if the VMX-preemption timer is being used.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns true if the VMX-preemption timer is being used, otherwise false.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Restart an I/O instruction that was refused in ring-0
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns Strict VBox status code. Informational status codes other than the one documented
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @retval VINF_SUCCESS Success.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * status code must be passed on to EM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @retval VERR_NOT_FOUND if no pending I/O instruction.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Pointer to the guest CPU context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Write back to the EAX register. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Check for I/O breakpoints.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Check fatal VT-x/AMD-V error and produce some meaningful
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * log release message.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param iStatusCode VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * might be getting inaccurate values for non-guru'ing EMTs. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo Log VM-entry event injection control fields
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] idxExitHistoryFree %u\n", i, pVCpu->hm.s.idxExitHistoryFree));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync unsigned const idxLast = pVCpu->hm.s.idxExitHistoryFree > 0 ?
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync for (unsigned k = 0; k < RT_ELEMENTS(pVCpu->hm.s.auExitHistory); k++)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("HM: CPU[%u] auExitHistory[%2u] = %#x (%u) %s\n", i, k, pVCpu->hm.s.auExitHistory[k],
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.auExitHistory[k], idxLast == k ? "<-- Last" : ""));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Execute state save operation.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pSSM SSM operation handle.
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsyncstatic DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Save the basic bits - fortunately all the other things can be resynced on load.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntInfo);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo Shouldn't we be saving GCPtrFaultAddress too? */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * perhaps not even that (the initial value of @c true is safe. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Store all the guest patch records too. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Execute state load operation.
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync * @returns VBox status code.
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pSSM SSM operation handle.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param uVersion Data layout version.
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync * @param uPass The data pass.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Validate version.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (uVersion >= HM_SAVED_STATE_VERSION_NO_PATCHING)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo See note in hmR3Save(). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Fetch all TPR patch records. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);