EMHwaccm.cpp revision 1f1218115ed7be1a29be1143ef6d8736532af2cc
8e2911e5309f5dff976cc7ac17d832d4ee2cdca3vboxsync * EM - Execution Monitor / Manager - hardware virtualization
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * Copyright (C) 2006-2012 Oracle Corporation
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * available from http://www.virtualbox.org. This file is free software;
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * you can redistribute it and/or modify it under the terms of the GNU
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * General Public License (GPL) as published by the Free Software
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync/*******************************************************************************
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync* Header Files *
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync*******************************************************************************/
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync/*******************************************************************************
dc1ef3adbbc24e348697c7f7d4b4df5cf4f64c32vboxsync* Defined Constants And Macros *
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync*******************************************************************************/
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
cba6719bd64ec749967bbe931230452664109857vboxsync/*******************************************************************************
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync* Internal Functions *
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync*******************************************************************************/
dc1ef3adbbc24e348697c7f7d4b4df5cf4f64c32vboxsyncDECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsyncstatic int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsyncstatic int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync#if defined(DEBUG) && defined(SOME_UNUSED_FUNCTIONS)
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * Steps hardware accelerated mode.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * @returns VBox status code.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * @param pVM The VM handle.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * @param pVCpu The VMCPU handle.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS));
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * Check vital forced actions, but ignore pending interrupts and timers.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * Set flags for single stepping.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * Single step.
dc1ef3adbbc24e348697c7f7d4b4df5cf4f64c32vboxsync * We do not start time or anything, if anything we should just do a few nanoseconds.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * Make sure the trap flag is cleared.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * (Too bad if the guest is trying to single step too.)
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * Deal with the return codes.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsyncstatic int emR3SingleStepExecHwAcc(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync || !HWACCMR3CanExecuteGuest(pVM, pVCpu->em.s.pCtx))
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync return rc == VINF_SUCCESS ? VINF_EM_RESCHEDULE_REM : rc;
cba6719bd64ec749967bbe931230452664109857vboxsync#endif /* DEBUG */
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * Executes one (or perhaps a few more) instruction(s).
cba6719bd64ec749967bbe931230452664109857vboxsync * @returns VBox status code suitable for EM.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * @param pVM VM handle.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * @param pVCpu VMCPU handle
cba6719bd64ec749967bbe931230452664109857vboxsync * @param rcRC Return code from RC.
cba6719bd64ec749967bbe931230452664109857vboxsync * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * instruction and prefix the log output with this text.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsyncstatic int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC, const char *pszPrefix)
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsyncstatic int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC)
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * The simple solution is to use the recompiler.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * The better solution is to disassemble the current instruction and
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * try handle as many as possible without using REM.
cba6719bd64ec749967bbe931230452664109857vboxsync * Disassemble the instruction if requested.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync#endif /* LOG_ENABLED */
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync /* Try our own instruction emulator before falling back to the recompiler. */
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
cba6719bd64ec749967bbe931230452664109857vboxsync /* @todo we can do more now */
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
ad77e3ec3cde24263bc7537575f5cae442bee3b1vboxsync if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
dc1ef3adbbc24e348697c7f7d4b4df5cf4f64c32vboxsync#endif /* 0 */
dc1ef3adbbc24e348697c7f7d4b4df5cf4f64c32vboxsync Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
ad77e3ec3cde24263bc7537575f5cae442bee3b1vboxsync /* Flush the recompiler TLB if the VCPU has changed. */
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); NOREF(pVM);
cba6719bd64ec749967bbe931230452664109857vboxsync if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
cba6719bd64ec749967bbe931230452664109857vboxsync * Executes one (or perhaps a few more) instruction(s).
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync * This is just a wrapper for discarding pszPrefix in non-logging builds.
#ifdef LOG_ENABLED
/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
case OP_IN:
case OP_OUT:
case OP_INSB:
case OP_INSWD:
case OP_OUTSB:
case OP_OUTSWD:
return VINF_SUCCESS;
AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR || rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
return rc;
return rc;
rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
return rc;
return rc;
return VINF_EM_NO_MEMORY;
return VINF_SUCCESS;
* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
*pfFFDone = false;
#ifdef EM_NOTIFY_HWACCM
VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
#ifdef LOG_ENABLED
Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs, (RTGCPTR)pCtx->rip));
Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
#ifdef VBOX_HIGH_RES_TIMERS_HACK
*pfFFDone = true;
return rc;