CPUMR3Db.cpp revision 9f22c692723a5d3cb78b91896c48cf681c4fb608
5b281ba489ca18f0380d7efc7a5108b606cce449vboxsync * CPUM - CPU database part.
c58f1213e628a545081c70e26c6b67a841cff880vboxsync * Copyright (C) 2013 Oracle Corporation
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync * available from http://www.virtualbox.org. This file is free software;
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync * you can redistribute it and/or modify it under the terms of the GNU
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync * General Public License (GPL) as published by the Free Software
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync/*******************************************************************************
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync* Header Files *
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync*******************************************************************************/
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync/*******************************************************************************
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync* Structures and Typedefs *
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync*******************************************************************************/
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsynctypedef struct CPUMDBENTRY
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync /** The CPU name. */
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync const char *pszName;
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync /** The full CPU name. */
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync /** The CPU vendor (CPUMCPUVENDOR). */
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync /** The CPU family. */
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync /** The CPU model. */
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync /** The CPU stepping. */
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync /** The microarchitecture. */
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync /** Flags (TBD). */
f212e1f2b6bb160f9b7539562599a4604ca44cd2vboxsync /** The maximum physical address with of the CPU. This should correspond to
} CPUMDBENTRY;
#ifndef CPUM_DB_STANDALONE
RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
#ifdef VBOX_WITH_STATISTICS
# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
#include "cpus/Intel_Core_i7_3960X.h"
#include "cpus/Intel_Core_i5_3570.h"
#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
#include "cpus/AMD_FX_8150_Eight_Core.h"
#include "cpus/Quad_Core_AMD_Opteron_2384.h"
#ifndef CPUM_DB_STANDALONE
static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
if (!cMsrRanges)
if (i <= iStart)
if (i >= iLast)
if (i < cMsrRanges)
static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
if (!pvNew)
return NULL;
return *ppaMsrRanges;
int cpumR3MsrRangesInsert(PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange)
if ( cMsrRanges > 0
if (!paMsrRanges)
return VERR_NO_MEMORY;
if ( i >= cMsrRanges
if (!paMsrRanges)
return VERR_NO_MEMORY;
if (i < cMsrRanges)
if (!paMsrRanges)
return VERR_NO_MEMORY;
if (i < cMsrRanges)
while ( i < cMsrRanges
if (!paMsrRanges)
return VERR_NO_MEMORY;
if (i < cMsrRanges)
return VINF_SUCCESS;
int rc;
return rc;
return rc;
CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
if (!pEntry)
if (pEntry)
pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
if (!pEntry)
return VERR_CPUM_DB_CPU_NOT_FOUND;
return VERR_NO_MEMORY;
while (cLeft-- > 0)
return rc;
pCurMsr++;
return VINF_SUCCESS;
STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
# ifdef VBOX_WITH_STATISTICS
STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
return VINF_SUCCESS;