41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * CPUM - CPU database part.
aae8a6a38fd27661046ab1d06cb2cb5c096c40edvboxsync * Copyright (C) 2013-2015 Oracle Corporation
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * available from http://www.virtualbox.org. This file is free software;
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * you can redistribute it and/or modify it under the terms of the GNU
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * General Public License (GPL) as published by the Free Software
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/*******************************************************************************
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync* Header Files *
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync*******************************************************************************/
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/*******************************************************************************
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync* Structures and Typedefs *
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync*******************************************************************************/
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The CPU name. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The full CPU name. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The CPU vendor (CPUMCPUVENDOR). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The CPU family. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The CPU model. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The CPU stepping. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The microarchitecture. */
ecb98c0e709a5cebd8877fb39f61a821804024bcvboxsync /** Scalable bus frequency used for reporting other frequencies. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** Flags (TBD). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The maximum physical address with of the CPU. This should correspond to
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * the value in CPUID leaf 0x80000008 when present. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** Pointer to an array of CPUID leaves. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The number of CPUID leaves in the array paCpuIdLeaves points to. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The method used to deal with unknown CPUID leaves. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The default unknown CPUID value. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** MSR mask. Several microarchitectures ignore higher bits of the */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The number of ranges in the table pointed to b paMsrRanges. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** MSR ranges for this CPU. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/*******************************************************************************
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync* Defined Constants And Macros *
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync*******************************************************************************/
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** @def NULL_ALONE
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * For eliminating an unnecessary data dependency in standalone builds (for
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * VBoxSVC). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** @def ZERO_ALONE
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * For eliminating an unnecessary data size dependency in standalone builds (for
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * VBoxSVC). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** @name Short macros for the MSR range entries.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * These are rather cryptic, but this is to reduce the attack on the right
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Alias one MSR onto another (a_uTarget). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Functions handles everything. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Functions handles everything, with GP mask. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Function handlers, read-only. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Function handlers, ignore all writes. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Function handlers, with value. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Function handlers, with write ignore mask. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Function handlers, extended version. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Function handlers, with CPUMCPU storage variable. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Read-only fixed value. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Read-only fixed value, ignores all writes. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Read fixed value, ignore writes outside GP mask. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Read fixed value, extended version with both GP and ignore masks. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** The short form, no CPUM backing. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Range: Functions handles everything. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Range: Read fixed value, read-only. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Range: Read fixed value, ignore writes. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Range: The short form, no CPUM backing. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Internal form used by the macros. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync { 0 }, { 0 }, { 0 }, { 0 } }
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * The database entries.
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync * 1. The first entry is special. It is the fallback for unknown
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync * processors. Thus, it better be pretty representative.
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync * 2. The first entry for a CPU vendor is likewise important as it is
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync * the default entry for that vendor.
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync * Generally we put the most recent CPUs first, since these tend to have the
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync * most complicated and backwards compatible list of MSRs.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsyncstatic CPUMDBENTRY const * const g_apCpumDbEntries[] =
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Binary search used by cpumR3MsrRangesInsert and has some special properties
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * wrt to mismatches.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @returns Insert location.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @param paMsrRanges The MSR ranges to search.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @param cMsrRanges The number of MSR ranges.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @param uMsr What to search for.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsyncstatic uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Ensures that there is space for at least @a cNewRanges in the table,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * reallocating the table if necessary.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @returns Pointer to the MSR ranges on success, NULL on failure. On failure
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @a *ppaMsrRanges is freed and set to NULL.
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * @param pVM Pointer to the VM, used as the heap selector.
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * Passing NULL uses the host-context heap, otherwise
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * the VM's hyper heap is used.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @param ppaMsrRanges The variable pointing to the ranges (input/output).
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @param cMsrRanges The current number of ranges.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @param cNewRanges The number of ranges to be added.
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsyncstatic PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
5fb8c92d14bd1abb521cde47c8cf1b79eb5622d0vboxsync * We're using the hyper heap now, but when the range array was copied over to it from
5fb8c92d14bd1abb521cde47c8cf1b79eb5622d0vboxsync * the host-context heap, we only copy the exact size and not the ensured size.
5fb8c92d14bd1abb521cde47c8cf1b79eb5622d0vboxsync * See @bugref{7270}.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
5fb8c92d14bd1abb521cde47c8cf1b79eb5622d0vboxsync LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync pvNew = RTMemRealloc(*ppaMsrRanges, cNew * sizeof(**ppaMsrRanges));
5fb8c92d14bd1abb521cde47c8cf1b79eb5622d0vboxsync /* Update R0 and RC pointers. */
5fb8c92d14bd1abb521cde47c8cf1b79eb5622d0vboxsync Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
5fb8c92d14bd1abb521cde47c8cf1b79eb5622d0vboxsync pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
5fb8c92d14bd1abb521cde47c8cf1b79eb5622d0vboxsync pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, *ppaMsrRanges);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Inserts a new MSR range in into an sorted MSR range array.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * If the new MSR range overlaps existing ranges, the existing ones will be
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * adjusted/removed to fit in the new one.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @returns VBox status code.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @retval VINF_SUCCESS
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @retval VERR_NO_MEMORY
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * @param pVM Pointer to the VM, used as the heap selector.
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * Passing NULL uses the host-context heap, otherwise
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * the hyper heap.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @param ppaMsrRanges The variable pointing to the ranges (input/output).
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * Must be NULL if using the hyper heap.
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * @param pcMsrRanges The variable holding number of ranges. Must be NULL
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * if using the hyper heap.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @param pNewRange The new range.
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsyncint cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * Validate and use the VM's MSR ranges array if we are using the hyper heap.
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Optimize the linear insertion case where we add new entries at the end.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync && paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync Assert(i == cMsrRanges || pNewRange->uFirst <= paMsrRanges[i].uLast);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync Assert(i == 0 || pNewRange->uFirst > paMsrRanges[i - 1].uLast);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Adding an entirely new entry?
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Replace existing entry?
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Splitting an existing entry?
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Complicated scenarios that can affect more than one range.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * The current code does not optimize memmove calls when replacing
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * one or more existing ranges, because it's tedious to deal with and
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * not expected to be a frequent usage scenario.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /* Adjust start of first match? */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /* Adjust end of first match? */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /* Replace the whole first match (lazy bird). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /* Do the new range affect more ranges? */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /* Adjust the start of it, then we're done. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /* Remove it entirely. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /* Now, perform a normal insertion. */
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
9d7b020d79101e5c23c1f58a0ce5fa49488ccf73vboxsync * Worker for cpumR3MsrApplyFudge that applies one table.
9d7b020d79101e5c23c1f58a0ce5fa49488ccf73vboxsync * @returns VBox status code.
9d7b020d79101e5c23c1f58a0ce5fa49488ccf73vboxsync * @param pVM Pointer to the cross context VM structure.
9d7b020d79101e5c23c1f58a0ce5fa49488ccf73vboxsync * @param paRanges Array of MSRs to fudge.
9d7b020d79101e5c23c1f58a0ce5fa49488ccf73vboxsync * @param cRanges Number of MSRs in the array.
9d7b020d79101e5c23c1f58a0ce5fa49488ccf73vboxsyncstatic int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
9d7b020d79101e5c23c1f58a0ce5fa49488ccf73vboxsync LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
311878f2d5c242b01836760b93577a1a5f6d63b7vboxsync int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync * Fudges the MSRs that guest are known to access in some odd cases.
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync * A typical example is a VM that has been moved between different hosts where
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync * for instance the cpu vendor differs.
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync * @returns VBox status code.
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync * @param pVM Pointer to the cross context VM structure.
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
6ea079037b825359aab1ba56bb4b9e202ecea648vboxsync MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
9d7b020d79101e5c23c1f58a0ce5fa49488ccf73vboxsync int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
9d7b020d79101e5c23c1f58a0ce5fa49488ccf73vboxsync * XP might mistake opterons and other newer CPUs for P4s.
9d7b020d79101e5c23c1f58a0ce5fa49488ccf73vboxsync MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
34c7651e294c98d15cac0b35e5a585404c0d26aavboxsync rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsyncint cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Create a CPU database entry for the host CPU. This means getting
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * the CPUID bits from the real CPU and grabbing the closest matching
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * database entry for MSRs.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /* Lookup database entry for MSRs. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync /* Match against Family, Microarch, model and stepping. Except
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync for family, always match the closer with preference given to
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync the later/older ones. */
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync /* Perfect match. */
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync ? pCur->uStepping < pEntry->uStepping || pEntry->uStepping < uStepping
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync ? pCur->uModel < pEntry->uModel || pEntry->uModel < uModel
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync ? pCur->enmMicroarch < pEntry->enmMicroarch || pEntry->enmMicroarch < enmMicroarch
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync /* We don't do closeness matching on family, we use the first
90ce7af4052f25f4a94d18c0ef86181971396cd3vboxsync entry for the CPU vendor instead. (P4 workaround.) */
f2b0fba08946caa4699216915ed6cc13645f4693vboxsync LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
f2b0fba08946caa4699216915ed6cc13645f4693vboxsync LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * We're supposed to be emulating a specific CPU that is included in
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * our CPU database. The CPUID tables needs to be copied onto the
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * heap so the caller can modify them and so they can be freed like
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * in the host case above.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDup(pEntry->paCpuIdLeaves,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
f2b0fba08946caa4699216915ed6cc13645f4693vboxsync LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
ecb98c0e709a5cebd8877fb39f61a821804024bcvboxsync pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Copy the MSR range.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync while (cLeft-- > 0)
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync Assert(!paMsrs); /* The above function frees this. */
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * Insert an MSR range into the VM.
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * If the new MSR range overlaps existing ranges, the existing ones will be
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * adjusted/removed to fit in the new one.
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * @returns VBox status code.
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * @param pVM Pointer to the cross context VM structure.
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync * @param pNewRange Pointer to the MSR range being inserted.
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsyncVMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
1bc6deb47f3874f8d1d7a7b6e01d7d7c314d808fvboxsync return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges */, NULL /* pcMsrRanges */, pNewRange);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Register statistics for the MSRs.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * This must not be called before the MSRs have been finalized and moved to the
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * hyper heap.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @returns VBox status code.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @param pVM Pointer to the cross context VM structure.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Global statistics.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
728b52f802ac19865bd4aa8e9ade8f506a9e6c10vboxsync STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
728b52f802ac19865bd4aa8e9ade8f506a9e6c10vboxsync STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Per range.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync# endif /* VBOX_WITH_STATISTICS */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#endif /* !CPUM_DB_STANDALONE */