CPUMR3CpuId.cpp revision 3005ffba3f5479638902e025ca1598d60491afa3
/* $Id$ */
/** @file
* CPUM - CPU ID part.
*/
/*
* Copyright (C) 2013-2015 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_CPUM
#include "CPUMInternal.h"
#include <iprt/asm-amd64-x86.h>
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
#define CPUM_CPUID_MAX_LEAVES 2048
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/**
* The intel pentium family.
*/
static const CPUMMICROARCH g_aenmIntelFamily06[] =
{
/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
/* [31(0x1f)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
/* [45(0x2d)] = */ kCpumMicroarch_Intel_Core7_SandyBridge, /* SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
/* [71(0x47)] = */ kCpumMicroarch_Intel_Unknown,
/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
/* [76(0x4c)] = */ kCpumMicroarch_Intel_Unknown,
/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
/* [78(0x4e)] = */ kCpumMicroarch_Intel_Unknown,
/* [79(0x4f)] = */ kCpumMicroarch_Intel_Unknown,
};
/**
* Figures out the (sub-)micro architecture given a bit of CPUID info.
*
* @returns Micro architecture.
* @param enmVendor The CPU vendor .
* @param bFamily The CPU family.
* @param bModel The CPU model.
* @param bStepping The CPU stepping.
*/
{
if (enmVendor == CPUMCPUVENDOR_AMD)
{
switch (bFamily)
{
case 0x03: return kCpumMicroarch_AMD_Am386;
case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
case 0x06:
switch (bModel)
{
case 0: return kCpumMicroarch_AMD_K7_Palomino;
case 1: return kCpumMicroarch_AMD_K7_Palomino;
case 2: return kCpumMicroarch_AMD_K7_Palomino;
case 3: return kCpumMicroarch_AMD_K7_Spitfire;
case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
case 6: return kCpumMicroarch_AMD_K7_Palomino;
case 7: return kCpumMicroarch_AMD_K7_Morgan;
case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
}
return kCpumMicroarch_AMD_K7_Unknown;
case 0x0f:
/*
* This family is a friggin mess. Trying my best to make some
* sense out of it. Too much happened in the 0x0f family to
* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
*
* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
* cpu-world.com, and other places:
* - 130nm:
* - 90nm:
* - 90nm introducing Dual core:
* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
*
* - 65nm:
*/
if (bModel < 0x10)
return kCpumMicroarch_AMD_K8_130nm;
return kCpumMicroarch_AMD_K8_65nm;
if (bModel >= 0x40)
return kCpumMicroarch_AMD_K8_90nm_AMDV;
switch (bModel)
{
case 0x21:
case 0x23:
case 0x2b:
case 0x2f:
case 0x37:
case 0x3f:
}
return kCpumMicroarch_AMD_K8_90nm;
case 0x10:
return kCpumMicroarch_AMD_K10;
case 0x11:
return kCpumMicroarch_AMD_K10_Lion;
case 0x12:
return kCpumMicroarch_AMD_K10_Llano;
case 0x14:
return kCpumMicroarch_AMD_Bobcat;
case 0x15:
switch (bModel)
{
case 0x11: /* ?? */
case 0x12: /* ?? */
}
return kCpumMicroarch_AMD_15h_Unknown;
case 0x16:
return kCpumMicroarch_AMD_Jaguar;
}
return kCpumMicroarch_AMD_Unknown;
}
if (enmVendor == CPUMCPUVENDOR_INTEL)
{
switch (bFamily)
{
case 3:
return kCpumMicroarch_Intel_80386;
case 4:
return kCpumMicroarch_Intel_80486;
case 5:
return kCpumMicroarch_Intel_P5;
case 6:
return g_aenmIntelFamily06[bModel];
case 15:
switch (bModel)
{
case 0: return kCpumMicroarch_Intel_NB_Willamette;
case 1: return kCpumMicroarch_Intel_NB_Willamette;
case 2: return kCpumMicroarch_Intel_NB_Northwood;
case 3: return kCpumMicroarch_Intel_NB_Prescott;
case 6: return kCpumMicroarch_Intel_NB_CedarMill;
case 7: return kCpumMicroarch_Intel_NB_Gallatin;
default: return kCpumMicroarch_Intel_NB_Unknown;
}
break;
/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
case 1:
return kCpumMicroarch_Intel_8086;
case 2:
return kCpumMicroarch_Intel_80286;
}
return kCpumMicroarch_Intel_Unknown;
}
if (enmVendor == CPUMCPUVENDOR_VIA)
{
switch (bFamily)
{
case 5:
switch (bModel)
{
case 1: return kCpumMicroarch_Centaur_C6;
case 4: return kCpumMicroarch_Centaur_C6;
case 8: return kCpumMicroarch_Centaur_C2;
case 9: return kCpumMicroarch_Centaur_C3;
}
break;
case 6:
switch (bModel)
{
case 5: return kCpumMicroarch_VIA_C3_M2;
case 6: return kCpumMicroarch_VIA_C3_C5A;
case 8: return kCpumMicroarch_VIA_C3_C5N;
case 10: return kCpumMicroarch_VIA_C7_C5J;
case 15: return kCpumMicroarch_VIA_Isaiah;
}
break;
}
return kCpumMicroarch_VIA_Unknown;
}
if (enmVendor == CPUMCPUVENDOR_CYRIX)
{
switch (bFamily)
{
case 4:
switch (bModel)
{
case 9: return kCpumMicroarch_Cyrix_5x86;
}
break;
case 5:
switch (bModel)
{
case 2: return kCpumMicroarch_Cyrix_M1;
case 4: return kCpumMicroarch_Cyrix_MediaGX;
case 5: return kCpumMicroarch_Cyrix_MediaGXm;
}
break;
case 6:
switch (bModel)
{
case 0: return kCpumMicroarch_Cyrix_M2;
}
break;
}
return kCpumMicroarch_Cyrix_Unknown;
}
return kCpumMicroarch_Unknown;
}
/**
* Translates a microarchitecture enum value to the corresponding string
* constant.
*
* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
* NULL if the value is invalid.
*
* @param enmMicroarch The enum value to convert.
*/
{
switch (enmMicroarch)
{
case kCpumMicroarch_Invalid:
case kCpumMicroarch_Intel_End:
case kCpumMicroarch_AMD_End:
case kCpumMicroarch_VIA_End:
case kCpumMicroarch_Cyrix_End:
case kCpumMicroarch_32BitHack:
break;
/* no default! */
}
return NULL;
}
/**
* Gets a matching leaf in the CPUID leaf array.
*
* @returns Pointer to the matching leaf, or NULL if not found.
* @param paLeaves The CPUID leaves to search. This is sorted.
* @param cLeaves The number of leaves in the array.
* @param uLeaf The leaf to locate.
* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
*/
static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
{
/* Lazy bird does linear lookup here since this is only used for the
occational CPUID overrides. */
return &paLeaves[i];
return NULL;
}
/**
* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
*
* @returns true if found, false it not.
* @param paLeaves The CPUID leaves to search. This is sorted.
* @param cLeaves The number of leaves in the array.
* @param uLeaf The leaf to locate.
* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
* @param pLegacy The legacy output leaf.
*/
static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
{
if (pLeaf)
{
return true;
}
return false;
}
/**
* Ensures that the CPUID leaf array can hold one more leaf.
*
* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
* failure.
* @param pVM Pointer to the VM, used as the heap selector. Passing
* NULL uses the host-context heap, otherwise the VM's
* hyper heap is used.
* @param ppaLeaves Pointer to the variable holding the array pointer
* @param cLeaves The current array size.
*
* @remarks This function will automatically update the R0 and RC pointers when
* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
* be the corresponding VM's CPUID arrays (which is asserted).
*/
{
/*
* If pVM is not specified, we're on the regular heap and can waste a
* little space to speed things up.
*/
if (!pVM)
{
{
if (pvNew)
else
{
}
}
}
/*
* Otherwise, we're on the hyper heap and are probably just inserting
* one or two leaves and should conserve space.
*/
else
{
#ifdef IN_VBOX_CPU_REPORT
#else
if (RT_SUCCESS(rc))
{
/* Update the R0 and RC pointers. */
}
else
{
}
#endif
}
return *ppaLeaves;
}
/**
* Append a CPUID leaf or sub-leaf.
*
* ASSUMES linear insertion order, so we'll won't need to do any searching or
* replace anything. Use cpumR3CpuIdInsert() for those cases.
*
* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
* the caller need do no more work.
* @param ppaLeaves Pointer to the the pointer to the array of sorted
* CPUID leaves and sub-leaves.
* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
* @param uLeaf The leaf we're adding.
* @param uSubLeaf The sub-leaf number.
* @param fSubLeafMask The sub-leaf mask.
* @param uEax The EAX value.
* @param uEbx The EBX value.
* @param uEcx The ECX value.
* @param uEdx The EDX value.
* @param fFlags The flags.
*/
{
return VERR_NO_MEMORY;
*pcLeaves += 1;
return VINF_SUCCESS;
}
/**
* Checks that we've updated the CPUID leaves array correctly.
*
* This is a no-op in non-strict builds.
*
* @param paLeaves The leaves array.
* @param cLeaves The number of leaves.
*/
{
#ifdef VBOX_STRICT
AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
else
{
("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
}
#else
#endif
}
/**
* Inserts a CPU ID leaf, replacing any existing ones.
*
* When inserting a simple leaf where we already got a series of subleaves with
* the same leaf number (eax), the simple leaf will replace the whole series.
*
* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
* host-context heap and has only been allocated/reallocated by the
* cpumR3CpuIdEnsureSpace function.
*
* @returns VBox status code.
* @param pVM Pointer to the VM, used as the heap selector.
* Passing NULL uses the host-context heap, otherwise
* the VM's hyper heap is used.
* @param ppaLeaves Pointer to the the pointer to the array of sorted
* CPUID leaves and sub-leaves. Must be NULL if using
* the hyper heap.
* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must be
* NULL if using the hyper heap.
* @param pNewLeaf Pointer to the data of the new leaf we're about to
* insert.
*/
static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
{
/*
* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
*/
if (pVM)
{
}
/*
* Validate the new leaf a little.
*/
/*
* Find insertion point. The lazy bird uses the same excuse as in
* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
*/
uint32_t i;
if ( cLeaves > 0
{
/* Add at end. */
i = cLeaves;
}
else if ( cLeaves > 0
{
/* Either replacing the last leaf or dealing with sub-leaves. Spool
back to the first sub-leaf to pretend we did the linear search. */
i = cLeaves - 1;
while ( i > 0
i--;
}
else
{
/* Linear search from the start. */
i = 0;
while ( i < cLeaves
i++;
}
if ( i < cLeaves
{
{
/*
* The sub-leaf mask differs, replace all existing leaves with the
* same leaf number.
*/
uint32_t c = 1;
while ( i + c < cLeaves
c++;
if (c > 1 && i + c < cLeaves)
{
}
return VINF_SUCCESS;
}
/* Find sub-leaf insertion point. */
while ( i < cLeaves
i++;
/*
* If we've got an exactly matching leaf, replace it.
*/
if ( i < cLeaves
{
return VINF_SUCCESS;
}
}
/*
* Adding a new leaf at 'i'.
*/
if (!paLeaves)
return VERR_NO_MEMORY;
if (i < cLeaves)
*pcLeaves += 1;
return VINF_SUCCESS;
}
/**
* Removes a range of CPUID leaves.
*
* This will not reallocate the array.
*
* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
* @param pcLeaves Where we keep the leaf count for @a paLeaves.
* @param uFirst The first leaf.
* @param uLast The last leaf.
*/
static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
{
/*
* Find the first one.
*/
iFirst++;
/*
* Find the end (last + 1).
*/
iEnd++;
/*
* Adjust the array if anything needs removing.
*/
{
}
}
/**
* Checks if ECX make a difference when reading a given CPUID leaf.
*
* @returns @c true if it does, @c false if it doesn't.
* @param uLeaf The leaf we're reading.
* @param pcSubLeaves Number of sub-leaves accessible via ECX.
* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
* final sub-leaf (for leaf 0xb only).
*/
static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t *pcSubLeaves, bool *pfFinalEcxUnchanged)
{
*pfFinalEcxUnchanged = false;
/* Look for sub-leaves. */
for (;;)
{
break;
/* Advance / give up. */
uSubLeaf++;
if (uSubLeaf >= 64)
{
*pcSubLeaves = 1;
return false;
}
}
/* Count sub-leaves. */
uSubLeaf = 0;
for (;;)
{
/* Figuring out when to stop isn't entirely straight forward as we need
to cover undocumented behavior up to a point and implementation shortcuts. */
/* 1. Look for zero values. */
if ( auCur[0] == 0
&& auCur[1] == 0
{
cRepeats = 0;
break;
}
/* 2. Look for more than 4 repeating value sets. */
{
cRepeats++;
if (cRepeats > 4)
break;
}
else
cRepeats = 0;
/* 3. Leaf 0xb level type 0 check. */
if ( uLeaf == 0xb
{
cRepeats = 0;
break;
}
/* 99. Give up. */
if (uSubLeaf >= 128)
{
#ifndef IN_VBOX_CPU_REPORT
/* Ok, limit it according to the documentation if possible just to
avoid annoying users with these detection issues. */
if (uLeaf == 0x4)
cDocLimit = 4;
else if (uLeaf == 0x7)
cDocLimit = 1;
else if (uLeaf == 0xf)
cDocLimit = 2;
if (cDocLimit != UINT32_MAX)
{
return true;
}
#endif
return true;
}
/* Advance. */
uSubLeaf++;
}
/* Standard exit. */
if (*pcSubLeaves == 0)
*pcSubLeaves = 1;
return true;
}
/**
* Gets a CPU ID leaf.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pLeaf Where to store the found leaf.
* @param uLeaf The leaf to locate.
* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
*/
{
PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
if (pcLeaf)
{
return VINF_SUCCESS;
}
return VERR_NOT_FOUND;
}
/**
* Inserts a CPU ID leaf, replacing any existing ones.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pNewLeaf Pointer to the leaf being inserted.
*/
{
/*
* Validate parameters.
*/
/*
* Disallow replacing CPU ID leaves that this API currently cannot manage.
* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
*/
{
return VERR_NOT_SUPPORTED;
}
}
/**
* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
*
* @returns VBox status code.
* @param ppaLeaves Where to return the array pointer on success.
* Use RTMemFree to release.
* @param pcLeaves Where to return the size of the array on
* success.
*/
{
*pcLeaves = 0;
/*
* Try out various candidates. This must be sorted!
*/
{
{ UINT32_C(0x00000000), false },
{ UINT32_C(0x10000000), false },
{ UINT32_C(0x20000000), false },
{ UINT32_C(0x30000000), false },
{ UINT32_C(0x40000000), false },
{ UINT32_C(0x50000000), false },
{ UINT32_C(0x60000000), false },
{ UINT32_C(0x70000000), false },
{ UINT32_C(0x80000000), false },
{ UINT32_C(0x80860000), false },
{ UINT32_C(0x8ffffffe), true },
{ UINT32_C(0x8fffffff), true },
{ UINT32_C(0x90000000), false },
{ UINT32_C(0xa0000000), false },
{ UINT32_C(0xb0000000), false },
{ UINT32_C(0xc0000000), false },
{ UINT32_C(0xd0000000), false },
{ UINT32_C(0xe0000000), false },
{ UINT32_C(0xf0000000), false },
};
{
/*
* Does EAX look like a typical leaf count value?
*/
{
/* Yes, dump them. */
while (cLeaves-- > 0)
{
/* There are currently three known leaves containing an APIC ID
that needs EMT specific attention */
if (uLeaf == 1)
&& ( uEax
|| uEbx
|| uEdx
/* Check three times here to reduce the chance of CPU migration
resulting in false positives with things like the APIC ID. */
bool fFinalEcxUnchanged;
{
if (cSubLeaves > 16)
{
/* This shouldn't happen. But in case it does, file all
relevant details in the release log. */
LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
LogRel(("------------------ dump of problematic subleaves ------------------\n"));
{
LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
}
LogRel(("----------------- dump of what we've found so far -----------------\n"));
LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
}
if (fFinalEcxUnchanged)
{
if (RT_FAILURE(rc))
return rc;
}
}
else
{
if (RT_FAILURE(rc))
return rc;
}
/* next */
uLeaf++;
}
}
/*
* Special CPUIDs needs special handling as they don't follow the
* leaf count principle used above.
*/
{
bool fKeep = false;
fKeep = true;
else if ( uLeaf == 0x8fffffff
fKeep = true;
if (fKeep)
{
if (RT_FAILURE(rc))
return rc;
}
}
}
return VINF_SUCCESS;
}
/**
* Determines the method the CPU uses to handle unknown CPUID leaves.
*
* @returns VBox status code.
* @param penmUnknownMethod Where to return the method.
* @param pDefUnknown Where to return default unknown values. This
* will be set, even if the resulting method
* doesn't actually needs it.
*/
VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
{
if (!ASMIsValidExtRange(uLastExt))
uLastExt = 0x80000000;
{
uLastStd + 1,
uLastStd + 5,
uLastStd + 8,
uLastStd + 32,
uLastStd + 251,
uLastExt + 1,
uLastExt + 8,
uLastExt + 15,
uLastExt + 63,
uLastExt + 255,
0x7fbbffcc,
0x833f7872,
0xefff2353,
0x35779456,
0x1ef6d33e,
};
static const uint32_t s_auValues[] =
{
0xa95d2156,
0x00000001,
0x00000002,
0x00000008,
0x00000000,
0x55773399,
0x93401769,
0x12039587,
};
/*
* Simple method, all zeros.
*/
pDefUnknown->uEax = 0;
pDefUnknown->uEbx = 0;
pDefUnknown->uEcx = 0;
pDefUnknown->uEdx = 0;
/*
* Intel has been observed returning the last standard leaf.
*/
while (cChecks > 0)
{
break;
cChecks--;
}
if (cChecks == 0)
{
/* Now, what happens when the input changes? Esp. ECX. */
uint32_t cLastWithEcx = 0;
while (cValues > 0)
{
while (cChecks > 0)
{
ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
{
cSame++;
cLastWithEcx++;
}
cLastWithEcx++;
else
cNeither++;
cTotal++;
cChecks--;
}
cValues--;
}
Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
else if (cLastWithEcx == cTotal)
else
return VINF_SUCCESS;
}
/*
* Unchanged register values?
*/
while (cChecks > 0)
{
while (cValues > 0)
{
break;
cValues--;
}
if (cValues != 0)
break;
cChecks--;
}
if (cChecks == 0)
{
return VINF_SUCCESS;
}
/*
* Just go with the simple method.
*/
return VINF_SUCCESS;
}
/**
* Translates a unknow CPUID leaf method into the constant name (sans prefix).
*
* @returns Read only name string.
* @param enmUnknownMethod The method to translate.
*/
{
switch (enmUnknownMethod)
{
case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
case CPUMUNKNOWNCPUID_INVALID:
case CPUMUNKNOWNCPUID_END:
break;
}
return "Invalid-unknown-CPUID-method";
}
/**
* Detect the CPU vendor give n the
*
* @returns The vendor.
* @param uEAX EAX from CPUID(0).
* @param uEBX EBX from CPUID(0).
* @param uECX ECX from CPUID(0).
* @param uEDX EDX from CPUID(0).
*/
VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
{
if (ASMIsValidStdRange(uEAX))
{
return CPUMCPUVENDOR_AMD;
return CPUMCPUVENDOR_INTEL;
return CPUMCPUVENDOR_VIA;
return CPUMCPUVENDOR_CYRIX;
/* "Geode by NSC", example: family 5, model 9. */
/** @todo detect the other buggers... */
}
return CPUMCPUVENDOR_UNKNOWN;
}
/**
* Translates a CPU vendor enum value into the corresponding string constant.
*
* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
* value name. This can be useful when generating code.
*
* @returns Read only name string.
* @param enmVendor The CPU vendor value.
*/
{
switch (enmVendor)
{
case CPUMCPUVENDOR_INTEL: return "INTEL";
case CPUMCPUVENDOR_AMD: return "AMD";
case CPUMCPUVENDOR_VIA: return "VIA";
case CPUMCPUVENDOR_CYRIX: return "CYRIX";
case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
case CPUMCPUVENDOR_INVALID:
case CPUMCPUVENDOR_32BIT_HACK:
break;
}
return "Invalid-cpu-vendor";
}
static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
{
/* Could do binary search, doing linear now because I'm lazy. */
while (cLeaves-- > 0)
{
return pLeaf;
pLeaf++;
}
return NULL;
}
static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
{
if ( !pLeaf
return pLeaf;
/* Linear sub-leaf search. Lazy as usual. */
while ( cLeaves-- > 0
{
return pLeaf;
pLeaf++;
}
return NULL;
}
{
if (cLeaves >= 2)
{
pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
if (pLeaf)
else
/* Standard features. */
/* Structured extended features. */
if (pSxfLeaf0)
{
}
if (pMWaitLeaf)
{
pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
}
/* Extended features. */
if (pExtLeaf)
{
}
if ( pExtLeaf
{
/* AMD features. */
}
/*
* Quirks.
*/
/*
* Max extended (/FPU) state.
*/
if (pFeatures->fXSaveRstor)
{
if (pXStateLeaf0)
{
{
}
else
AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
pFeatures->fXSaveRstor = 0);
}
else
AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
pFeatures->fXSaveRstor = 0);
}
}
else
return VINF_SUCCESS;
}
/*
*
* Init related code.
* Init related code.
* Init related code.
*
*
*/
#ifdef VBOX_IN_VMM
/**
* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
*
* This ignores the fSubLeafMask.
*
* @returns Pointer to the matching leaf, or NULL if not found.
* @param paLeaves The CPUID leaves to search. This is sorted.
* @param cLeaves The number of leaves in the array.
* @param uLeaf The leaf to locate.
* @param uSubLeaf The subleaf to locate.
*/
{
if (iEnd)
{
for (;;)
{
{
if (i > iBegin)
iEnd = i;
else
break;
}
{
if (i + 1 < iEnd)
iBegin = i + 1;
else
break;
}
else
return &paLeaves[i];
}
}
return NULL;
}
/**
* Loads MSR range overrides.
*
* This must be called before the MSR ranges are moved from the normal heap to
* the hyper heap!
*
* @returns VBox status code (VMSetError called).
* @param pVM Pointer to the cross context VM structure
* @param pMsrNode The CFGM node with the MSR overrides.
*/
{
{
/*
* Assemble a valid MSR range.
*/
MsrRange.offCpumCpu = 0;
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
char szType[32];
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
{
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
}
else
/*
* MSR ranges).
*/
rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
&MsrRange);
if (RT_FAILURE(rc))
}
return VINF_SUCCESS;
}
/**
* Loads CPUID leaf overrides.
*
* This must be called before the CPUID leaves are moved from the normal
* heap to the hyper heap!
*
* @returns VBox status code (VMSetError called).
* @param pVM Pointer to the cross context VM structure
* @param pParentNode The CFGM node with the CPUID leaves.
* @param pszLabel How to label the overrides we're loading.
*/
{
{
/*
* Get the leaf and subleaf numbers.
*/
char szName[128];
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
/* The leaf number is either specified directly or thru the node name. */
if (rc == VERR_CFGM_VALUE_NOT_FOUND)
{
if (rc != VINF_SUCCESS)
}
else if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
/*
* Look up the specified leaf, since the output register values
* defaults to any existing values. This allows overriding a single
* register, without needing to know the other values.
*/
if (pLeaf)
else
if (RT_FAILURE(rc))
if (RT_FAILURE(rc))
if (RT_FAILURE(rc))
if (RT_FAILURE(rc))
/*
* Insert the leaf into the table (replaces existing ones).
*/
rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
&Leaf);
if (RT_FAILURE(rc))
}
return VINF_SUCCESS;
}
/**
* Fetches overrides for a CPUID leaf.
*
* @returns VBox status code.
* @param pLeaf The leaf to load the overrides into.
* @param pCfgNode The CFGM node containing the overrides
* @param iLeaf The CPUID leaf number.
*/
{
if (pLeafNode)
{
if (RT_SUCCESS(rc))
else
if (RT_SUCCESS(rc))
else
if (RT_SUCCESS(rc))
else
if (RT_SUCCESS(rc))
else
}
return VINF_SUCCESS;
}
/**
* Load the overrides for a set of CPUID leaves.
*
* @returns VBox status code.
* @param paLeaves The leaf array.
* @param cLeaves The number of leaves.
* @param uStart The start leaf number.
* @param pCfgNode The CFGM node containing the overrides
*/
static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
{
{
if (RT_FAILURE(rc))
return rc;
}
return VINF_SUCCESS;
}
/**
* Init a set of host CPUID leaves.
*
* @returns VBox status code.
* @param paLeaves The leaf array.
* @param cLeaves The number of leaves.
* @param uStart The start leaf number.
*/
static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
{
/* Using the ECX variant for all of them can't hurt... */
ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].uEax, &paLeaves[i].uEbx, &paLeaves[i].uEcx, &paLeaves[i].uEdx);
/* Load CPUID leaf override; we currently don't care if the user
specifies features the host CPU doesn't support. */
}
static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
{
/*
* Install the CPUID information.
*/
Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
/*
* Update the default CPUID leaf if necessary.
*/
{
{
/* We don't use CPUID(0).eax here because of the NT hack that only
changes that value without actually removing any leaves. */
uint32_t i = 0;
{
i++;
}
break;
}
default:
break;
}
/*
* Explode the guest CPU features.
*/
rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
/*
* Adjust the scalable bus frequency according to the CPUID information
* we're now using.
*/
pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
/*
* Populate the legacy arrays. Currently used for everything, later only
* for patch manager.
*/
{
};
{
while (cLeft-- > 0)
{
uLeaf--;
pLegacyLeaf--;
if (pLeaf)
{
}
else
}
}
return VINF_SUCCESS;
}
/** @name Instruction Set Extension Options
* @{ */
/** Configuration option type (extended boolean, really). */
typedef uint8_t CPUMISAEXTCFG;
/** Always disable the extension. */
#define CPUMISAEXTCFG_DISABLED false
/** Enable the extension if it's supported by the host CPU. */
#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
/** Enable the extension if it's supported by the host CPU, but don't let
* the portable CPUID feature disable it. */
/** Always enable the extension. */
/** @} */
/**
* CPUID Configuration (from CFGM).
*
* @remarks The members aren't document since we would only be duplicating the
* \@cfgm entries in cpumR3CpuIdReadConfig.
*/
typedef struct CPUMCPUIDCONFIG
{
bool fSyntheticCpu;
bool fNt4LeafLimit;
bool fInvariantTsc;
char szCpuName[128];
/** Pointer to CPUID config (from CFGM). */
typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
/**
* Insert hypervisor identification leaves.
*
* We only return minimal information, primarily ensuring that the
* 0x40000000 function returns 0x40000001 and identifying ourselves.
* Hypervisor-specific interface is supported through GIM which will
* modify these leaves if required depending on the GIM provider.
*
* @returns VBox status code.
* @param pCpum The CPUM instance data.
* @param pConfig The CPUID configuration we've read from CFGM.
*/
{
NewLeaf.fSubLeafMask = 0;
int rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves, &NewLeaf);
return VINF_SUCCESS;
}
/**
* Mini CPU selection support for making Mac OS X happy.
*
* Executes the /CPUM/MaxIntelFamilyModelStep config.
*
* @param pCpum The CPUM instance data.
* @param pConfig The CPUID configuration we've read from CFGM.
*/
{
{
0);
{
if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
uNew |= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
}
}
}
/**
* Limit it the number of entries, zapping the remainder.
*
* The limits are masking off stuff about power saving and similar, this
* is perhaps a bit crudely done as there is probably some relatively harmless
* info too in these leaves (like words about having a constant TSC).
*
* @param pCpum The CPUM instance data.
* @param pConfig The CPUID configuration we've read from CFGM.
*/
{
/*
* Standard leaves.
*/
if (pCurLeaf)
{
{
{
}
/* NT4 hack, no zapping of extra leaves here. */
}
else
{
}
}
/*
* Extended leaves.
*/
uSubLeaf = 0;
if (pCurLeaf)
{
{
{
}
}
else
{
}
}
/*
* Centaur leaves (VIA).
*/
uSubLeaf = 0;
if (pCurLeaf)
{
{
{
}
}
else
{
}
}
}
/**
* Clears a CPUID leaf and all sub-leaves (to zero).
*
* @param pCpum The CPUM instance data.
* @param uLeaf The leaf to clear.
*/
{
{
uSubLeaf++;
}
}
/**
* Sanitizes and adjust the CPUID leaves.
*
* Drop features that aren't virtualized (or virtualizable). Adjust information
* and capabilities to fit the virtualized hardware. Remove information the
* guest shouldn't have (because it's wrong in the virtual world or because it
* gives away host details) or that we don't have documentation for and no idea
* what means.
*
* @returns VBox status code.
* @param pVM Pointer to the cross context VM structure (for cCpus).
* @param pCpum The CPUM instance data.
* @param pConfig The CPUID configuration we've read from CFGM.
*/
{
{ \
}
{ \
}
&& ((a_pLeafReg) & (fBitMask)) \
&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
{ \
}
/* Cpuid 1:
* EAX: CPU model, family and stepping.
*
* ECX + EDX: Supported features. Only report features we can support.
* Note! When enabling new features the Synthetic CPU and Portable CPUID
* options may require adjusting (i.e. stripping what was enabled).
*
* EBX: Branding, CLFLUSH line size, logical processors per package and
* initial APIC ID.
*/
PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
//| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
//| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
//| RT_BIT_32(10) - not defined
/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
//| X86_CPUID_FEATURE_EDX_SEP
| X86_CPUID_FEATURE_EDX_PAT /* 16 */
//| X86_CPUID_FEATURE_EDX_PSN - no serial number.
//| RT_BIT_32(20) - not defined
//| X86_CPUID_FEATURE_EDX_DS - no debug store.
//| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
//| X86_CPUID_FEATURE_EDX_SS - no self snoop.
//| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading/cores - see below.
//| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
//| RT_BIT_32(30) - not defined
//| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
;
pStdFeatureLeaf->uEcx &= 0
//| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
//| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
//| X86_CPUID_FEATURE_ECX_VMX - not virtualized yet.
//| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
//| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
//| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
//| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
//| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
//| X86_CPUID_FEATURE_ECX_TPRUPDATE
//| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
//| X86_CPUID_FEATURE_ECX_PCID - not implemented yet.
//| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
//| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
//| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
//| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
//| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
//| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
;
if (pCpum->u8PortableCpuIdLevel > 0)
{
PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
)));
)));
}
#ifdef VBOX_WITH_MULTI_CORE
{
/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
core times the number of CPU cores per processor */
pStdFeatureLeaf->uEdx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
}
#endif
/* Force standard feature bits. */
/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
* AMD:
* EAX: CPU model, family and stepping.
*
* ECX + EDX: Supported features. Only report features we can support.
* Note! When enabling new features the Synthetic CPU and Portable CPUID
* options may require adjusting (i.e. stripping what was enabled).
* ASSUMES that this is ALWAYS the AMD defined feature set if present.
*
* EBX: Branding ID and package type (or reserved).
*
* Intel and probably most others:
* EAX: 0
* EBX: 0
* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
*/
if (pExtFeatureLeaf)
{
| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
//| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
//| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
//| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
//| RT_BIT_32(10) - reserved
eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
//| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
//| RT_BIT_32(18) - reserved
//| RT_BIT_32(19) - reserved
//| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
//| RT_BIT_32(21) - reserved
//| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
//| RT_BIT_32(28) - reserved
//| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
;
//| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
//| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
//| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
/* Note: This could prevent teleporting from AMD to Intel CPUs! */
| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
//| X86_CPUID_AMD_FEATURE_ECX_OSVW
//| X86_CPUID_AMD_FEATURE_ECX_IBS
//| X86_CPUID_AMD_FEATURE_ECX_XOP
//| X86_CPUID_AMD_FEATURE_ECX_SKINIT
//| X86_CPUID_AMD_FEATURE_ECX_WDT
//| RT_BIT_32(14) - reserved
//| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
//| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
//| RT_BIT_32(17) - reserved
//| RT_BIT_32(18) - reserved
//| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
//| RT_BIT_32(20) - reserved
//| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
//| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
//| RT_BIT_32(23) - reserved
//| RT_BIT_32(24) - reserved
//| RT_BIT_32(25) - reserved
//| RT_BIT_32(26) - reserved
//| RT_BIT_32(27) - reserved
//| RT_BIT_32(28) - reserved
//| RT_BIT_32(29) - reserved
//| RT_BIT_32(30) - reserved
//| RT_BIT_32(31) - reserved
;
#ifdef VBOX_WITH_MULTI_CORE
#endif
if (pCpum->u8PortableCpuIdLevel > 0)
{
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
| UINT32_C(0xff964000)
)));
| RT_BIT(18)
| RT_BIT(19)
| RT_BIT(21)
| RT_BIT(28)
)));
}
/* Force extended feature bits. */
}
/* Cpuid 2:
* Intel: (Nondeterministic) Cache and TLB information
* AMD: Reserved
* VIA: Reserved
* Safe to expose. Restrict the number of calls to 1 since we don't
* implement this kind of subleaves (is there hardware that does??).
*/
{
{
}
uSubLeaf++;
}
/* Cpuid 3:
* Intel: EAX, EBX - reserved (transmeta uses these)
* ECX, EDX - Processor Serial Number if available, otherwise reserved
* AMD: Reserved
* VIA: Reserved
* Safe to expose
*/
{
uSubLeaf = 0;
{
if (pCpum->u8PortableCpuIdLevel > 0)
uSubLeaf++;
}
}
/* Cpuid 4 + ECX:
* Intel: Deterministic Cache Parameters Leaf.
* AMD: Reserved
* VIA: Reserved
* Safe to expose, except for EAX:
* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
* Bits 31-26: Maximum number of processor cores in this physical package**
* Note: These SMP values are constant regardless of ECX
*/
uSubLeaf = 0;
{
pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
#ifdef VBOX_WITH_MULTI_CORE
{
/* One logical processor with possibly multiple cores. */
/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
pCurLeaf->uEax |= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
}
#endif
uSubLeaf++;
}
* Intel: ECX, EDX - reserved
* EAX, EBX - Smallest and largest monitor line size
* AMD: EDX - reserved
* EAX, EBX - Smallest and largest monitor line size
* ECX - extensions (ignored for now)
* VIA: Reserved
* Safe to expose
*/
uSubLeaf = 0;
{
if (pConfig->enmMWaitExtensions)
{
/** @todo: for now we just expose host's MWAIT C-states, although conceptually
it shall be part of our power management virtualization model */
#if 0
/* MWAIT sub C-states */
(0 << 0) /* 0 in C0 */ |
(2 << 4) /* 2 in C1 */ |
(2 << 8) /* 2 in C2 */ |
(2 << 12) /* 2 in C3 */ |
(0 << 16) /* 0 in C4 */
;
#endif
}
else
uSubLeaf++;
}
/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
* Intel: Various stuff.
* AMD: EAX, EBX, EDX - reserved.
* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
* present. Same as intel.
* VIA: ??
*
* We clear everything here for now.
*/
/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
* EAX: Number of sub leaves.
* EBX+ECX+EDX: Feature flags
*
* We only have documentation for one sub-leaf, so clear all other (no need
* to remove them as such, just set them to zero).
*
* Note! When enabling new features the Synthetic CPU and Portable CPUID
* options may require adjusting (i.e. stripping what was enabled).
*/
uSubLeaf = 0;
{
switch (uSubLeaf)
{
case 0:
{
//| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
//| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
//| RT_BIT(2) - reserved
//| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
//| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
//| RT_BIT(6) - reserved
//| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
//| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
//| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
//| X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
//| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
//| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
//| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
//| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
//| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
//| RT_BIT(17) - reserved
//| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
//| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
//| RT_BIT(21) - reserved
//| RT_BIT(22) - reserved
//| RT_BIT(24) - reserved
//| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
//| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
//| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
//| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
//| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
//| RT_BIT(30) - reserved
//| RT_BIT(31) - reserved
;
//| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
;
if (pCpum->u8PortableCpuIdLevel > 0)
{
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
}
/* Force standard feature bits. */
break;
}
default:
/* Invalid index, all values are zero. */
break;
}
uSubLeaf++;
}
/* Cpuid 8: Marked as reserved by Intel and AMD.
* We zero this since we don't know what it may have been used for.
*/
/* Cpuid 9: Direct Cache Access (DCA) Parameters
* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
* EBX, ECX, EDX - reserved.
* AMD: Reserved
* VIA: ??
*
* We zero this.
*/
/* Cpuid 0xa: Architectural Performance Monitor Features
* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
* EBX, ECX, EDX - reserved.
* AMD: Reserved
* VIA: ??
*
* We zero this, for now at least.
*/
/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
* Intel: EAX - APCI ID shift right for next level.
* ECX - Level number (same as input) and level type (1,2,0).
* EDX - Extended initial APIC ID.
* AMD: Reserved
* VIA: ??
*/
uSubLeaf = 0;
{
{
if (bLevelType == 1)
{
/* Thread level - we don't do threads at the moment. */
}
else if (bLevelType == 2)
{
/* Core level. */
pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
#ifdef VBOX_WITH_MULTI_CORE
#endif
}
else
{
}
pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
}
else
{
}
uSubLeaf++;
}
/* Cpuid 0xc: Marked as reserved by Intel and AMD.
* We zero this since we don't know what it may have been used for.
*/
/* Cpuid 0xd + ECX: Processor Extended State Enumeration
* ECX=0: EAX - Valid bits in XCR0[31:0].
* EBX - Maximum state size as per current XCR0 value.
* ECX - Maximum state size for all supported features.
* EDX - Valid bits in XCR0[63:32].
* ECX=1: EAX - Various X-features.
* EBX - Maximum state size as per current XCR0|IA32_XSS value.
* ECX - Valid bits in IA32_XSS[31:0].
* EDX - Valid bits in IA32_XSS[63:32].
* if the bit invalid all four registers are set to zero.
* EAX - The state size for this feature.
* EBX - The state byte offset of this feature.
* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
* EDX - Reserved, but is set to zero if invalid sub-leaf index.
*
* Clear them all as we don't currently implement extended CPU state.
*/
uint64_t fGuestXcr0Mask = 0;
{
}
/* Work the sub-leaves. */
{
if (pCurLeaf)
{
if (fGuestXcr0Mask)
{
switch (uSubLeaf)
{
case 0:
continue;
case 1:
continue;
default:
{
continue;
}
break;
}
}
/* Clear the leaf. */
}
}
/* Cpuid 0xe: Marked as reserved by Intel and AMD.
* We zero this since we don't know what it may have been used for.
*/
/* Cpuid 0xf + ECX: Platform qualifity of service monitoring (PQM).
* We zero this as we don't currently virtualize PQM.
*/
/* Cpuid 0x10 + ECX: Platform qualifity of service enforcement (PQE).
* We zero this as we don't currently virtualize PQE.
*/
/* Cpuid 0x11: Marked as reserved by Intel and AMD.
* We zero this since we don't know what it may have been used for.
*/
/* Cpuid 0x12 + ECX: SGX resource enumeration.
* We zero this as we don't currently virtualize this.
*/
/* Cpuid 0x13: Marked as reserved by Intel and AMD.
* We zero this since we don't know what it may have been used for.
*/
/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
* We zero this as we don't currently virtualize this.
*/
/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
* EAX - denominator (unsigned).
* EBX - numerator (unsigned).
* ECX, EDX - reserved.
* AMD: Reserved / undefined / not implemented.
* VIA: Reserved / undefined / not implemented.
* We zero this as we don't currently virtualize this.
*/
/* Cpuid 0x16: Processor frequency info
* Intel: EAX - Core base frequency in MHz.
* EBX - Core maximum frequency in MHz.
* ECX - Bus (reference) frequency in MHz.
* EDX - Reserved.
* AMD: Reserved / undefined / not implemented.
* VIA: Reserved / undefined / not implemented.
* We zero this as we don't currently virtualize this.
*/
/* Cpuid 0x17..0x10000000: Unknown.
* We don't know these and what they mean, so remove them. */
/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
* We remove all these as we're a hypervisor and must provide our own.
*/
/* Cpuid 0x80000000 is harmless. */
/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
* Safe to pass on to the guest.
*
* AMD: 0x800000005 L1 cache information
* Intel: 0x800000005 reserved
* 0x800000006 L2 cache information
* VIA: 0x800000005 TLB and L1 cache information
* 0x800000006 L2 cache information
*/
/* Cpuid 0x800000007: Advanced Power Management Information.
* AMD: EAX: Processor feedback capabilities.
* EBX: RAS capabilites.
* ECX: Advanced power monitoring interface.
* EDX: Enhanced power management capabilities.
* Intel: EAX, EBX, ECX - reserved.
* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
* VIA: Reserved
* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
*/
uSubLeaf = 0;
{
{
//| X86_CPUID_AMD_ADVPOWER_EDX_TS
//| X86_CPUID_AMD_ADVPOWER_EDX_FID
//| X86_CPUID_AMD_ADVPOWER_EDX_VID
//| X86_CPUID_AMD_ADVPOWER_EDX_TTP
//| X86_CPUID_AMD_ADVPOWER_EDX_TM
//| X86_CPUID_AMD_ADVPOWER_EDX_STC
//| X86_CPUID_AMD_ADVPOWER_EDX_MC
//| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
#if 0 /*
* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
* Linux kernels blindly assume that the AMD performance counters work
* if this is set for 64 bits guests. (Can't really find a CPUID feature
* bit for them though.)
*/
/** @todo need to recheck this with new MSR emulation. */
#endif
//| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
//| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
//| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
//| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
| 0;
}
else
if (pConfig->fInvariantTsc)
uSubLeaf++;
}
/* Cpuid 0x80000008:
* AMD: EBX, EDX - reserved
* ECX: Number of cores + APICIdCoreIdSize
* EBX, ECX, EDX - reserved
* EBX, ECX, EDX - reserved
*
* We only expose the virtual+pysical address size to the guest atm.
* On AMD we set the core count, but not the apic id stuff as we're
* currently not doing the apic id assignments in a complatible manner.
*/
uSubLeaf = 0;
{
/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
#ifdef VBOX_WITH_MULTI_CORE
#endif
uSubLeaf++;
}
/* Cpuid 0x80000009: Reserved
* We zero this since we don't know what it may have been used for.
*/
/* Cpuid 0x8000000a: SVM Information
* AMD: EAX - SVM revision.
* EBX - Number of ASIDs.
* ECX - Reserved.
* EDX - SVM Feature identification.
* We clear all as we currently does not virtualize SVM.
*/
/* Cpuid 0x8000000b thru 0x80000018: Reserved
* We clear these as we don't know what purpose they might have. */
/* Cpuid 0x80000019: TLB configuration
* Seems to be harmless, pass them thru as is. */
/* Cpuid 0x8000001a: Peformance optimization identifiers.
* Strip anything we don't know what is or addresses feature we don't implement. */
uSubLeaf = 0;
{
//| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
;
uSubLeaf++;
}
/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
* Clear this as we don't currently virtualize this feature. */
/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
* Clear this as we don't currently virtualize this feature. */
/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
* We need to sanitize the cores per cache (EAX[25:14]).
*
* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
* and EDX[2] are reserved here, and EAX[14:25] is documented having a
* slightly different meaning.
*/
uSubLeaf = 0;
{
#ifdef VBOX_WITH_MULTI_CORE
#else
#endif
uSubLeaf++;
}
/* Cpuid 0x8000001e: Get APIC / unit / node information.
* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
* setup, we have one compute unit with all the cores in it. Single node.
*/
uSubLeaf = 0;
{
{
#ifdef VBOX_WITH_MULTI_CORE
#else
#endif
}
else
{
}
uSubLeaf++;
}
/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
* We don't know these and what they mean, so remove them. */
/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
* Just pass it thru for now. */
/* Cpuid 0x8fffffff: Mystery hammer time leaf!
* Just pass it thru for now. */
/* Cpuid 0xc0000000: Centaur stuff.
* Harmless, pass it thru. */
/* Cpuid 0xc0000001: Centaur features.
* VIA: EAX - Family, model, stepping.
* EDX - Centaur extended feature flags. Nothing interesting, except may
* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
* EBX, ECX - reserved.
* We keep EAX but strips the rest.
*/
uSubLeaf = 0;
{
pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
uSubLeaf++;
}
/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
* We only have fixed stale values, but should be harmless. */
/* Cpuid 0xc0000003: Reserved.
* We zero this since we don't know what it may have been used for.
*/
/* Cpuid 0xc0000004: Centaur Performance Info.
* We only have fixed stale values, but should be harmless. */
/* Cpuid 0xc0000005...0xcfffffff: Unknown.
* We don't know these and what they mean, so remove them. */
return VINF_SUCCESS;
}
/**
*
* @returns VBox status code (error message raised).
* @param pVM The VM handle (for errors).
* @param pszValueName The value / extension name.
* @param penmValue Where to return the choice.
* @param enmDefault The default choice.
*/
{
/*
* Try integer encoding first.
*/
if (RT_SUCCESS(rc))
switch (uValue)
{
case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
default:
"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
}
/*
* If missing, use default.
*/
*penmValue = enmDefault;
else
{
if (rc == VERR_CFGM_NOT_INTEGER)
{
/*
* Not an integer, try read it as a string.
*/
char szValue[32];
if (RT_SUCCESS(rc))
{
else if (EQ("portable"))
*penmValue = enmDefault;
else
"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
}
}
if (RT_FAILURE(rc))
return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
}
return VINF_SUCCESS;
}
/**
*
* @returns VBox status code (error message raised).
* @param pVM The VM handle (for errors).
* @param pszValueName The value / extension name.
* @param penmValue Where to return the choice.
* @param enmDefault The default choice.
* @param fAllowed Allowed choice. Applied both to the result and to
* the default value.
*/
{
int rc;
if (fAllowed)
else
{
}
return rc;
}
/**
*
* @returns VBox status code (error message raised).
* @param pVM The VM handle (for errors).
* @param pCpumCfg The /CPUM node (can be NULL).
* @param pszValueName The value / extension name.
* @param penmValue Where to return the choice.
* @param enmDefault The default choice.
*/
static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
{
{
LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
else
bool fLegacy;
int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
if (RT_SUCCESS(rc))
{
return VINF_SUCCESS;
}
return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
}
}
static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
{
int rc;
/** @cfgm{/CPUM/SyntheticCpu, boolean, false}
* Enables the Synthetic CPU. The Vendor ID and Processor Name are
* completely overridden by VirtualBox custom strings. Some
* CPUID information is withheld, like the cache info.
*
* This is obsoleted by PortableCpuIdLevel. */
/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
* When non-zero CPUID features that could cause portability issues will be
* stripped. The higher the value the more features gets stripped. Higher
* values should only be used when older CPUs are involved since it may
* harm performance and maybe also cause problems with specific guests. */
rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, pConfig->fSyntheticCpu ? 1 : 0);
/** @cfgm{/CPUM/GuestCpuName, string}
* The name of the CPU we're to emulate. The default is the host CPU.
* Note! CPUs other than "host" one is currently unsupported. */
rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
*/
/** @cfgm{/CPUM/InvariantTsc, boolean, complicated}
* Set the invariant TSC flag in 0x80000007 if true, otherwas take default
* action. By default the flag is passed thru as is from the host CPU, except
* on AMD CPUs where it's suppressed to avoid trouble from linux assuming we
* virtualize performance counters.
*/
/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
* Restrict the reported CPU family+model+stepping of intel CPUs. This is
* probably going to be a temporary hack, so don't depend on this.
* The 1st byte of the value is the stepping, the 2nd byte value is the model
* number and the 3rd byte value is the family, and the 4th value must be zero.
*/
rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
* The last standard leaf to keep. The actual last value that is stored in EAX
* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
* removed. (This works independently of and differently from NT4LeafLimit.)
* The default is usually set to what we're able to reasonably sanitize.
*/
/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
* The last extended leaf to keep. The actual last value that is stored in EAX
* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
* leaf are removed. The default is set to what we're able to sanitize.
*/
/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
* The last extended leaf to keep. The actual last value that is stored in EAX
* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
* leaf are removed. The default is set to what we're able to sanitize.
*/
rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
/*
* Instruction Set Architecture (ISA) Extensions.
*/
if (pIsaExts)
{
"CMPXCHG16B"
"|MONITOR"
"|MWaitExtensions"
"|SSE4.1"
"|SSE4.2"
"|AESNI"
"|PCLMUL"
"|POPCNT"
"|MOVBE"
"|RDRAND"
"|RDSEED"
"|CLFLUSHOPT"
, "" /*pszValidNodes*/, "CPUM" /*pszWho*/, 0 /*uInstance*/);
if (RT_FAILURE(rc))
return rc;
}
/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
* Expose CMPXCHG16B to the guest if supported by the host. For the time
* being the default is to only do this for VMs with nested paging and AMD-V or
* unrestricted guest mode.
*/
rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
*/
rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
* Expose MWAIT extended features to the guest. For now we expose just MWAIT
* break on interrupt feature (bit 1).
*/
rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
* Expose SSE4.1 to the guest if available.
*/
* Expose SSE4.2 to the guest if available.
*/
bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
* default is to only expose this to VMs with nested paging and AMD-V or
* unrestricted guest execution mode. Not possible to force this one without
* host support at the moment.
*/
rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
fMayHaveXSave /*fAllowed*/);
* Expose the AVX instruction set extensions to the guest if available and
* XSAVE is exposed too. For the time being the default is to only expose this
* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
*/
rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
* Expose the AVX2 instruction set extensions to the guest if available and
* XSAVE is exposed too. For the time being the default is to only expose this
* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
*/
rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec,
* Whether to expose the AES instructions to the guest. For the time being the
* default is to only do this for VMs with nested paging and AMD-V or
* unrestricted guest mode.
*/
rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
* Whether to expose the PCLMULQDQ instructions to the guest. For the time
* being the default is to only do this for VMs with nested paging and AMD-V or
* unrestricted guest mode.
*/
rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
* Whether to expose the POPCNT instructions to the guest. For the time
* being the default is to only do this for VMs with nested paging and AMD-V or
* unrestricted guest mode.
*/
rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
* Whether to expose the MOVBE instructions to the guest. For the time
* being the default is to only do this for VMs with nested paging and AMD-V or
* unrestricted guest mode.
*/
rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
* Whether to expose the RDRAND instructions to the guest. For the time being
* the default is to only do this for VMs with nested paging and AMD-V or
* unrestricted guest mode.
*/
rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
* Whether to expose the RDSEED instructions to the guest. For the time being
* the default is to only do this for VMs with nested paging and AMD-V or
* unrestricted guest mode.
*/
rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
* being the default is to only do this for VMs with nested paging and AMD-V or
* unrestricted guest mode.
*/
rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
/* AMD: */
* Whether to expose the AMD ABM instructions to the guest. For the time
* being the default is to only do this for VMs with nested paging and AMD-V or
* unrestricted guest mode.
*/
rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
* Whether to expose the AMD SSE4A instructions to the guest. For the time
* being the default is to only do this for VMs with nested paging and AMD-V or
* unrestricted guest mode.
*/
rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
* the time being the default is to only do this for VMs with nested paging and
* AMD-V or unrestricted guest mode.
*/
rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
* For the time being the default is to only do this for VMs with nested paging
* and AMD-V or unrestricted guest mode.
*/
rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
* Whether to expose the AMD's MMX Extensions to the guest. For the time being
* the default is to only do this for VMs with nested paging and AMD-V or
* unrestricted guest mode.
*/
rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
return VINF_SUCCESS;
}
/**
* Initializes the emulated CPU's CPUID & MSR information.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
/*
* Read the configuration.
*/
int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
/*
*
* The CPUID and MSRs are currently living on the regular heap to avoid
* API for the hyper heap). This means special cleanup considerations.
*/
if (RT_FAILURE(rc))
return rc == VERR_CPUM_DB_CPU_NOT_FOUND
: rc;
* Overrides the guest MSRs.
*/
* Overrides the CPUID leaf values (from the host CPU usually) used for
* calculating the guest CPUID leaves. This can be used to preserve the CPUID
* values when moving a VM to a different machine. Another use is restricting
* (or extending) the feature set exposed to the guest. */
if (RT_SUCCESS(rc))
"Please use IMachine::setCPUIDLeaf() instead.");
/*
* Pre-explode the CPUID info.
*/
if (RT_SUCCESS(rc))
rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
/*
* Sanitize the cpuid information passed on to the guest.
*/
if (RT_SUCCESS(rc))
{
if (RT_SUCCESS(rc))
{
}
}
/*
* Plant our own hypervisor CPUID leaves.
*/
if (RT_SUCCESS(rc))
/*
* MSR fudging.
*/
if (RT_SUCCESS(rc))
{
* Fudges some common MSRs if not present in the selected CPU database entry.
* This is for trying to keep VMs running when moved between different hosts
* and different CPU vendors. */
bool fEnable;
{
}
}
if (RT_SUCCESS(rc))
{
/*
* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
* guest CPU features again.
*/
/*
* Some more configuration that we're applying at the end of everything
* via the CPUMSetGuestCpuIdFeature API.
*/
/* Check if PAE was explicitely enabled by the user. */
bool fEnable;
if (fEnable)
/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
if (fEnable)
/* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
if (fEnable)
return VINF_SUCCESS;
}
/*
* Failed before switching to hyper heap.
*/
return rc;
}
/*
*
*
* Saved state related code.
* Saved state related code.
* Saved state related code.
*
*
*/
/**
* Called both in pass 0 and the final pass.
*
* @param pVM Pointer to the VM.
* @param pSSM The saved state handle.
*/
{
/*
* Save all the CPU ID leaves.
*/
/*
* Save a good portion of the raw CPU IDs as well as they may come in
* handy when validating features for raw mode.
*/
for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
}
static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
{
if (RT_SUCCESS(rc))
{
if (cCpuIds < 64)
{
{
if (RT_FAILURE(rc))
break;
NewLeaf.fSubLeafMask = 0;
}
}
else
}
if (RT_FAILURE(rc))
{
*pcLeaves = 0;
}
return rc;
}
static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
{
*pcLeaves = 0;
int rc;
{
/*
* The new format. Starts by declaring the leave size and count.
*/
if (RT_SUCCESS(rc))
{
{
if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
{
/*
* Load the leaves one by one.
*
* The uPrev stuff is a kludge for working around a week worth of bad saved
* states during the CPUID revamp in March 2015. We saved too many leaves
* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
* garbage entires at the end of the array when restoring. We also had
* a subleaf insertion bug that triggered with the leaf 4 stuff below,
* this kludge doesn't deal correctly with that, but who cares...
*/
{
if (RT_SUCCESS(rc))
{
{
}
else
uPrev = UINT32_MAX;
}
}
}
else
}
else
}
}
else
{
/*
* The old format with its three inflexible arrays.
*/
if (RT_SUCCESS(rc))
if (RT_SUCCESS(rc))
if (RT_SUCCESS(rc))
{
/*
* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
*/
if ( pLeaf
{
if (RT_SUCCESS(rc))
{
}
if (RT_SUCCESS(rc))
{
}
}
}
}
return rc;
}
/**
* Loads the CPU ID leaves saved by pass 0, inner worker.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pSSM The saved state handle.
* @param uVersion The format version.
* @param paLeaves Guest CPUID leaves loaded from the state.
* @param cLeaves The number of leaves in @a paLeaves.
*/
int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
{
AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
/*
* Continue loading the state into stack buffers.
*/
ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
/*
* Get the raw CPU IDs for the current host.
*/
for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
/*
* Get the host and guest overrides so we don't reject the state because
* some feature was enabled thru these interfaces.
* Note! We currently only need the feature leaves, so skip rest.
*/
cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
/*
* This can be skipped.
*/
bool fStrictCpuIdChecks;
CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
/*
*/
/* Generic expression + failure message. */
do { \
if (!(expr)) \
{ \
if (fStrictCpuIdChecks) \
{ \
return rcCpuid; \
} \
} \
} while (0)
do { \
if (!(expr)) \
} while (0)
/* For comparing two values and bitch if they differs. */
do { \
{ \
if (fStrictCpuIdChecks) \
} \
} while (0)
do { \
} while (0)
/* For checking raw cpu features (raw mode). */
do { \
{ \
if (fStrictCpuIdChecks) \
} \
} while (0)
do { \
} while (0)
/* For checking guest features. */
do { \
) \
{ \
if (fStrictCpuIdChecks) \
} \
} while (0)
do { \
) \
} while (0)
do { \
) \
LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
} while (0)
/* For checking guest features if AMD guest CPU. */
do { \
&& fGuestAmd \
) \
{ \
if (fStrictCpuIdChecks) \
} \
} while (0)
do { \
&& fGuestAmd \
) \
} while (0)
do { \
&& fGuestAmd \
) \
LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
} while (0)
/* For checking AMD features which have a corresponding bit in the standard
range. (Intel defines very few bits in the extended feature sets.) */
do { \
&& !(fHostAmd \
) \
{ \
if (fStrictCpuIdChecks) \
LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
} \
} while (0)
do { \
&& !(fHostAmd \
) \
LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
} while (0)
do { \
&& !(fHostAmd \
) \
LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
} while (0)
/*
* For raw-mode we'll require that the CPUs are very similar since we don't
* intercept CPUID instructions for user mode applications.
*/
if (!HMIsEnabled(pVM))
{
/* CPUID(0) */
(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
/* CPUID(1).eax */
CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
/* CPUID(1).ecx */
/* CPUID(1).edx */
/* CPUID(2) - config, mostly about caches. ignore. */
/* CPUID(3) - processor serial number. ignore. */
/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
/* CPUID(6) - power management. ignore. */
/* CPUID(7) - ???. ignore. */
/* CPUID(8) - ???. ignore. */
/* CPUID(9) - DCA. ignore for now. */
/* CPUID(a) - PeMo info. ignore for now. */
/* CPUID(b) - topology info - takes ECX as input. ignore. */
/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
{
/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
}
/* CPUID(0x80000000) - same as CPUID(0) except for eax.
will verify them as if it's an AMD CPU. */
CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
{
(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
/* CPUID(0x80000001).ecx */
/* CPUID(0x80000001).edx */
/** @todo verify the rest as well. */
}
}
/*
* Verify that we can support the features already exposed to the guest on
* this host.
*
* Most of the features we're emulating requires intercepting instruction
* and doing it the slow way, so there is no need to warn when they aren't
* present in the host CPU. Thus we use IGN instead of EMU on these.
*
* Trailing comments:
* "EMU" - Possible to emulate, could be lots of work and very slow.
* "EMU?" - Can this be emulated?
*/
/* CPUID(1).ecx */
/* CPUID(1).edx */
/* CPUID(0x80000000). */
{
/** @todo deal with no 0x80000001 on the host. */
bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
/* CPUID(0x80000001).ecx */
/* CPUID(0x80000001).edx */
CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
}
/** @todo check leaf 7 */
/* CPUID(d) - XCR0 stuff - takes ECX as input.
* ECX=0: EAX - Valid bits in XCR0[31:0].
* EBX - Maximum state size as per current XCR0 value.
* ECX - Maximum state size for all supported features.
* EDX - Valid bits in XCR0[63:32].
* ECX=1: EAX - Various X-features.
* EBX - Maximum state size as per current XCR0|IA32_XSS value.
* ECX - Valid bits in IA32_XSS[31:0].
* EDX - Valid bits in IA32_XSS[63:32].
* if the bit invalid all four registers are set to zero.
* EAX - The state size for this feature.
* EBX - The state byte offset of this feature.
* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
* EDX - Reserved, but is set to zero if invalid sub-leaf index.
*/
if ( pCurLeaf
{
N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
/* We don't support any additional features yet. */
N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
{
}
{
if (pCurLeaf)
{
/* If advertised, the state component offset and size must match the one used by host. */
{
}
}
}
}
/*
* We're good, commit the CPU ID leaves.
*/
return VINF_SUCCESS;
}
/**
* Loads the CPU ID leaves saved by pass 0.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pSSM The saved state handle.
* @param uVersion The format version.
*/
{
AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
/*
* Load the CPUID leaves array first and call worker to do the rest, just so
* we can free the memory when we need to without ending up in column 1000.
*/
if (RT_SUCCESS(rc))
{
}
return rc;
}
/*
*
*
* CPUID Info Handler.
* CPUID Info Handler.
* CPUID Info Handler.
*
*
*/
/**
* Get L1 cache / TLS associativity.
*/
static const char *getCacheAss(unsigned u, char *pszBuf)
{
if (u == 0)
return "res0 ";
if (u == 1)
return "direct";
if (u == 255)
return "fully";
if (u >= 256)
return "???";
return pszBuf;
}
/**
* Get L2 cache associativity.
*/
const char *getL2CacheAss(unsigned u)
{
switch (u)
{
case 0: return "off ";
case 1: return "direct";
case 2: return "2 way ";
case 3: return "res3 ";
case 4: return "4 way ";
case 5: return "res5 ";
case 6: return "8 way ";
case 7: return "res7 ";
case 8: return "16 way";
case 9: return "res9 ";
case 10: return "res10 ";
case 11: return "res11 ";
case 12: return "res12 ";
case 13: return "res13 ";
case 14: return "res14 ";
case 15: return "fully ";
default: return "????";
}
}
/** CPUID(1).EDX field descriptions. */
static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
{
};
/** CPUID(1).ECX field descriptions. */
static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
{
};
/** CPUID(7,0).EBX field descriptions. */
static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
{
};
/** CPUID(7,0).ECX field descriptions. */
static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
{
};
/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
{
};
/** CPUID(13,1).EAX field descriptions. */
static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
{
};
/** CPUID(0x80000001,0).EDX field descriptions. */
static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
{
};
/** CPUID(0x80000001,0).ECX field descriptions. */
static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
{
};
static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
{
if (pszLeadIn)
{
pDesc++;
{
else
{
}
}
else
}
if (pszLeadIn)
}
static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
{
if (pszLeadIn)
{
pDesc++;
{
else
{
}
}
else
}
if (pszLeadIn)
}
static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
{
if (!uVal)
else
{
}
}
static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
{
{
pDesc++;
{
{
}
pDesc++;
}
else
}
}
/**
* Produces a detailed summary of standard leaf 0x00000001.
*
* @param pHlp The info helper functions.
* @param paLeaves The CPUID leaves array.
* @param cLeaves The number of leaves in the array.
* @param pCurLeaf The 0x00000001 leaf.
* @param fVerbose Whether to be very verbose or not.
* @param fIntel Set if intel CPU.
*/
static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
{
"%36s %2d \tExtended: %d \tEffective: %d\n"
"%36s %2d \tExtended: %d \tEffective: %d\n"
"%36s %d\n"
"%36s %d (%s)\n"
"%36s %#04x\n"
"%36s %d\n"
"%36s %d\n"
"%36s %#04x\n"
,
if (fVerbose)
{
}
else
{
}
}
/**
* Produces a detailed summary of standard leaf 0x00000007.
*
* @param pHlp The info helper functions.
* @param paLeaves The CPUID leaves array.
* @param cLeaves The number of leaves in the array.
* @param pCurLeaf The first 0x00000007 leaf.
* @param fVerbose Whether to be very verbose or not.
*/
static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
{
for (;;)
{
ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
{
case 0:
if (fVerbose)
{
cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
}
else
{
cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
}
break;
default:
break;
}
/* advance. */
pCurLeaf++;
break;
}
}
/**
* Produces a detailed summary of standard leaf 0x0000000d.
*
* @param pHlp The info helper functions.
* @param paLeaves The CPUID leaves array.
* @param cLeaves The number of leaves in the array.
* @param pCurLeaf The first 0x00000007 leaf.
* @param fVerbose Whether to be very verbose or not.
*/
static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
{
{
ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
switch (uSubLeaf)
{
case 0:
pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
"Valid XCR0 bits, guest:", 42);
"Valid XCR0 bits, host:", 42);
break;
case 1:
cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
" Valid IA32_XSS bits, guest:", 42);
" Valid IA32_XSS bits, host:", 42);
break;
default:
if ( pCurLeaf
{
}
{
}
break;
}
/* advance. */
if (pCurLeaf)
{
pCurLeaf++;
}
}
}
static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
{
{
" %s\n"
{
ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
"Gst: %08x/%04x %08x %08x %08x %08x\n"
"Hst: %08x %08x %08x %08x\n",
pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
pCurLeaf++;
}
}
return pCurLeaf;
}
/**
* Display the guest CpuId leaves.
*
* @param pVM Pointer to the VM.
* @param pHlp The info helper functions.
* @param pszArgs "terse", "default" or "verbose".
*/
{
/*
* Parse the argument.
*/
unsigned iVerbosity = 1;
if (pszArgs)
{
iVerbosity--;
iVerbosity++;
}
/*
* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
*/
" Raw Standard CPUID Leaves\n"
{
cMaxSubLeaves = 16;
else if (uLeaf == 0xd)
cMaxSubLeaves = 128;
{
{
"Gst: %08x/%04x %08x %08x %08x %08x\n"
"Hst: %08x %08x %08x %08x\n",
pCurLeaf++;
}
else if ( uLeaf != 0xd
|| uSubLeaf <= 1
"Hst: %08x/%04x %08x %08x %08x %08x\n",
/* Done? */
)
)
break;
}
}
/*
* If verbose, decode it.
*/
"%36s %.04s%.04s%.04s\n"
"%36s 0x00000000-%#010x\n"
,
if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
/*
* Hypervisor leaves.
*
* Unlike most of the other leaves reported, the guest hypervisor leaves
* aren't a subset of the host CPUID bits.
*/
pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
{
pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
/** @todo dump these in more detail. */
}
/*
* Extended. Custom raw dump here due to ECX sub-leaves host handling.
* Implemented after AMD specs.
*/
pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
{
" Raw Extended CPUID Leaves\n"
{
cMaxSubLeaves = 16;
{
{
"Gst: %08x/%04x %08x %08x %08x %08x\n"
"Hst: %08x %08x %08x %08x\n",
pCurLeaf++;
}
else if ( uLeaf != 0xd
|| uSubLeaf <= 1
"Hst: %08x/%04x %08x %08x %08x %08x\n",
/* Done? */
break;
}
}
/*
* Understandable output
*/
if (iVerbosity)
"Ext Name: %.4s%.4s%.4s\n"
"Ext Supports: 0x80000000-%#010x\n",
if (iVerbosity && pCurLeaf)
{
"Family: %d \tExtended: %d \tEffective: %d\n"
"Model: %d \tExtended: %d \tEffective: %d\n"
"Stepping: %d\n"
"Brand ID: %#05x\n",
if (iVerbosity == 1)
{
cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
}
else
{
}
}
if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
{
if (pCurLeaf)
{
}
if (pCurLeaf)
{
}
}
if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
{
char sz1[32];
char sz2[32];
"TLB 2/4M Data: %s %3d entries\n",
"TLB 4K Data: %s %3d entries\n",
"L1 Instr Cache Lines Per Tag: %d\n"
"L1 Instr Cache Associativity: %s\n"
"L1 Instr Cache Size: %d KB\n",
(uEDX >> 0) & 0xff,
"L1 Data Cache Line Size: %d bytes\n"
"L1 Data Cache Lines Per Tag: %d\n"
"L1 Data Cache Associativity: %s\n"
"L1 Data Cache Size: %d KB\n",
(uECX >> 0) & 0xff,
}
if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
{
"L2 TLB 2/4M Data: %s %4d entries\n",
"L2 TLB 4K Data: %s %4d entries\n",
"L2 Cache Line Size: %d bytes\n"
"L2 Cache Lines Per Tag: %d\n"
"L2 Cache Associativity: %s\n"
"L2 Cache Size: %d KB\n",
(uEDX >> 0) & 0xff,
}
if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
{
}
if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0)) != NULL)
{
"Physical Address Width: %d bits\n"
"Virtual Address Width: %d bits\n"
"Guest Physical Address Width: %d bits\n",
(uEAX >> 0) & 0xff,
"Physical Core Count: %d\n",
(uECX >> 0) & 0xff);
}
}
/*
* Centaur.
*/
pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
{
pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
/*
* Understandable output
*/
if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
"Centaur Supports: 0xc0000000-%#010x\n",
if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
{
if (iVerbosity == 1)
{
}
else
{
pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
}
}
}
/*
* The remainder.
*/
pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
}
/*
*
*
* PATM interfaces.
* PATM interfaces.
* PATM interfaces.
*
*
*/
# if defined(VBOX_WITH_RAW_MODE) || defined(DOXYGEN_RUNNING)
/** @name Patchmanager CPUID legacy table APIs
* @{
*/
/**
* Gets a pointer to the default CPUID leaf.
*
* @returns Raw-mode pointer to the default CPUID leaf (read-only).
* @param pVM Pointer to the VM.
* @remark Intended for PATM only.
*/
{
}
/**
* Gets a number of standard CPUID leaves (PATM only).
*
* @returns Number of leaves.
* @param pVM Pointer to the VM.
* @remark Intended for PATM - legacy, don't use in new code.
*/
{
}
/**
* Gets a number of extended CPUID leaves (PATM only).
*
* @returns Number of leaves.
* @param pVM Pointer to the VM.
* @remark Intended for PATM - legacy, don't use in new code.
*/
{
}
/**
* Gets a number of centaur CPUID leaves.
*
* @returns Number of leaves.
* @param pVM Pointer to the VM.
* @remark Intended for PATM - legacy, don't use in new code.
*/
{
}
/**
* Gets a pointer to the array of standard CPUID leaves.
*
* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
*
* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
* @param pVM Pointer to the VM.
* @remark Intended for PATM - legacy, don't use in new code.
*/
{
}
/**
* Gets a pointer to the array of extended CPUID leaves.
*
* CPUMGetGuestCpuIdExtMax() give the size of the array.
*
* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
* @param pVM Pointer to the VM.
* @remark Intended for PATM - legacy, don't use in new code.
*/
{
}
/**
* Gets a pointer to the array of centaur CPUID leaves.
*
* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
*
* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
* @param pVM Pointer to the VM.
* @remark Intended for PATM - legacy, don't use in new code.
*/
{
}
/** @} */
# endif /* VBOX_WITH_RAW_MODE || DOXYGEN_RUNNING */
#endif /* VBOX_IN_VMM */