HWVMXR0.cpp revision a63dfea04c51d4be12ffd06c25945571459e34d1
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * HWACCM VMX - Host Context Ring 0.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * available from http://www.virtualbox.org. This file is free software;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * you can redistribute it and/or modify it under the terms of the GNU
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * General Public License (GPL) as published by the Free Software
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * additional information or have any questions.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/*******************************************************************************
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync* Header Files *
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync*******************************************************************************/
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/*******************************************************************************
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync* Defined Constants And Macros *
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync*******************************************************************************/
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync# define VMX_IS_64BIT_HOST_MODE() (true)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync# define VMX_IS_64BIT_HOST_MODE() (false)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/*******************************************************************************
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync* Global Variables *
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync*******************************************************************************/
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/* IO operation lookup arrays. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** See HWACCMR0A.asm. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/*******************************************************************************
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync* Local Functions *
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync*******************************************************************************/
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
968c867cc19737e4e1fd97c396fcf75a3d52dd27vboxsyncstatic void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
968c867cc19737e4e1fd97c396fcf75a3d52dd27vboxsyncstatic void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
968c867cc19737e4e1fd97c396fcf75a3d52dd27vboxsyncstatic void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic bool vmxR0IsValidReadField(uint32_t idxField);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic bool vmxR0IsValidWriteField(uint32_t idxField);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Sets up and activates VT-x on the current CPU
b84a3f2aac9529d5c5840512b12d81bc62d0e665vboxsync * @returns VBox status code.
968c867cc19737e4e1fd97c396fcf75a3d52dd27vboxsync * @param pCpu CPU info struct
968c867cc19737e4e1fd97c396fcf75a3d52dd27vboxsync * @param pVM The VM to operate on. (can be NULL after a resume!!)
b84a3f2aac9529d5c5840512b12d81bc62d0e665vboxsync * @param pvPageCpu Pointer to the global cpu page
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pPageCpuPhys Physical address of the global cpu page
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Set revision dword at the beginning of the VMXON structure. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * (which can have very bad consequences!!!)
968c867cc19737e4e1fd97c396fcf75a3d52dd27vboxsync /* Make sure the VMX instructions don't cause #UD faults. */
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync /* Enter VMX Root Mode */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deactivates VT-x on the current CPU
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCpu CPU info struct
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pvPageCpu Pointer to the global cpu page
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pPageCpuPhys Physical address of the global cpu page
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Leave VMX Root Mode. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* And clear the X86_CR4_VMXE bit */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Does Ring-0 per VM VT-x init.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Allocate one page for the APIC physical page (serves for filtering accesses). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Allocate the MSR bitmap if this feature is supported. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Allocate VMCBs for all guest CPUs. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Allocate one page for the VM control structure (VMCS). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Allocate one page for the virtual APIC page for TPR caching. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.pVAPIC = (uint8_t *)RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVAPIC);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.pVAPICPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMMemZero32(pVCpu->hwaccm.s.vmx.pVAPIC, PAGE_SIZE);
968c867cc19737e4e1fd97c396fcf75a3d52dd27vboxsync /* Current guest paging mode. */
b84a3f2aac9529d5c5840512b12d81bc62d0e665vboxsync pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Does Ring-0 per VM VT-x termination.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVCpu->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVMCS, false);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVCpu->hwaccm.s.vmx.pMemObjVAPIC != NIL_RTR0MEMOBJ)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, false);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
b84a3f2aac9529d5c5840512b12d81bc62d0e665vboxsync if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
b84a3f2aac9529d5c5840512b12d81bc62d0e665vboxsync pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
968c867cc19737e4e1fd97c396fcf75a3d52dd27vboxsync ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
968c867cc19737e4e1fd97c396fcf75a3d52dd27vboxsync * Sets up VT-x for the specified VM
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
b84a3f2aac9529d5c5840512b12d81bc62d0e665vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Set revision dword at the beginning of the VMCS structure. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Clear VM Control Structure. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Activate the VM Control Structure. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Set required bits to one and zero according to the MSR capabilities.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* External and non-maskable interrupts cause VM-exits. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Set required bits to one and zero according to the MSR capabilities.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Program which event cause VM-exits and which features we want to use. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* We will use the secondary control if it's present. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Mask away the bits that the CPU doesn't support */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo make sure they don't conflict with the above requirements. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Set required bits to one and zero according to the MSR capabilities.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* HWACCM_VTX_WITH_EPT */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* HWACCM_VTX_WITH_VPID */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Mask away the bits that the CPU doesn't support */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo make sure they don't conflict with the above requirements. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Set required bits to one and zero according to the MSR capabilities.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Forward all exception except #NM & #PF to the guest.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * We always need to check pagefaults since our shadow page table can be out of sync.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * And we always lazily sync the FPU & XMM state.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo Possible optimization:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Keep the FPU and XMM state current in the EM thread. That way there's no need to
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * registers ourselves of course.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Don't filter page faults; all of them should cause a switch. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Init TSC offset to zero. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Set the MSR bitmap address. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Optional */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Clear MSR controls. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Optional */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hwaccm.s.vmx.pVAPICPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Set link pointer to -1. Not currently used. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Configure the VMCS read cache. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Status code VMCS reads. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync } /* for each VMCPU */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Choose the right TLB setup function. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Default values for flushing. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* If the capabilities specify we can do more, then make use of it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Default values for flushing. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* If the capabilities specify we can do more, then make use of it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* HWACCM_VTX_WITH_VPID */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Injects an event (trap or external interrupt)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx CPU Context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param intInfo VMX interrupt info
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param cbInstr Opcode length of faulting instruction
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param errCode Error code (optional)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[iGate & MASK_INJECT_IRQ_STAT]);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || pCtx->eflags.u32 & X86_EFL_IF);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Injecting events doesn't work right with real mode emulation.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * (#GP if we try to inject external hardware interrupts)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Inject the interrupt or trap directly instead.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * ASSUMES no access handlers for the bits we read or write below (should be safe).
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Check if the interrupt handler is present. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || iGate == 3 /* Both #BP and #OF point to the instruction after. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Read the selector:offset pair of the interrupt handler. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler, sizeof(offset)); AssertRC(rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = PGMPhysSimpleReadGCPhys(pVM, &sel, GCPhysHandler + 2, sizeof(sel)); AssertRC(rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Construct the stack frame. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo should check stack limit. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Update the CPU state for executing the handler. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* HWACCM_VMX_EMULATE_REALMODE */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Set event injection state. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Checks for pending guest interrupts and injects them
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx CPU Context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* If an active trap is already pending, then we must forward it first! */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI_BIT))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* @todo SMI interrupts. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* When external interrupts are pending, we should exit the VM when IF is set. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* else nothing to do but wait */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Just continue */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* If a new event is pending, then dispatch it now. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &errCode, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Clear the pending trap. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Valid error codes. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync } /* if (interrupts can be dispatched) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Save the host state
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Host CPU Context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Control registers */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Selector registers. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* GDTR & IDTR */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Save the base address of the TR selector. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* FS and GS base. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Sysenter MSRs. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo expensive!! */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#if 0 /* @todo deal with 32/64 */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Restore the host EFER - on CPUs that support it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Prefetch the 4 PDPT pointers (PAE and nested paging only)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Guest context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync for (unsigned i=0;i<4;i++)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Update the exception bitmap according to the current CPU state
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Guest context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1167f682bad8a5c086022e181da3bb4028a20ff8vboxsync u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1167f682bad8a5c086022e181da3bb4028a20ff8vboxsync /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#ifdef DEBUG /* till after branching, enable it by default then. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Intercept X86_XCPT_DB if stepping is enabled */
968c867cc19737e4e1fd97c396fcf75a3d52dd27vboxsync /** @todo Don't trap it unless the debugger has armed breakpoints. */
1167f682bad8a5c086022e181da3bb4028a20ff8vboxsync /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1167f682bad8a5c086022e181da3bb4028a20ff8vboxsync if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1167f682bad8a5c086022e181da3bb4028a20ff8vboxsync# endif /* HWACCM_VMX_EMULATE_REALMODE */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Loads the guest state
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Guest context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* VMX_VMCS_CTRL_ENTRY_CONTROLS
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Set required bits to one and zero according to the MSR capabilities.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#if 0 /* @todo deal with 32/64 */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Required for the EFER write below, not supported on all CPUs. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* 64 bits guest mode? */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* else Must be zero when AMD64 is not available. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Mask away the bits that the CPU doesn't support */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* VMX_VMCS_CTRL_EXIT_CONTROLS
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Set required bits to one and zero according to the MSR capabilities.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#if 0 /* @todo deal with 32/64 */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* else: Must be zero when AMD64 is not available. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Don't acknowledge external interrupts on VM-exit. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Correct weird requirements for switching to protected mode. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Flush the recompiler code cache as it's not unlikely
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * the guest will rewrite code it will later execute in real
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * mode (OpenBSD 4.0 is one such example)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* DPL of all hidden selector registers must match the current CPL (0). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* The limit must correspond to the granularity bit. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Switching from protected mode to real mode. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* The limit must also be set to 0xffff. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* HWACCM_VMX_EMULATE_REALMODE */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Guest CPU context: LDTR. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Guest CPU context: TR. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* We convert it here every time as pci regions could be reconfigured. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* HWACCM_VMX_EMULATE_REALMODE */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* The TSS selector must be busy. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Guest CPU context: GDTR. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Guest CPU context: IDTR. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Sysenter MSRs (unconditional)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Control registers */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Always use #NM exceptions to load the FPU/XMM state on demand. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo check if we support the old style mess correctly. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Disable cr3 read/write monitoring as we don't need it for EPT. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Always enable caching. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* CR0 flags owned by the host; if the guests attempts to change them, then
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * the VM will exit.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync | X86_CR0_ET /* Bit not restored during VM-exit! */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync | X86_CR0_CD /* Bit not restored during VM-exit! */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync | X86_CR0_NW /* Bit not restored during VM-exit! */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo use normal 32 bits paging */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync default: /* shut up gcc */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Our identity mapping is a 32 bits page directory. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* CR4 flags owned by the host; if the guests attempts to change them, then
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * the VM will exit.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* We convert it here every time as pci regions could be reconfigured. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * take care of the translation to host physical addresses.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Prefetch the four PDPT entries in PAE mode. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(val || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Save our shadow CR3 register. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Debug registers. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Resync DR7 */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Sync the debug state now if any breakpoint is armed. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Disable drx move intercepts. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Save the host and load the guest debug state. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* IA32_DEBUGCTL MSR. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo do we really ever need this? */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* EIP, ESP and EFLAGS */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Real mode emulation using v86 mode. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* HWACCM_VMX_EMULATE_REALMODE */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* TSC offset. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* 64 bits guest mode? */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Unconditionally update these as wrmsr might have changed them. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#if 0 /* @todo deal with 32/64 */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Unconditionally update the guest EFER - on CPUs that supports it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Done. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Syncs back the guest state
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Guest context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncDECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Let's first sync back eip, esp, and eflags. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Take care of instruction fusing (sti, mov ss) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(uInterruptState <= 2); /* only sti & mov ss */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("uInterruptState %x eip=%RGv\n", (uint32_t)uInterruptState, pCtx->rip));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Control registers. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Can be updated behind our back in the nested paging case. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Prefetch the four PDPT entries in PAE mode. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Sync back DR7 here. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * System MSRs
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Real mode emulation using v86 mode. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Hide our emulation flags */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Restore original IOPL setting as we always use 0. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Force a TR resync every time in case we switch modes. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* HWACCM_VMX_EMULATE_REALMODE */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Dummy placeholder
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Setup the tagged TLB for EPT
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Deal with tagged TLBs if VPID or EPT is supported. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Force a TLB flush on VM entry. */
11923fc977be1686f5428c3e790c04d0701a074cvboxsync /* Check for tlb shootdown flushes. */
11923fc977be1686f5428c3e790c04d0701a074cvboxsync if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
11923fc977be1686f5428c3e790c04d0701a074cvboxsync for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
11923fc977be1686f5428c3e790c04d0701a074cvboxsync /* aTlbShootdownPages contains physical addresses in this case. */
11923fc977be1686f5428c3e790c04d0701a074cvboxsync vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync * Setup the tagged TLB for VPID
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync * @returns VBox status code.
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync * @param pVM The VM to operate on.
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync * @param pVCpu The VMCPU to operate on.
11923fc977be1686f5428c3e790c04d0701a074cvboxsyncstatic void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync /* Deal with tagged TLBs if VPID or EPT is supported. */
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync /* Force a TLB flush on VM entry. */
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync /* Check for tlb shootdown flushes. */
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* HWACCM_VTX_WITH_VPID */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Runs guest code in a VT-x VM.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Guest context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync unsigned cResume = 0;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) || (pVCpu->hwaccm.s.vmx.pVAPIC && pVM->hwaccm.s.vmx.pAPIC));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Check if we need to use TPR shadowing. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* allowed zero */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* allowed one */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Must be set according to the MSR, but can be cleared in case of EPT. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* allowed zero */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* allowed one */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* allowed zero */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* allowed one */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* allowed zero */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* allowed one */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync (int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Safety precaution; looping for too long here can have a very bad effect on the host */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Irq inhibition is no longer active; clear the corresponding VMX state. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Irq inhibition is no longer active; clear the corresponding VMX state. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Check for pending actions that force us to go back to ring 3. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Intercept X86_XCPT_DB if stepping is enabled */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Exit to ring-3 preemption/work is pending.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Interrupts are disabled before the call to make sure we don't miss any interrupt
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * further down, but VMXR0CheckPendingInterrupt makes that impossible.)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * shootdowns rely on this.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* When external interrupts are pending, we should exit the VM when IF is set. */
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo check timers?? */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* TPR caching using CR8 is only available in 64 bits mode */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @todo query and update the TPR only when it could have been changed (mmio access & wrmsr (x2apic))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* TPR caching in CR8 */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* The TPR can be found at offset 0x80 in the APIC mmio page. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Two options here:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * - external interrupt pending, but masked by the TPR value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * -> a CR8 update that lower the current TPR value should cause an exit
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * - no pending interrupts
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? (u8LastTPR >> 4) : 0); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync# endif /* HWACCM_VTX_WITH_VPID */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * (until the actual world switch)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Save the host state first. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Load the guest state */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Disable interrupts to make sure a poke will interrupt execution.
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Deal with tagged TLB setup and invalidation. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Non-register state Guest Context */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo change me according to cpu state */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Manual save and restore:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * - General purpose registers except RIP, RSP
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * - CR2 (we don't care)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * - LDTR (reset to 0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * - DRx (presumably not changed at all)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * - DR7 (reset to 0x400)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * - EFLAGS (reset to RT_BIT(1); not relevant)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* All done! Let's start VM execution. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* In case we execute a goto ResumeExecution later on. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Success. Query the guest state and figure out what has happened. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Investigate why there was a VM-exit. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Sync back the guest state */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note! NOW IT'S SAFE FOR LOGGING! */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Check if an injected event was interrupted prematurely. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Ignore 'int xx' as they'll be restarted anyway. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Ignore software exceptions (such as int3) as they'll reoccur when we restart the instruction anyway. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Error code present? */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("E%d: New EIP=%RGv\n", exitReason, (RTGCPTR)pCtx->rip));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("Interruption error code %d\n", (uint32_t)errCode));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Sync back the TPR if it was changed. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = PDMApicSetTPR(pVCpu, pVCpu->hwaccm.s.vmx.pVAPIC[0x80]);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* External interrupt; leave to allow it to be dispatched again. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* External interrupt; leave to allow it to be dispatched again. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertFailed(); /* can't come here; fails the first check. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* no break */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("Hardware/software interrupt %d\n", vector));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Continue execution. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync { /* A genuine pagefault.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Forward the trap to the guest by injecting the exception and resuming execution.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Now we must update CR2. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Exit qualification contains the linear address of the page fault. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Shortcut for APIC TPR reads and writes. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = PGMGstGetPage(pVCpu, (RTGCPTR)exitQualification, NULL, &GCPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Enable VT-x virtual APIC access filtering\n"));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync { /* We've successfully synced our shadow pages, so let's just continue execution. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync { /* A genuine pagefault.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Forward the trap to the guest by injecting the exception and resuming execution.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* The error code might have been changed. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Now we must update CR2. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Need to go back to the recompiler to emulate the instruction. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* old style FPU error reporting needs some extra work. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo don't fall back to the recompiler, but do it manually. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Exit qualification bits:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * 3:0 B0-B3 which breakpoint condition was met
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * 12:4 Reserved (0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * 13 BD - debug register access detected
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * 14 BS - single step execution or branch taken
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * 63:15 Reserved (0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note that we don't support guest and host-initiated debugging at the same time. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(DBGFIsStepping(pVCpu) || CPUMIsGuestInRealModeEx(pCtx));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), uDR6);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo this isn't working, but we'll never get here normally. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Update DR6 here. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Paranoia. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Resync DR7 */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Return to ring 3 to deal with the debug exit code. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case X86_XCPT_GP: /* General protection failure exception.*/
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (eflags.u & X86_EFL_POPF_BITS & uMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* RF cleared when popped in real mode; see pushf description in AMD manual. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (pDis->prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("iret to %04x:%x\n", pCtx->cs, pCtx->ip));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("Realmode: INT %x\n", pDis->param1.parval & 0xff));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, &cbSize);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCtx->rip += cbOp; /* Move on to the next instruction. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Only resume if successful. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case X86_XCPT_NP: /* Segment not present exception. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
a95fedb133944ec689b02e94077b0387bda0262bvboxsync Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
a95fedb133944ec689b02e94077b0387bda0262bvboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
a95fedb133944ec689b02e94077b0387bda0262bvboxsync /* Go back to ring 3 in case of a triple fault. */
a95fedb133944ec689b02e94077b0387bda0262bvboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
a95fedb133944ec689b02e94077b0387bda0262bvboxsync AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
a95fedb133944ec689b02e94077b0387bda0262bvboxsync } /* switch (vector) */
021a33be84282e41b811563b5f60f3ada196af3evboxsync AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
021a33be84282e41b811563b5f60f3ada196af3evboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
021a33be84282e41b811563b5f60f3ada196af3evboxsync case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Determine the kind of violation. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* If the page is present, then it's a page level protection fault. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Shortcut for APIC TPR reads and writes. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && GCPhys > 0x1000000 /* to skip VGA frame buffer accesses */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Enable VT-x virtual APIC access filtering\n"));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* GCPhys contains the guest physical address of the page fault. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Handle the pagefault trap for the nested shadow table. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync { /* We've successfully synced our shadow pages, so let's just continue execution. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Need to go back to the recompiler to emulate the instruction. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Clear VM-exit on IF=1 change. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync goto ResumeExecution; /* we check for pending guest interrupts there */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Skip instruction and continue directly. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Continue execution.*/
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Update EIP and continue execution. */
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Update EIP and continue execution. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Update EIP and continue execution. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), exitQualification);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Update EIP and continue execution. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC((exitReason == VMX_EXIT_RDMSR) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* EIP has been updated already. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Only resume if successful. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* CR8 contains the APIC TPR */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Check if a sync operation is pending. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Update EIP if no error occurred. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Only resume if successful. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Disable drx move intercepts. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Save the host and load the guest debug state. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Update EIP if no error occurred. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Only resume if successful. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo necessary to make the distinction? */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* paranoia */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Disassemble manually to deal with segment prefixes. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* normal in/out */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Write back to the EAX register. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Handled the I/O return codes.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Update EIP and continue execution. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync for (unsigned i=0;i<4;i++)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Clear all breakpoint status flags and set the one we just hit. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: AMD64 Architecture Programmer's Manual 13.1:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * the contents have been read.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Paranoia. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Resync DR7 */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Construct inject info. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync unsigned uAccessType = VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(exitQualification);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(exitQualification);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = IOMMMIOPhysHandler(pVM, (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW, CPUMCTX2CORE(pCtx), GCPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* The rest is handled after syncing the entire CPU state. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: the guest state isn't entirely synced back at this stage. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Investigate why there was a VM-exit. (part 2) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Already handled above. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VINF_EM_RESET; /* Triple fault equals a reset. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** Check if external interrupts are pending; if so, don't switch back. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Update EIP and continue execution. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** Check if external interrupts are pending; if so, don't switch back. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo inject #UD immediately */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* already handled above */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* VBOX_STRICT */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Signal changes for the recompiler. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* On the next entry we'll only sync the host context. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* On the next entry we'll sync everything. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo we can do better than this */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Not in the VINF_PGM_CHANGE_MODE though! */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* translate into a less severe return code */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Try to extract more information about what might have gone wrong here. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Just set the correct state here instead of trying to catch every goto above. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Restore interrupts if we exitted after disabling them. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Enters the VT-x session
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCpu CPU info struct
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Activate the VM Control Structure. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Leaves the VT-x session
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx CPU context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Save the guest debug state if necessary. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Enable drx move intercepts again. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Resync the debug registers the next time. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Flush the TLB (EPT)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VM CPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param enmFlush Type of flush
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param GCPhys Physical address of the page to flush
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Flush the TLB (EPT)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync * @param pVCpu The VM CPU to operate on.
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync * @param enmFlush Type of flush
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync * @param GCPtr Virtual address of the page to flush
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsyncstatic void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* HWACCM_VTX_WITH_VPID */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Invalidates a guest page
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VM CPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param GCVirt Page to invalidate
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Only relevant if we want to use VPID.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * In the nested paging case we still see such calls, but
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * can safely ignore them. (e.g. after cr3 updates)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Skip it if a TLB flush is already pending. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* HWACCM_VTX_WITH_VPID */
968c867cc19737e4e1fd97c396fcf75a3d52dd27vboxsync * Invalidates a guest page by physical address
968c867cc19737e4e1fd97c396fcf75a3d52dd27vboxsync * NOTE: Assumes the current instruction references this physical page though a virtual address!!
021a33be84282e41b811563b5f60f3ada196af3evboxsync * @returns VBox status code.
021a33be84282e41b811563b5f60f3ada196af3evboxsync * @param pVM The VM to operate on.
021a33be84282e41b811563b5f60f3ada196af3evboxsync * @param pVCpu The VM CPU to operate on.
021a33be84282e41b811563b5f60f3ada196af3evboxsync * @param GCPhys Page to invalidate
021a33be84282e41b811563b5f60f3ada196af3evboxsyncVMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Skip it if a TLB flush is already pending. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Report world switch error and dump some useful debug info
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param rc Return code
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Current CPU context (not updated)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* VBOX_STRICT */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* impossible */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Prepares for and executes VMLAUNCH (64 bits guest mode)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param fResume vmlauch/vmresume
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Guest context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCache VMCS cache
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM to operate on.
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncDECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
a96f8709d113c056da40edb8e2591983226a9761vboxsync aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
a96f8709d113c056da40edb8e2591983226a9761vboxsync * Executes the specified handler in 64 mode
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync * @returns VBox status code.
a96f8709d113c056da40edb8e2591983226a9761vboxsync * @param pVM The VM to operate on.
a96f8709d113c056da40edb8e2591983226a9761vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Guest context
cea26cf0a0d390c2cca75cb19cb0e86c580e9d77vboxsync * @param pfnHandler RC handler
a96f8709d113c056da40edb8e2591983226a9761vboxsync * @param cbParam Number of parameters
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param paParam Array of 32 bits parameters
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2afbe132eb7931e0125141eabe3a48e08f1ffab5vboxsync /* @todo This code is not guest SMP safe (hyper stack and switchers) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
fb9af443dbf06990f4956d683286ddce29c4dca6vboxsync pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Leave VMX Root Mode. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Call switcher. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Make sure the VMX instructions don't cause #UD faults. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Enter VMX Root Mode */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Executes VMWRITE
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param idxField VMCS index
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param u64Val 16, 32 or 64 bits value
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* These fields consist of two parts, which are both writable in 32 bits mode. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsgFailed(("Unexpected field %x\n", idxField));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVCpu The VMCPU to operate on.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param idxField VMCS field
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param u64Val Value
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Make sure there are no duplicates. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic bool vmxR0IsValidReadField(uint32_t idxField)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return true;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic bool vmxR0IsValidWriteField(uint32_t idxField)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return true;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;