HWVMXR0.cpp revision 5e89c2baed2e85b3f68c0e556d0859172ff769ad
/* $Id$ */
/** @file
* HWACCM VMX - Host Context Ring 0.
*/
/*
* Copyright (C) 2006-2007 Sun Microsystems, Inc.
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
* Clara, CA 95054 USA or visit http://www.sun.com if you need
* additional information or have any questions.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_HWACCM
#include "HWACCMInternal.h"
#include "HWVMXR0.h"
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
#if defined(RT_ARCH_AMD64)
# define VMX_IS_64BIT_HOST_MODE() (true)
#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
#else
# define VMX_IS_64BIT_HOST_MODE() (false)
#endif
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/* IO operation lookup arrays. */
/** See HWACCMR0A.asm. */
#endif
/*******************************************************************************
* Local Functions *
*******************************************************************************/
#ifdef VBOX_STRICT
#endif
{
if (rc == VERR_VMX_GENERIC)
{
}
}
/**
* Sets up and activates VT-x on the current CPU
*
* @returns VBox status code.
* @param pCpu CPU info struct
* @param pVM The VM to operate on. (can be NULL after a resume!!)
* @param pvPageCpu Pointer to the global cpu page
* @param pPageCpuPhys Physical address of the global cpu page
*/
VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
{
#ifdef LOG_ENABLED
SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
#endif
if (pVM)
{
/* Set revision dword at the beginning of the VMXON structure. */
}
/** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
* (which can have very bad consequences!!!)
*/
/* Make sure the VMX instructions don't cause #UD faults. */
/* Enter VMX Root Mode */
if (RT_FAILURE(rc))
{
if (pVM)
return VERR_VMX_VMXON_FAILED;
}
return VINF_SUCCESS;
}
/**
* Deactivates VT-x on the current CPU
*
* @returns VBox status code.
* @param pCpu CPU info struct
* @param pvPageCpu Pointer to the global cpu page
* @param pPageCpuPhys Physical address of the global cpu page
*/
{
/* Leave VMX Root Mode. */
VMXDisable();
/* And clear the X86_CR4_VMXE bit */
#ifdef LOG_ENABLED
#endif
return VINF_SUCCESS;
}
/**
* Does Ring-0 per VM VT-x init.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
int rc;
#ifdef LOG_ENABLED
#endif
if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
{
/* Allocate one page for the virtual APIC mmio cache. */
rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
if (RT_FAILURE(rc))
return rc;
}
else
{
}
/* Allocate the MSR bitmap if this feature is supported. */
if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
{
rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
if (RT_FAILURE(rc))
return rc;
pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
}
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
{
rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
if (RT_FAILURE(rc))
return rc;
}
#endif
/* Allocate VMCBs for all guest CPUs. */
{
/* Allocate one page for the VM control structure (VMCS). */
rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
if (RT_FAILURE(rc))
return rc;
/* Current guest paging mode. */
#ifdef LOG_ENABLED
SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
#endif
}
return VINF_SUCCESS;
}
/**
* Does Ring-0 per VM VT-x termination.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
{
{
}
}
{
}
{
}
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
{
}
#endif
return VINF_SUCCESS;
}
/**
* Sets up VT-x for the specified VM
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
int rc = VINF_SUCCESS;
{
/* Set revision dword at the beginning of the VMCS structure. */
*(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
/* Clear VM Control Structure. */
if (RT_FAILURE(rc))
goto vmx_end;
/* Activate the VM Control Structure. */
if (RT_FAILURE(rc))
goto vmx_end;
/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
* Set required bits to one and zero according to the MSR capabilities.
*/
/* External and non-maskable interrupts cause VM-exits. */
val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
* Set required bits to one and zero according to the MSR capabilities.
*/
/* Program which event cause VM-exits and which features we want to use. */
| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
/* Without nested paging we should intercept invlpg and cr3 mov instructions. */
/* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
{
/* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
}
else
/* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
#ifdef VBOX_WITH_VTX_MSR_BITMAPS
if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
{
}
#endif
/* We will use the secondary control if it's present. */
/* Mask away the bits that the CPU doesn't support */
/** @todo make sure they don't conflict with the above requirements. */
if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
{
/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
* Set required bits to one and zero according to the MSR capabilities.
*/
#ifdef HWACCM_VTX_WITH_EPT
#endif /* HWACCM_VTX_WITH_EPT */
#ifdef HWACCM_VTX_WITH_VPID
else
#endif /* HWACCM_VTX_WITH_VPID */
/* Mask away the bits that the CPU doesn't support */
/** @todo make sure they don't conflict with the above requirements. */
}
/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
* Set required bits to one and zero according to the MSR capabilities.
*/
/* Forward all exception except #NM & #PF to the guest.
* We always need to check pagefaults since our shadow page table can be out of sync.
* And we always lazily sync the FPU & XMM state.
*/
/** @todo Possible optimization:
* Keep the FPU and XMM state current in the EM thread. That way there's no need to
* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
* registers ourselves of course.
*
* Note: only possible if the current state is actually ours (X86_CR0_TS flag)
*/
/* Don't filter page faults; all of them should cause a switch. */
/* Init TSC offset to zero. */
/* Set the MSR bitmap address. */
if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
{
/* Optional */
}
/* Clear MSR controls. */
if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
{
/* Optional */
}
/* Set link pointer to -1. Not currently used. */
/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
/* Configure the VMCS read cache. */
/* Status code VMCS reads. */
{
}
else
} /* for each VMCPU */
/* Choose the right TLB setup function. */
{
/* Default values for flushing. */
/* If the capabilities specify we can do more, then make use of it. */
else
}
#ifdef HWACCM_VTX_WITH_VPID
else
{
/* Default values for flushing. */
/* If the capabilities specify we can do more, then make use of it. */
else
}
#endif /* HWACCM_VTX_WITH_VPID */
else
return rc;
}
/**
* Injects an event (trap or external interrupt)
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
* @param pCtx CPU Context
* @param intInfo VMX interrupt info
* @param cbInstr Opcode length of faulting instruction
* @param errCode Error code (optional)
*/
static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
{
int rc;
#ifdef VBOX_STRICT
if (iGate == 0xE)
LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
else
if (iGate < 0x20)
LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
else
{
Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || pCtx->eflags.u32 & X86_EFL_IF);
}
#endif
#ifdef HWACCM_VMX_EMULATE_REALMODE
if (CPUMIsGuestInRealModeEx(pCtx))
{
/* Injecting events doesn't work right with real mode emulation.
* (#GP if we try to inject external hardware interrupts)
* Inject the interrupt or trap directly instead.
*
* ASSUMES no access handlers for the bits we read or write below (should be safe).
*/
/* Check if the interrupt handler is present. */
{
Log(("IDT cbIdt violation\n"));
if (iGate != X86_XCPT_DF)
{
return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
}
Log(("Triple fault -> reset the VM!\n"));
return VINF_EM_RESET;
}
|| iGate == 4)
{
}
else
/* Read the selector:offset pair of the interrupt handler. */
/* Construct the stack frame. */
/** @todo should check stack limit. */
rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
/* Update the CPU state for executing the handler. */
return VINF_SUCCESS;
}
#endif /* HWACCM_VMX_EMULATE_REALMODE */
/* Set event injection state. */
rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
return rc;
}
/**
* Checks for pending guest interrupts and injects them
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
* @param pCtx CPU Context
*/
{
int rc;
/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
{
Log(("Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
/* When external interrupts are pending, we should exit the VM when IF is set. */
if ( !TRPMHasTrap(pVM)
{
{
{
LogFlow(("Enable irq window exit!\n"));
}
/* else nothing to do but wait */
}
else
{
Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
if (RT_SUCCESS(rc))
{
}
else
{
/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
/* Just continue */
}
}
else
}
#ifdef VBOX_STRICT
if (TRPMHasTrap(pVM))
{
}
#endif
&& TRPMHasTrap(pVM)
)
{
int rc;
/* If a new event is pending, then dispatch it now. */
/* Clear the pending trap. */
{
switch (u8Vector) {
case 8:
case 10:
case 11:
case 12:
case 13:
case 14:
case 17:
/* Valid error codes. */
break;
default:
break;
}
else
}
else
} /* if (interrupts can be dispatched) */
return VINF_SUCCESS;
}
/**
* Save the host state
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
*/
{
int rc = VINF_SUCCESS;
/*
* Host CPU Context
*/
{
/* Control registers */
if (VMX_IS_64BIT_HOST_MODE())
{
cr3 = hwaccmR0Get64bitCR3();
}
else
#endif
{
}
/* Selector registers. */
if (VMX_IS_64BIT_HOST_MODE())
{
}
else
{
/* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
}
#else
#endif
/* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
#if HC_ARCH_BITS == 32
if (!VMX_IS_64BIT_HOST_MODE())
{
}
#endif
/* GDTR & IDTR */
if (VMX_IS_64BIT_HOST_MODE())
{
}
else
#endif
{
ASMGetGDTR(&gdtr);
ASMGetIDTR(&idtr);
}
/* Save the base address of the TR selector. */
{
return VERR_VMX_INVALID_HOST_STATE;
}
if (VMX_IS_64BIT_HOST_MODE())
{
}
else
#endif
{
#if HC_ARCH_BITS == 64
#else
#endif
}
/* FS and GS base. */
if (VMX_IS_64BIT_HOST_MODE())
{
}
#endif
/* Sysenter MSRs. */
/** @todo expensive!! */
if (VMX_IS_64BIT_HOST_MODE())
{
}
else
{
}
#else
#endif
#if 0 /* @todo deal with 32/64 */
/* Restore the host EFER - on CPUs that support it. */
{
}
#endif
}
return rc;
}
/**
* Prefetch the 4 PDPT pointers (PAE and nested paging only)
*
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
* @param pCtx Guest context
*/
{
if (CPUMIsGuestInPAEModeEx(pCtx))
{
for (unsigned i=0;i<4;i++)
{
}
}
}
/**
* Update the exception bitmap according to the current CPU state
*
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
* @param pCtx Guest context
*/
{
#ifndef DEBUG
#endif
/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
if ( CPUMIsGuestFPUStateActive(pVCpu) == true
{
}
#ifdef DEBUG /* till after branching, enable it by default then. */
/* Intercept X86_XCPT_DB if stepping is enabled */
if (DBGFIsStepping(pVM))
/** @todo Don't trap it unless the debugger has armed breakpoints. */
#endif
#ifdef VBOX_STRICT
#endif
# ifdef HWACCM_VMX_EMULATE_REALMODE
/* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
# endif /* HWACCM_VMX_EMULATE_REALMODE */
}
/**
* Loads the guest state
*
* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
* @param pCtx Guest context
*/
{
int rc = VINF_SUCCESS;
/* VMX_VMCS_CTRL_ENTRY_CONTROLS
* Set required bits to one and zero according to the MSR capabilities.
*/
/* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
#if 0 /* @todo deal with 32/64 */
/* Required for the EFER write below, not supported on all CPUs. */
#endif
/* 64 bits guest mode? */
/* else Must be zero when AMD64 is not available. */
/* Mask away the bits that the CPU doesn't support */
/* VMX_VMCS_CTRL_EXIT_CONTROLS
* Set required bits to one and zero according to the MSR capabilities.
*/
/* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
#if 0 /* @todo deal with 32/64 */
#else
#endif
if (VMX_IS_64BIT_HOST_MODE())
/* else: Must be zero when AMD64 is not available. */
else
#endif
/* Don't acknowledge external interrupts on VM-exit. */
/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
{
#ifdef HWACCM_VMX_EMULATE_REALMODE
{
{
/* Correct weird requirements for switching to protected mode. */
&& enmGuestMode >= PGMMODE_PROTECTED)
{
/* Flush the recompiler code cache as it's not unlikely
* the guest will rewrite code it will later execute in real
* mode (OpenBSD 4.0 is one such example)
*/
/* DPL of all hidden selector registers must match the current CPL (0). */
/* The limit must correspond to the granularity bit. */
}
else
/* Switching from protected mode to real mode. */
&& enmGuestMode == PGMMODE_REAL)
{
/* The limit must also be set to 0xffff. */
}
}
else
/* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
if ( CPUMIsGuestInRealModeEx(pCtx)
{
}
}
#endif /* HWACCM_VMX_EMULATE_REALMODE */
/* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
}
/* Guest CPU context: LDTR. */
{
{
/* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
}
else
{
}
}
/* Guest CPU context: TR. */
{
#ifdef HWACCM_VMX_EMULATE_REALMODE
/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
if (CPUMIsGuestInRealModeEx(pCtx))
{
/* We convert it here every time as pci regions could be reconfigured. */
attr.u = 0;
}
else
#endif /* HWACCM_VMX_EMULATE_REALMODE */
{
/* The TSS selector must be busy. */
else
/* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
}
}
/* Guest CPU context: GDTR. */
{
}
/* Guest CPU context: IDTR. */
{
}
/*
* Sysenter MSRs (unconditional)
*/
/* Control registers */
{
if (CPUMIsGuestFPUStateActive(pVCpu) == false)
{
}
else
{
/** @todo check if we support the old style mess correctly. */
if (!(val & X86_CR0_NE))
Log(("Forcing X86_CR0_NE!!!\n"));
val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
}
/* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
{
{
}
else
{
}
}
else
{
/* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
val |= X86_CR0_WP;
}
/* Always enable caching. */
/* CR0 flags owned by the host; if the guests attempts to change them, then
* the VM will exit.
*/
| X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
| X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
| X86_CR0_ET /* Bit not restored during VM-exit! */
| X86_CR0_CD /* Bit not restored during VM-exit! */
| X86_CR0_NW /* Bit not restored during VM-exit! */
| X86_CR0_MP;
}
{
/* CR4 */
/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
{
{
case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
case PGMMODE_32_BIT: /* 32-bit paging. */
val &= ~X86_CR4_PAE;
break;
case PGMMODE_PAE: /* PAE paging. */
case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
/** @todo use normal 32 bits paging */
val |= X86_CR4_PAE;
break;
case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
#ifdef VBOX_ENABLE_64_BITS_GUESTS
break;
#else
AssertFailed();
#endif
default: /* shut up gcc */
AssertFailed();
}
}
else
{
/* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
val |= X86_CR4_PSE;
/* Our identity mapping is a 32 bits page directory. */
val &= ~X86_CR4_PAE;
}
/* CR4 flags owned by the host; if the guests attempts to change them, then
* the VM will exit.
*/
val = 0
| X86_CR4_VMXE;
}
{
{
/** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
{
/* We convert it here every time as pci regions could be reconfigured. */
/* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
* take care of the translation to host physical addresses.
*/
}
else
{
/* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
/* Prefetch the four PDPT entries in PAE mode. */
}
}
else
{
}
/* Save our shadow CR3 register. */
}
/* Debug registers. */
{
/* Resync DR7 */
/* Sync the debug state now if any breakpoint is armed. */
&& !DBGFIsStepping(pVM))
{
/* Disable drx move intercepts. */
/* Save the host and load the guest debug state. */
}
/* IA32_DEBUGCTL MSR. */
/** @todo do we really ever need this? */
}
/* EIP, ESP and EFLAGS */
/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
#ifdef HWACCM_VMX_EMULATE_REALMODE
/* Real mode emulation using v86 mode. */
if (CPUMIsGuestInRealModeEx(pCtx))
{
}
#endif /* HWACCM_VMX_EMULATE_REALMODE */
/* TSC offset. */
{
/* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
}
else
{
}
/* 64 bits guest mode? */
{
#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
#else
# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
# endif
#endif
/* Unconditionally update these as wrmsr might have changed them. */
}
else
{
}
#if 0 /* @todo deal with 32/64 */
/* Unconditionally update the guest EFER - on CPUs that supports it. */
{
}
#endif
/* Done. */
return rc;
}
/**
* Syncs back the guest state
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
* @param pCtx Guest context
*/
{
int rc;
/* Let's first sync back eip, esp, and eflags. */
/* Take care of instruction fusing (sti, mov ss) */
if (uInterruptState != 0)
{
}
else
/* Control registers. */
/* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
{
/* Can be updated behind our back in the nested paging case. */
{
}
/* Prefetch the four PDPT entries in PAE mode. */
}
/* Sync back DR7 here. */
/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
/*
* System MSRs
*/
/* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
#ifdef HWACCM_VMX_EMULATE_REALMODE
/* Real mode emulation using v86 mode. */
if (CPUMIsGuestInRealModeEx(pCtx))
{
/* Hide our emulation flags */
/* Restore original IOPL setting as we always use 0. */
/* Force a TR resync every time in case we switch modes. */
}
else
#endif /* HWACCM_VMX_EMULATE_REALMODE */
{
/* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
}
return VINF_SUCCESS;
}
/**
* Dummy placeholder
*
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
*/
{
return;
}
/**
* Setup the tagged TLB for EPT
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
*/
{
/* Deal with tagged TLBs if VPID or EPT is supported. */
/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
{
/* Force a TLB flush on VM entry. */
}
else
#ifdef VBOX_WITH_STATISTICS
else
#endif
}
#ifdef HWACCM_VTX_WITH_VPID
/**
* Setup the tagged TLB for VPID
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
*/
{
/* Deal with tagged TLBs if VPID or EPT is supported. */
/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
{
/* Force a TLB flush on VM entry. */
}
else
/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
{
{
pCpu->cTLBFlushes++;
}
else
{
}
}
else
{
}
AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
#ifdef VBOX_WITH_STATISTICS
else
#endif
}
#endif /* HWACCM_VTX_WITH_VPID */
/**
* Runs guest code in a VT-x VM.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
* @param pCtx Guest context
*/
{
int rc = VINF_SUCCESS;
bool fSyncTPR = false;
PHWACCM_CPUINFO pCpu = 0;
unsigned cResume = 0;
#ifdef VBOX_STRICT
#endif
#ifdef VBOX_WITH_STATISTICS
bool fStatEntryStarted = true;
bool fStatExit2Started = false;
#endif
Log2(("\nE"));
#ifdef VBOX_STRICT
{
/* allowed zero */
if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
/* allowed one */
Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
/* Must be set according to the MSR, but can be cleared in case of EPT. */
/* allowed zero */
if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
/* allowed one */
Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
/* allowed zero */
if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
/* allowed one */
Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
/* allowed zero */
if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
/* allowed one */
Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
}
#endif
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
#endif
/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
*/
if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
});
("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
/* Safety precaution; looping for too long here can have a very bad effect on the host */
if (++cResume > HWACCM_MAX_RESUME_LOOPS)
{
goto end;
}
/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
{
Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVM, pVCpu)));
{
/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
* break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
*/
/* Irq inhibition is no longer active; clear the corresponding VMX state. */
}
}
else
{
/* Irq inhibition is no longer active; clear the corresponding VMX state. */
}
/* Check for pending actions that force us to go back to ring 3. */
{
rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
goto end;
}
/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
{
goto end;
}
/* When external interrupts are pending, we should exit the VM when IF is set. */
/* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
if (RT_FAILURE(rc))
goto end;
/** @todo check timers?? */
/* TPR caching using CR8 is only available in 64 bits mode */
/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
/**
* @todo reduce overhead
*/
{
/* TPR caching in CR8 */
bool fPending;
/* The TPR can be found at offset 0x80 in the APIC mmio page. */
/* Two options here:
* - external interrupt pending, but masked by the TPR value.
* -> a CR8 update that lower the current TPR value should cause an exit
* - no pending interrupts
* -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
*/
/* Always sync back the TPR; we should optimize this though */ /** @todo optimize TPR sync. */
fSyncTPR = true;
}
#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
# ifdef HWACCM_VTX_WITH_VPID
# endif /* HWACCM_VTX_WITH_VPID */
)
{
{
Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
else
Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
}
else
LogFlow(("Manual TLB flush\n"));
}
#endif
#endif
/*
* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
* (until the actual world switch)
*/
#ifdef VBOX_STRICT
idCpuCheck = RTMpCpuId();
#endif
#ifdef LOG_LOGGING
#endif
/* Save the host state first. */
if (rc != VINF_SUCCESS)
goto end;
/* Load the guest state */
if (rc != VINF_SUCCESS)
goto end;
/* Deal with tagged TLB setup and invalidation. */
/* Non-register state Guest Context */
/** @todo change me according to cpu state */
/* Manual save and restore:
* - General purpose registers except RIP, RSP
*
* Trashed:
* - CR2 (we don't care)
* - LDTR (reset to 0)
* - DRx (presumably not changed at all)
* - DR7 (reset to 0x400)
* - EFLAGS (reset to RT_BIT(1); not relevant)
*
*/
/* All done! Let's start VM execution. */
#ifdef VBOX_STRICT
#endif
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
#endif
rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
/* In case we execute a goto ResumeExecution later on. */
/*
* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
*/
if (rc != VINF_SUCCESS)
{
goto end;
}
/* Success. Query the guest state and figure out what has happened. */
/* Investigate why there was a VM-exit. */
/* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
/* Sync back the guest state */
/* Note! NOW IT'S SAFE FOR LOGGING! */
#ifdef LOG_LOGGING
#endif
/* Check if an injected event was interrupted prematurely. */
/* Ignore 'int xx' as they'll be restarted anyway. */
&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
/* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
{
/* Error code present? */
{
Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
}
else
{
Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
}
}
#ifdef VBOX_STRICT
else
/* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
{
Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
}
#endif
Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
if (fSyncTPR)
{
}
/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
switch (exitReason)
{
case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
{
{
/* External interrupt; leave to allow it to be dispatched again. */
break;
}
switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
{
case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
/* External interrupt; leave to allow it to be dispatched again. */
break;
case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
AssertFailed(); /* can't come here; fails the first check. */
break;
case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
/* no break */
case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
switch (vector)
{
case X86_XCPT_NM:
{
/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
if (rc == VINF_SUCCESS)
{
/* Continue execution. */
goto ResumeExecution;
}
Log(("Forward #NM fault to the guest\n"));
rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
goto ResumeExecution;
}
case X86_XCPT_PF: /* Page fault */
{
#ifdef DEBUG
{ /* A genuine pagefault.
* Forward the trap to the guest by injecting the exception and resuming execution.
*/
Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
/* Now we must update CR2. */
rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
goto ResumeExecution;
}
#endif
/* Exit qualification contains the linear address of the page fault. */
/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
if (rc == VINF_SUCCESS)
{ /* We've successfully synced our shadow pages, so let's just continue execution. */
Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
goto ResumeExecution;
}
else
if (rc == VINF_EM_RAW_GUEST_TRAP)
{ /* A genuine pagefault.
* Forward the trap to the guest by injecting the exception and resuming execution.
*/
Log2(("Forward page fault to the guest\n"));
/* The error code might have been changed. */
/* Now we must update CR2. */
rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
goto ResumeExecution;
}
#ifdef VBOX_STRICT
#endif
/* Need to go back to the recompiler to emulate the instruction. */
break;
}
case X86_XCPT_MF: /* Floating point exception. */
{
{
/* old style FPU error reporting needs some extra work. */
/** @todo don't fall back to the recompiler, but do it manually. */
break;
}
rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
goto ResumeExecution;
}
case X86_XCPT_DB: /* Debug exception. */
{
/* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
*
* Exit qualification bits:
* 3:0 B0-B3 which breakpoint condition was met
* 12:4 Reserved (0)
* 13 BD - debug register access detected
* 14 BS - single step execution or branch taken
* 63:15 Reserved (0)
*/
/* Note that we don't support guest and host-initiated debugging at the same time. */
if (rc == VINF_EM_RAW_GUEST_TRAP)
{
/** @todo this isn't working, but we'll never get here normally. */
/* Update DR6 here. */
/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
/* Paranoia. */
/* Resync DR7 */
Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
goto ResumeExecution;
}
/* Return to ring 3 to deal with the debug exit code. */
break;
}
#ifdef DEBUG /* till after branching, enable by default after that. */
case X86_XCPT_BP: /* Breakpoint. */
{
if (rc == VINF_EM_RAW_GUEST_TRAP)
{
rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
goto ResumeExecution;
}
if (rc == VINF_SUCCESS)
goto ResumeExecution;
break;
}
#endif
case X86_XCPT_GP: /* General protection failure exception.*/
{
#ifdef VBOX_STRICT
if (!CPUMIsGuestInRealModeEx(pCtx))
{
rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
goto ResumeExecution;
}
#endif
if (RT_SUCCESS(rc))
{
bool fUpdateRIP = true;
{
case OP_CLI:
break;
case OP_STI:
break;
case OP_HLT:
fUpdateRIP = false;
rc = VINF_EM_HALT;
break;
case OP_POPF:
{
{
cbParm = 4;
uMask = 0xffffffff;
}
else
{
cbParm = 2;
uMask = 0xffff;
}
if (RT_FAILURE(rc))
{
break;
}
eflags.u = 0;
if (RT_FAILURE(rc))
{
break;
}
pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (eflags.u & X86_EFL_POPF_BITS & uMask);
/* RF cleared when popped in real mode; see pushf description in AMD manual. */
break;
}
case OP_PUSHF:
{
{
cbParm = 4;
uMask = 0xffffffff;
}
else
{
cbParm = 2;
uMask = 0xffff;
}
rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);
if (RT_FAILURE(rc))
{
break;
}
/* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */
if (RT_FAILURE(rc))
{
break;
}
break;
}
case OP_IRET:
{
{
break;
}
if (RT_FAILURE(rc))
{
break;
}
if (RT_FAILURE(rc))
{
break;
}
pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
fUpdateRIP = false;
break;
}
case OP_INT:
{
fUpdateRIP = false;
break;
}
case OP_INTO:
{
{
LogFlow(("Realmode: INTO\n"));
fUpdateRIP = false;
}
break;
}
case OP_INT3:
{
LogFlow(("Realmode: INT 3\n"));
intInfo = 3;
fUpdateRIP = false;
break;
}
default:
break;
}
if (rc == VINF_SUCCESS)
{
if (fUpdateRIP)
/* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
/* Only resume if successful. */
goto ResumeExecution;
}
}
else
AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
break;
}
#ifdef VBOX_STRICT
case X86_XCPT_DE: /* Divide error. */
case X86_XCPT_UD: /* Unknown opcode exception. */
case X86_XCPT_SS: /* Stack segment exception. */
case X86_XCPT_NP: /* Segment not present exception. */
{
switch(vector)
{
case X86_XCPT_DE:
break;
case X86_XCPT_UD:
break;
case X86_XCPT_SS:
break;
case X86_XCPT_NP:
break;
}
rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
goto ResumeExecution;
}
#endif
default:
#ifdef HWACCM_VMX_EMULATE_REALMODE
if (CPUMIsGuestInRealModeEx(pCtx))
{
rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
/* Go back to ring 3 in case of a triple fault. */
if ( vector == X86_XCPT_DF
&& rc == VINF_EM_RESET)
break;
goto ResumeExecution;
}
#endif
break;
} /* switch (vector) */
break;
default:
break;
}
break;
}
case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
{
/* Determine the kind of violation. */
errCode = 0;
/* If the page is present, then it's a page level protection fault. */
errCode |= X86_TRAP_PF_P;
/* GCPhys contains the guest physical address of the page fault. */
/* Handle the pagefault trap for the nested shadow table. */
if (rc == VINF_SUCCESS)
{ /* We've successfully synced our shadow pages, so let's just continue execution. */
Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
goto ResumeExecution;
}
#ifdef VBOX_STRICT
if (rc != VINF_EM_RAW_EMULATE_INSTR)
#endif
/* Need to go back to the recompiler to emulate the instruction. */
break;
}
case VMX_EXIT_EPT_MISCONFIG:
{
break;
}
case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
/* Clear VM-exit on IF=1 change. */
LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
goto ResumeExecution; /* we check for pending guest interrupts there */
case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
/* Skip instruction and continue directly. */
/* Continue execution.*/
goto ResumeExecution;
case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
{
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
{
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
{
Log2(("VMX: Rdtsc\n"));
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
{
Log2(("VMX: invlpg\n"));
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
break;
}
case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
{
/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
break;
}
case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
{
{
Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
{
case 0:
break;
case 2:
break;
case 3:
break;
case 4:
break;
case 8:
/* CR8 contains the APIC TPR */
Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
break;
default:
AssertFailed();
break;
}
/* Check if a sync operation is pending. */
{
}
break;
Log2(("VMX: mov x, crx\n"));
STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
/* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
break;
Log2(("VMX: clts\n"));
break;
rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
break;
}
/* Update EIP if no error occurred. */
if (RT_SUCCESS(rc))
if (rc == VINF_SUCCESS)
{
/* Only resume if successful. */
goto ResumeExecution;
}
break;
}
case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
{
if (!DBGFIsStepping(pVM))
{
/* Disable drx move intercepts. */
/* Save the host and load the guest debug state. */
#ifdef VBOX_WITH_STATISTICS
if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
else
#endif
goto ResumeExecution;
}
/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
{
Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
}
else
{
Log2(("VMX: mov x, drx\n"));
}
/* Update EIP if no error occurred. */
if (RT_SUCCESS(rc))
if (rc == VINF_SUCCESS)
{
/* Only resume if successful. */
goto ResumeExecution;
}
break;
}
/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
{
bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
/** @todo necessary to make the distinction? */
{
}
else
/* paranoia */
{
break;
}
{
/* Disassemble manually to deal with segment prefixes. */
/** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
/** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
if (rc == VINF_SUCCESS)
{
if (fIOWrite)
{
}
else
{
}
}
else
}
else
{
if (fIOWrite)
{
}
else
{
if (IOM_SUCCESS(rc))
{
/* Write back to the EAX register. */
}
}
}
/*
* Handled the I/O return codes.
* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
*/
if (IOM_SUCCESS(rc))
{
/* Update EIP and continue execution. */
{
/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
{
for (unsigned i=0;i<4;i++)
{
{
/* Clear all breakpoint status flags and set the one we just hit. */
/* Note: AMD64 Architecture Programmer's Manual 13.1:
* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
* the contents have been read.
*/
/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
/* Paranoia. */
/* Resync DR7 */
/* Construct inject info. */
rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
goto ResumeExecution;
}
}
}
goto ResumeExecution;
}
break;
}
#ifdef VBOX_STRICT
if (rc == VINF_IOM_HC_IOPORT_READ)
else if (rc == VINF_IOM_HC_IOPORT_WRITE)
else
AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
#endif
break;
}
case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
LogFlow(("VMX_EXIT_TPR\n"));
/* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
goto ResumeExecution;
case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
goto ResumeExecution;
default:
/* The rest is handled after syncing the entire CPU state. */
break;
}
/* Note: the guest state isn't entirely synced back at this stage. */
/* Investigate why there was a VM-exit. (part 2) */
switch (exitReason)
{
case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
case VMX_EXIT_EPT_VIOLATION:
case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
/* Already handled above. */
break;
case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
break;
case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
AssertFailed(); /* Can't happen. Yet. */
break;
case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
AssertFailed(); /* Can't happen afaik. */
break;
case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
break;
case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
/** Check if external interrupts are pending; if so, don't switch back. */
goto ResumeExecution;
rc = VINF_EM_HALT;
break;
case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
AssertFailed(); /* can't happen. */
break;
case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
/** @todo inject #UD immediately */
break;
case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
/* already handled above */
|| rc == VINF_EM_RAW_INTERRUPT
|| rc == VERR_EM_INTERPRETER
|| rc == VINF_EM_RAW_EMULATE_INSTR
|| rc == VINF_PGM_SYNC_CR3
|| rc == VINF_IOM_HC_IOPORT_READ
|| rc == VINF_IOM_HC_IOPORT_WRITE
|| rc == VINF_EM_RAW_GUEST_TRAP
|| rc == VINF_TRPM_XCPT_DISPATCHED
|| rc == VINF_EM_RESCHEDULE_REM,
("rc = %d\n", rc));
break;
case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
/* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
break;
case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
break;
case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
break;
case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
{
#ifdef VBOX_STRICT
RTCCUINTREG val = 0;
Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
#endif /* VBOX_STRICT */
break;
}
case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
default:
break;
}
end:
/* Signal changes for the recompiler. */
CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
{
/* On the next entry we'll only sync the host context. */
}
else
{
/* On the next entry we'll sync everything. */
/** @todo we can do better than this */
/* Not in the VINF_PGM_CHANGE_MODE though! */
}
/* translate into a less severe return code */
if (rc == VERR_EM_INTERPRETER)
else
/* Try to extract more information about what might have gone wrong here. */
if (rc == VERR_VMX_INVALID_VMCS_PTR)
{
}
});
Log2(("X"));
return rc;
}
/**
* Enters the VT-x session
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
* @param pCpu CPU info struct
*/
{
if (!(cr4 & X86_CR4_VMXE))
{
AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
return VERR_VMX_X86_CR4_VMXE_CLEARED;
}
/* Activate the VM Control Structure. */
if (RT_FAILURE(rc))
return rc;
return VINF_SUCCESS;
}
/**
* Leaves the VT-x session
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
* @param pCtx CPU context
*/
{
/* Save the guest debug state if necessary. */
{
/* Enable drx move intercepts again. */
/* Resync the debug registers the next time. */
}
else
/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
return VINF_SUCCESS;
}
/**
* Flush the TLB (EPT)
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VM CPU to operate on.
* @param enmFlush Type of flush
* @param GCPhys Physical address of the page to flush
*/
{
}
#ifdef HWACCM_VTX_WITH_VPID
/**
* Flush the TLB (EPT)
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VM CPU to operate on.
* @param enmFlush Type of flush
* @param GCPtr Virtual address of the page to flush
*/
{
#if HC_ARCH_BITS == 32
/* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
if ( CPUMIsGuestInLongMode(pVCpu)
&& !VMX_IS_64BIT_HOST_MODE())
{
}
else
#endif
{
}
}
#endif /* HWACCM_VTX_WITH_VPID */
/**
* Invalidates a guest page
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VM CPU to operate on.
* @param GCVirt Page to invalidate
*/
{
/* Only relevant if we want to use VPID.
* In the nested paging case we still see such calls, but
* can safely ignore them. (e.g. after cr3 updates)
*/
#ifdef HWACCM_VTX_WITH_VPID
/* Skip it if a TLB flush is already pending. */
if ( !fFlushPending
#endif /* HWACCM_VTX_WITH_VPID */
return VINF_SUCCESS;
}
/**
* Invalidates a guest page by physical address
*
* NOTE: Assumes the current instruction references this physical page though a virtual address!!
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VM CPU to operate on.
* @param GCPhys Page to invalidate
*/
{
/* Skip it if a TLB flush is already pending. */
if (!fFlushPending)
return VINF_SUCCESS;
}
/**
* Report world switch error and dump some useful debug info
*
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
* @param rc Return code
* @param pCtx Current CPU context (not updated)
*/
{
switch (rc)
{
AssertFailed();
break;
{
int rc;
if (rc == VINF_SUCCESS)
{
Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
#ifdef VBOX_STRICT
ASMGetGDTR(&gdtr);
{
}
{
}
{
}
{
}
{
}
{
}
{
}
if (VMX_IS_64BIT_HOST_MODE())
{
}
# endif
#endif /* VBOX_STRICT */
}
break;
}
default:
/* impossible */
break;
}
}
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
/**
* Prepares for and executes VMLAUNCH (64 bits guest mode)
*
* @returns VBox status code
* @param pCtx Guest context
* @param pCache VMCS cache
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
*/
DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
{
int rc;
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
#endif
#ifdef DEBUG
#endif
aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
aParam[5] = 0;
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
#endif
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
#endif
#ifdef DEBUG
AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
#endif
return rc;
}
/**
* Executes the specified handler in 64 mode
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
* @param pCtx Guest context
* @param pfnHandler RC handler
* @param cbParam Number of parameters
* @param paParam Array of 32 bits parameters
*/
VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
{
/* @todo This code is not guest SMP safe (hyper stack) */
Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
#ifdef VBOX_STRICT
#endif
/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
/* Leave VMX Root Mode. */
VMXDisable();
for (int i=(int)cbParam-1;i>=0;i--)
/* Call switcher. */
/* Make sure the VMX instructions don't cause #UD faults. */
/* Enter VMX Root Mode */
if (RT_FAILURE(rc2))
{
if (pVM)
return VERR_VMX_VMXON_FAILED;
}
#ifdef RT_OS_WINDOWS
#else
#endif
return rc;
}
#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
/**
* Executes VMWRITE
*
* @returns VBox status code
* @param pVCpu The VMCPU to operate on.
* @param idxField VMCS index
* @param u64Val 16, 32 or 64 bits value
*/
{
int rc;
switch (idxField)
{
case VMX_VMCS_GUEST_EFER_FULL:
case VMX_VMCS_CTRL_EPTP_FULL:
/* These fields consist of two parts, which are both writable in 32 bits mode. */
return rc;
case VMX_VMCS64_GUEST_TR_BASE:
case VMX_VMCS64_GUEST_CR0:
case VMX_VMCS64_GUEST_CR4:
case VMX_VMCS64_GUEST_CR3:
case VMX_VMCS64_GUEST_DR7:
case VMX_VMCS64_GUEST_RIP:
case VMX_VMCS64_GUEST_RSP:
case VMX_VMCS64_GUEST_CS_BASE:
case VMX_VMCS64_GUEST_DS_BASE:
case VMX_VMCS64_GUEST_ES_BASE:
case VMX_VMCS64_GUEST_FS_BASE:
case VMX_VMCS64_GUEST_GS_BASE:
case VMX_VMCS64_GUEST_SS_BASE:
/* Queue a 64 bits value as we can't set it in 32 bits host mode. */
if (u64Val >> 32ULL)
else
return rc;
default:
return VERR_INVALID_PARAMETER;
}
}
/**
* Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
*
* @param pVCpu The VMCPU to operate on.
* @param idxField VMCS field
* @param u64Val Value
*/
{
AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
/* Make sure there are no duplicates. */
{
{
return VINF_SUCCESS;
}
}
return VINF_SUCCESS;
}
#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
#ifdef VBOX_STRICT
{
switch(idxField)
{
case VMX_VMCS64_GUEST_RIP:
case VMX_VMCS64_GUEST_RSP:
case VMX_VMCS_GUEST_RFLAGS:
case VMX_VMCS64_GUEST_CR0:
case VMX_VMCS64_GUEST_CR4:
case VMX_VMCS64_GUEST_DR7:
case VMX_VMCS64_GUEST_CS_BASE:
case VMX_VMCS64_GUEST_DS_BASE:
case VMX_VMCS64_GUEST_ES_BASE:
case VMX_VMCS64_GUEST_FS_BASE:
case VMX_VMCS64_GUEST_GS_BASE:
case VMX_VMCS64_GUEST_SS_BASE:
case VMX_VMCS64_GUEST_TR_BASE:
case VMX_VMCS32_RO_IDT_INFO:
case VMX_VMCS64_GUEST_CR3:
return true;
}
return false;
}
{
switch(idxField)
{
case VMX_VMCS64_GUEST_TR_BASE:
case VMX_VMCS64_GUEST_CR0:
case VMX_VMCS64_GUEST_CR4:
case VMX_VMCS64_GUEST_CR3:
case VMX_VMCS64_GUEST_DR7:
case VMX_VMCS64_GUEST_RIP:
case VMX_VMCS64_GUEST_RSP:
case VMX_VMCS64_GUEST_CS_BASE:
case VMX_VMCS64_GUEST_DS_BASE:
case VMX_VMCS64_GUEST_ES_BASE:
case VMX_VMCS64_GUEST_FS_BASE:
case VMX_VMCS64_GUEST_GS_BASE:
case VMX_VMCS64_GUEST_SS_BASE:
return true;
}
return false;
}
#endif