HWVMXR0.cpp revision 44990a165da4d0de9c409ff0494b84ca4cb97f75
b450d7a1747c5f4fb7c917a8ec1f9ce8440d7ffevboxsync * HM VMX (VT-x) - Host Context Ring-0.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Copyright (C) 2006-2012 Oracle Corporation
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * available from http://www.virtualbox.org. This file is free software;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * you can redistribute it and/or modify it under the terms of the GNU
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * General Public License (GPL) as published by the Free Software
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync/*******************************************************************************
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync* Header Files *
b450d7a1747c5f4fb7c917a8ec1f9ce8440d7ffevboxsync*******************************************************************************/
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync/*******************************************************************************
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync* Defined Constants And Macros *
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync*******************************************************************************/
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync# define VMX_IS_64BIT_HOST_MODE() (true)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync# define VMX_IS_64BIT_HOST_MODE() (false)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync/*******************************************************************************
6a795f9e75e30c7f1d75cd45e5de233c71662f58vboxsync* Global Variables *
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync*******************************************************************************/
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync/* IO operation lookup arrays. */
6a795f9e75e30c7f1d75cd45e5de233c71662f58vboxsyncstatic uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
6a795f9e75e30c7f1d75cd45e5de233c71662f58vboxsync/** See HMR0A.asm. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync/*******************************************************************************
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync* Local Functions *
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync*******************************************************************************/
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic DECLCALLBACK(void) hmR0VmxSetupTLBEPT(PVM pVM, PVMCPU pVCpu);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic DECLCALLBACK(void) hmR0VmxSetupTLBVPID(PVM pVM, PVMCPU pVCpu);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic DECLCALLBACK(void) hmR0VmxSetupTLBBoth(PVM pVM, PVMCPU pVCpu);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic DECLCALLBACK(void) hmR0VmxSetupTLBDummy(PVM pVM, PVMCPU pVCpu);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic void hmR0VmxFlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH_EPT enmFlush);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic void hmR0VmxFlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH_VPID enmFlush, RTGCPTR GCPtr);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic void hmR0VmxUpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic void hmR0VmxSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic void hmR0VmxReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc, PCPUMCTX pCtx);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Updates error from VMCS to HMCPU's lasterror record.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param rc The error code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic void hmR0VmxCheckError(PVM pVM, PVMCPU pVCpu, int rc)
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync VMXReadVmcs(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync pVCpu->hm.s.vmx.lasterror.ulInstrError = instrError;
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * Sets up and activates VT-x on the current CPU.
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync * @returns VBox status code.
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync * @param pCpu Pointer to the CPU info struct.
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync * @param pVM Pointer to the VM. (can be NULL after a resume!!)
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync * @param pvCpuPage Pointer to the global CPU page.
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync * @param HCPhysCpuPage Physical address of the global CPU page.
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * @param fEnabledByHost Set if SUPR0EnableVTx or similar was used to enable
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * VT-x/AMD-V on the host.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR0DECL(int) VMXR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Set revision dword at the beginning of the VMXON structure. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync *(uint32_t *)pvCpuPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * (which can have very bad consequences!!!)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo r=bird: Why is this code different than the probing code earlier
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * on? It just sets VMXE if needed and doesn't check that it isn't
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * set. Mac OS X host_vmxoff may leave this set and we'll fail here
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * and debug-assert in the calling code. This is what caused the
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * "regression" after backing out the SUPR0EnableVTx code hours before
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * 4.2.0GA (reboot fixed the issue). I've changed here to do the same
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * as the init code. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE); /* Make sure the VMX instructions don't cause #UD faults. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Enter VM root mode.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Flush all VPIDs (in case we or any other hypervisor have been using VPIDs) so that
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * we can avoid an explicit flush while using new VPIDs. We would still need to flush
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * each time while reusing a VPID after hitting the MaxASID limit once.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxFlushVPID(pVM, NULL /* pvCpu */, VMX_FLUSH_VPID_ALL_CONTEXTS, 0 /* GCPtr */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Deactivates VT-x on the current CPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCpu Pointer to the CPU info struct.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pvCpuPage Pointer to the global CPU page.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param HCPhysCpuPage Physical address of the global CPU page.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR0DECL(int) VMXR0DisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* If we're somehow not in VMX root mode, then we shouldn't dare leaving it. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Leave VMX Root Mode. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* And clear the X86_CR4_VMXE bit. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Does Ring-0 per VM VT-x initialization.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync /* Allocate one page for the APIC physical page (serves for filtering accesses). */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync rc = RTR0MemObjAllocCont(&pVM->hm.s.vmx.hMemObjApicAccess, PAGE_SIZE, false /* fExecutable */);
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync pVM->hm.s.vmx.pbApicAccess = (uint8_t *)RTR0MemObjAddress(pVM->hm.s.vmx.hMemObjApicAccess);
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync pVM->hm.s.vmx.HCPhysApicAccess = RTR0MemObjGetPagePhysAddr(pVM->hm.s.vmx.hMemObjApicAccess, 0);
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync ASMMemZero32(pVM->hm.s.vmx.pbApicAccess, PAGE_SIZE);
824104c3b60b9c8d5c03c40658e33ecd6c4fa9e8vboxsync rc = RTR0MemObjAllocCont(&pVM->hm.s.vmx.hMemObjScratch, PAGE_SIZE, false /* fExecutable */);
824104c3b60b9c8d5c03c40658e33ecd6c4fa9e8vboxsync pVM->hm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hm.s.vmx.hMemObjScratch);
824104c3b60b9c8d5c03c40658e33ecd6c4fa9e8vboxsync pVM->hm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hm.s.vmx.hMemObjScratch, 0);
824104c3b60b9c8d5c03c40658e33ecd6c4fa9e8vboxsync strcpy((char *)pVM->hm.s.vmx.pbScratch, "SCRATCH Magic");
824104c3b60b9c8d5c03c40658e33ecd6c4fa9e8vboxsync *(uint64_t *)(pVM->hm.s.vmx.pbScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Allocate VMCSs for all guest CPUs. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Allocate one page for the VM control structure (VMCS). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = RTR0MemObjAllocCont(&pVCpu->hm.s.vmx.hMemObjVMCS, PAGE_SIZE, false /* fExecutable */);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync pVCpu->hm.s.vmx.pvVMCS = RTR0MemObjAddress(pVCpu->hm.s.vmx.hMemObjVMCS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.HCPhysVMCS = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.vmx.hMemObjVMCS, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Allocate one page for the virtual APIC page for TPR caching. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = RTR0MemObjAllocCont(&pVCpu->hm.s.vmx.hMemObjVAPIC, PAGE_SIZE, false /* fExecutable */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.pbVAPIC = (uint8_t *)RTR0MemObjAddress(pVCpu->hm.s.vmx.hMemObjVAPIC);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.HCPhysVAPIC = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.vmx.hMemObjVAPIC, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Allocate the MSR bitmap if this feature is supported. */
a9f41cb889f53e8407561a6155052c441eb0fc5fvboxsync if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync rc = RTR0MemObjAllocCont(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, PAGE_SIZE, false /* fExecutable */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.pvMsrBitmap = (uint8_t *)RTR0MemObjAddress(pVCpu->hm.s.vmx.hMemObjMsrBitmap);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.vmx.hMemObjMsrBitmap, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync memset(pVCpu->hm.s.vmx.pvMsrBitmap, 0xff, PAGE_SIZE);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Allocate one page for the guest MSR load area (for preloading guest MSRs during the world switch). */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync rc = RTR0MemObjAllocCont(&pVCpu->hm.s.vmx.hMemObjGuestMsr, PAGE_SIZE, false /* fExecutable */);
b28326220af580dde4a61f15930f51fe584dc896vboxsync pVCpu->hm.s.vmx.pvGuestMsr = (uint8_t *)RTR0MemObjAddress(pVCpu->hm.s.vmx.hMemObjGuestMsr);
b28326220af580dde4a61f15930f51fe584dc896vboxsync pVCpu->hm.s.vmx.HCPhysGuestMsr = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.vmx.hMemObjGuestMsr, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Allocate one page for the host MSR load area (for restoring host MSRs after the world switch back). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = RTR0MemObjAllocCont(&pVCpu->hm.s.vmx.hMemObjHostMsr, PAGE_SIZE, false /* fExecutable */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.pvHostMsr = (uint8_t *)RTR0MemObjAddress(pVCpu->hm.s.vmx.hMemObjHostMsr);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.HCPhysHostMsr = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.vmx.hMemObjHostMsr, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Current guest paging mode. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hm.s.vmx.pvVMCS, (uint32_t)pVCpu->hm.s.vmx.HCPhysVMCS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Does Ring-0 per VM VT-x termination.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync RTR0MemObjFree(pVCpu->hm.s.vmx.hMemObjVMCS, false);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.vmx.hMemObjVAPIC != NIL_RTR0MEMOBJ)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync RTR0MemObjFree(pVCpu->hm.s.vmx.hMemObjVAPIC, false);
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync if (pVCpu->hm.s.vmx.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync RTR0MemObjFree(pVCpu->hm.s.vmx.hMemObjMsrBitmap, false);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.vmx.hMemObjHostMsr != NIL_RTR0MEMOBJ)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync RTR0MemObjFree(pVCpu->hm.s.vmx.hMemObjHostMsr, false);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.vmx.hMemObjGuestMsr != NIL_RTR0MEMOBJ)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync RTR0MemObjFree(pVCpu->hm.s.vmx.hMemObjGuestMsr, false);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.hMemObjApicAccess != NIL_RTR0MEMOBJ)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync RTR0MemObjFree(pVM->hm.s.vmx.hMemObjApicAccess, false);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.hMemObjScratch != NIL_RTR0MEMOBJ)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync RTR0MemObjFree(pVM->hm.s.vmx.hMemObjScratch, false);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Sets up VT-x for the specified VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Initialize these always, see hmR3InitFinalizeR0().*/
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Determine optimal flush type for EPT. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_SINGLE_CONTEXT;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_ALL_CONTEXTS;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Should never really happen. EPT is supported but no suitable flush types supported.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * We cannot ignore EPT at this point as we've already setup Unrestricted Guest execution.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_NOT_SUPPORTED;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Should never really happen. EPT is supported but INVEPT instruction is not supported.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_NOT_SUPPORTED;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Determine optimal flush type for VPID. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID)
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_SINGLE_CONTEXT;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_ALL_CONTEXTS;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Neither SINGLE nor ALL context flush types for VPID supported by the CPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * We do not handle other flush type combinations, ignore VPID capabilities.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("VMXR0SetupVM: Only VMX_FLUSH_VPID_INDIV_ADDR supported. Ignoring VPID.\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("VMXR0SetupVM: Only VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS supported. Ignoring VPID.\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_NOT_SUPPORTED;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Should not really happen. EPT is supported but INVEPT is not supported.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Ignore VPID capabilities as our code relies on using INVEPT for selective flushing.
6da7ae3144a7be1443dd37052b24370bf210fda1vboxsync Log(("VMXR0SetupVM: VPID supported without INVEPT support. Ignoring VPID.\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_NOT_SUPPORTED;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Set revision dword at the beginning of the VMCS structure. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync *(uint32_t *)pVCpu->hm.s.vmx.pvVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Clear and activate the VMCS.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("HCPhysVMCS = %RHp\n", pVCpu->hm.s.vmx.HCPhysVMCS));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Set required bits to one and zero according to the MSR capabilities.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val |= VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT /* External interrupts */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT; /* Non-maskable interrupts */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Enable the VMX preemption timer.
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync val |= VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER;
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS, val);
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync * VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync * Set required bits to one and zero according to the MSR capabilities.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync /* Program which event cause VM-exits and which features we want to use. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync the guest (host thinks the cpu load is high) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync * failure with an invalid control fields error. (combined with some other exit reasons)
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* We will use the secondary control if it's present. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Mask away the bits that the CPU doesn't support */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo make sure they don't conflict with the above requirements. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Set required bits to one and zero according to the MSR capabilities.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Mask away the bits that the CPU doesn't support */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo make sure they don't conflict with the above requirements. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val &= pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS2, val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * VMX_VMCS_CTRL_CR3_TARGET_COUNT
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Set required bits to one and zero according to the MSR capabilities.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Forward all exception except #NM & #PF to the guest.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * We always need to check pagefaults since our shadow page table can be out of sync.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * And we always lazily sync the FPU & XMM state. .
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo Possible optimization:
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Keep the FPU and XMM state current in the EM thread. That way there's no need to
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * registers ourselves of course.
8b82f5ce032cb07de31804c998483b0988530aebvboxsync * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Don't filter page faults, all of them should cause a world switch.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_A_FULL, 0);
9083f76e8c5709604766d0215a380de516e781eevboxsync rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_B_FULL, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Set the MSR bitmap address.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_MSR_BITMAP_FULL, pVCpu->hm.s.vmx.HCPhysMsrBitmap);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Allow the guest to directly modify these MSRs; they are loaded/stored automatically
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * using MSR-load/store areas in the VMCS.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync hmR0VmxSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync hmR0VmxSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync hmR0VmxSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxSetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync hmR0VmxSetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync hmR0VmxSetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync hmR0VmxSetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxSetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.vmx.u64ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxSetMSRPermission(pVCpu, MSR_K8_TSC_AUX, true, true);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Set the guest & host MSR load/store physical addresses.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysHostMsr);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Optional */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_TPR_THRESHOLD, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVAPIC);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, pVM->hm.s.vmx.HCPhysApicAccess);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Set link pointer to -1. Not currently used. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Clear VMCS, marking it inactive. Clear implementation specific data and writing back
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * VMCS data back to memory.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Configure the VMCS read cache.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_RIP);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_RSP);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_RFLAGS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_CR0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_CR4);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_DR7);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_SYSENTER_EIP);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_SYSENTER_ESP);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_GDTR_BASE);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_IDTR_BASE);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Status code VMCS reads.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_EXIT_REASON);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_IDT_INFO);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS_GUEST_CR3);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXSetupCachedReadVmcs(pCache, VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync } /* for each VMCPU */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Setup the right TLB function based on CPU capabilities.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.pfnFlushTaggedTlb = hmR0VmxSetupTLBBoth;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.pfnFlushTaggedTlb = hmR0VmxSetupTLBEPT;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.pfnFlushTaggedTlb = hmR0VmxSetupTLBVPID;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVM->hm.s.vmx.pfnFlushTaggedTlb = hmR0VmxSetupTLBDummy;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Sets the permission bits for the specified MSR.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param ulMSR The MSR value.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param fRead Whether reading is allowed.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param fWrite Whether writing is allowed.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic void hmR0VmxSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync uint8_t *pvMsrBitmap = (uint8_t *)pVCpu->hm.s.vmx.pvMsrBitmap;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * 0x000 - 0x3ff - Low MSR read bits
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * 0x400 - 0x7ff - High MSR read bits
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * 0x800 - 0xbff - Low MSR write bits
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * 0xc00 - 0xfff - High MSR write bits
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Pentium-compatible MSRs */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* AMD Sixth Generation x86 Processor MSRs */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Injects an event (trap or external interrupt).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code. Note that it may return VINF_EM_RESET to
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * indicate a triple fault when injecting X86_XCPT_DF.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Pointer to the guest CPU Context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param intInfo VMX interrupt info.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param cbInstr Opcode length of faulting instruction.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param errCode Error code (optional).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic int hmR0VmxInjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[iGate & MASK_INJECT_IRQ_STAT]);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogFlow(("hmR0VmxInjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogFlow(("hmR0VmxInjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync || !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Injecting events doesn't work right with real mode emulation.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * (#GP if we try to inject external hardware interrupts)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Inject the interrupt or trap directly instead.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * ASSUMES no access handlers for the bits we read or write below (should be safe).
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Check if the interrupt handler is present.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo2 = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo2 |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo2, 0, 0 /* no error code according to the Intel docs */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync || iGate == 3 /* Both #BP and #OF point to the instruction after. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Read the selector:offset pair of the interrupt handler.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler, sizeof(offset)); AssertRC(rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleReadGCPhys(pVM, &sel, GCPhysHandler + 2, sizeof(sel)); AssertRC(rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Construct the stack frame.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo Check stack limit. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss.Sel, pCtx->sp, pCtx->eflags.u));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ss.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss.Sel, pCtx->sp, pCtx->cs.Sel));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ss.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss.Sel, pCtx->sp, ip));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ss.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Update the CPU state for executing the handler.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCtx->eflags.u &= ~(X86_EFL_IF | X86_EFL_TF | X86_EFL_RF | X86_EFL_AC);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_SEGMENT_REGS;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Set event injection state.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Checks for pending guest interrupts and injects them.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
5e403442588989687ee8fb66dd921dd08199bfd0vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Pointer to the guest CPU context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic int hmR0VmxCheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Dispatch any pending interrupts (injected before, but a VM exit occurred prematurely).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hm.s.Event.intInfo,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
5e403442588989687ee8fb66dd921dd08199bfd0vboxsync rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, pVCpu->hm.s.Event.intInfo, 0, pVCpu->hm.s.Event.errCode);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * If an active trap is already pending, we must forward it first!
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo SMI interrupts. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * When external interrupts are pending, we should exit the VM when IF is set.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (!(pVCpu->hm.s.vmx.u64ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* else nothing to do but wait */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync u8Interrupt, u8Interrupt, rc, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Just continue */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * If a new event is pending, dispatch it now.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &errCode, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Clear the pending trap.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Valid error codes. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync } /* if (interrupts can be dispatched) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Checks for pending VMX events and converts them to TRPM. Before we execute any instruction
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * outside of VMX, any pending VMX event must be converted so that it can be delivered properly.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* If a trap was already pending, we did something wrong! */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert((TRPMQueryTrap(pVCpu, NULL, NULL) == VERR_TRPM_NO_ACTIVE_TRAP));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Clear the pending event and move it over to TRPM for the rest
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * of the world to see.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.intInfo))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync enmTrapType = TRPM_32BIT_HACK; /* Can't get here. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync TRPMAssertTrap(pVCpu, VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVCpu->hm.s.Event.intInfo), enmTrapType);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hm.s.Event.intInfo))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync TRPMSetErrorCode(pVCpu, pVCpu->hm.s.Event.errCode);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync //@todo: Is there any situation where we need to call TRPMSetFaultAddress()?
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Save the host state into the VMCS.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Host CPU Context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_CONTEXT)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Control registers.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS_HOST_CR4, ASMGetCR4());
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Selector registers.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS16_HOST_FIELD_TR, SelTR);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * GDTR & IDTR.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_HOST_IDTR_BASE, idtr64.uAddr);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Save the base address of the TR selector.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pDesc = (PCX86DESCHC)(gdtr.pGdt + (SelTR & X86_SEL_MASK));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync uint64_t trBase64 = X86DESC64_BASE((PX86DESC64)pDesc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS_HOST_TR_BASE, trBase64);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * FS base and GS base.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Sysenter MSRs.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo expensive!! */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Store all host MSRs in the VM-Exit load area, so they will be reloaded after
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * the world switch back to the host.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync unsigned idxMsr = 0;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync uint32_t u32HostExtFeatures = ASMCpuId_EDX(0x80000001);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (u32HostExtFeatures & (X86_CPUID_EXT_FEATURE_EDX_NX | X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Must match the EFER value in our 64 bits switcher. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pMsr->u64Value = ASMRdMsr(MSR_K6_EFER) | MSR_K6_EFER_LME | MSR_K6_EFER_SCE | MSR_K6_EFER_NXE;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pMsr->u64Value = ASMRdMsr(MSR_K6_STAR); /* legacy syscall eip, cs & ss */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pMsr->u64Value = ASMRdMsr(MSR_K8_LSTAR); /* 64 bits mode syscall rip */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pMsr->u64Value = ASMRdMsr(MSR_K8_SF_MASK); /* syscall flag mask */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* The KERNEL_GS_BASE MSR doesn't work reliably with auto load/store. See @bugref{6208} */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pMsr->u64Value = ASMRdMsr(MSR_K8_KERNEL_GS_BASE); /* swapgs exchange value */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.vmx.u64ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo r=ramshankar: check IA32_VMX_MISC bits 27:25 for valid idxMsr
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * range. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, idxMsr);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Loads the 4 PDPEs into the guest state when nested paging is used and the
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync * guest operates in PAE mode.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Pointer to the guest CPU context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic int hmR0VmxLoadPaePdpes(PVMCPU pVCpu, PCPUMCTX pCtx)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, aPdpes[0].u); AssertRCReturn(rc, rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, aPdpes[1].u); AssertRCReturn(rc, rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, aPdpes[2].u); AssertRCReturn(rc, rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, aPdpes[3].u); AssertRCReturn(rc, rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Saves the 4 PDPEs into the guest state when nested paging is used and the
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * guest operates in PAE mode.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VM CPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Pointer to the guest CPU context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @remarks Tell PGM about CR3 changes before calling this helper.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic int hmR0VmxSavePaePdpes(PVMCPU pVCpu, PCPUMCTX pCtx)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &aPdpes[0].u); AssertRCReturn(rc, rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &aPdpes[1].u); AssertRCReturn(rc, rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &aPdpes[2].u); AssertRCReturn(rc, rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &aPdpes[3].u); AssertRCReturn(rc, rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Update the exception bitmap according to the current CPU state.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Pointer to the guest CPU context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic void hmR0VmxUpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Set up a mask for intercepting traps.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo Do we really need to always intercept #DB? */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Without nested paging, #PF must be intercepted to implement shadow paging.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo NP state won't change so maybe we should build the initial trap mask up front? */
9b9a21c4dedad15ac8b2059a858a94c5a33db1bdvboxsync /* Catch floating point exceptions if we need to report them to the guest in a different way. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo Despite the claim to intercept everything, with NP we do not intercept #PF. Should we? */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync int rc = VMXWriteVmcs(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32TrapMask);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Loads a minimal guest state.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Pointer to the guest CPU context.
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsyncVMMR0DECL(void) VMXR0LoadMinimalGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2d8894b1c178c9f1199cac84059ca66aa5dee6b3vboxsync Assert(!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_ALL_GUEST));
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync * Load EIP, ESP and EFLAGS.
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync rc = VMXWriteVmcs64(VMX_VMCS_GUEST_RIP, pCtx->rip);
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_RSP, pCtx->rsp);
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync * Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1.
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync * Check if real mode emulation using v86 mode.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Loads the guest state.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Pointer to the guest CPU context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * VMX_VMCS_CTRL_ENTRY_CONTROLS
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Set required bits to one and zero according to the MSR capabilities.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Load guest debug controls (DR7 & IA32_DEBUGCTL_MSR).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* else Must be zero when AMD64 is not available. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Mask away the bits that the CPU doesn't support.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_ENTRY_CONTROLS, val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * VMX_VMCS_CTRL_EXIT_CONTROLS
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Set required bits to one and zero according to the MSR capabilities.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Save debug controls (DR7 & IA32_DEBUGCTL_MSR)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* else Must be zero when AMD64 is not available. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE; /* our switcher goes to long mode */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Don't acknowledge external interrupts on VM-exit.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_EXIT_CONTROLS, val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Guest CPU context: ES, CS, SS, DS, FS, GS.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Correct weird requirements for switching to protected mode.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Flush the recompiler code cache as it's not unlikely the guest will rewrite code
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * it will later execute in real mode (OpenBSD 4.0 is one such example)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * DPL of all hidden selector registers must match the current CPL (0).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Guest CPU context: LDTR.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_LDTR_BASE, 0); /* @todo removing "64" in the function should be the same. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr.Sel);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtr.u32Limit);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtr.u64Base); /* @todo removing "64" and it should be the same */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtr.Attr.u);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Guest CPU context: TR.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Real mode emulation using v86 mode with CR4.VME (interrupt redirection
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * using the int bitmap in the TSS).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* We convert it here every time as PCI regions could be reconfigured. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_TR_LIMIT, HM_VTX_TSS_SIZE);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr.Sel);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->tr.u32Limit);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_TR_BASE, pCtx->tr.u64Base);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* The TSS selector must be busy (REM bugs? see defect #XXXX). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Default if no TR selector has been set (otherwise vmlaunch will fail!) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg((val & 0xf) == X86_SEL_TYPE_SYS_386_TSS_BUSY || (val & 0xf) == X86_SEL_TYPE_SYS_286_TSS_BUSY,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Guest CPU context: GDTR.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Guest CPU context: IDTR.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Sysenter MSRs.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_MSR)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs64(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Guest CPU context: Control registers.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Always use #NM exceptions to load the FPU/XMM state on demand. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo check if we support the old style mess correctly. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Disable CR3 read/write monitoring as we don't need it for EPT. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.u64ProcCtls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
dba0e7f8f385de972564b6917e305b8f53ea3480vboxsync /* Reenable CR3 read/write monitoring as our identity mapped page table is active. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
4d4628e1fe67e333b01942cc6ac92818832fd0edvboxsync /* Always enable caching. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * CR0 flags owned by the host; if the guests attempts to change them, then the VM will exit.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync | X86_CR0_CD /* Bit not restored during VM-exit! */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync | X86_CR0_NW /* Bit not restored during VM-exit! */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * When the guest's FPU state is active, then we no longer care about the FPU related bits.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val = pCtx->cr4 | (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** Must use PAE paging as we could use physical memory > 4 GB */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync default: /* shut up gcc */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Our identity mapping is a 32 bits page directory. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Turn off VME if we're in emulated real mode.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * CR4 flags owned by the host; if the guests attempts to change them, then the VM will exit.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Enable single stepping if requested and CPU supports it. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVCpu);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, pVCpu->hm.s.vmx.GCPhysEPTP);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* We convert it here every time as PCI regions could be reconfigured. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsgRC(rc, ("pNonPagingModeEPTPageTable = %RGv\n", pVM->hm.s.vmx.pNonPagingModeEPTPageTable));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * We use our identity mapping page table here as we need to map guest virtual to
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * guest physical addresses; EPT will take care of the translation to host physical addresses.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(val || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Save our shadow CR3 register. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Guest CPU context: Debug registers.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Resync DR7 */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Sync the hypervisor debug state now if any breakpoint is armed. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Save the host and load the hypervisor debug state. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* DRx intercepts remain enabled. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Override dr7 with the hypervisor value. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS_GUEST_DR7, CPUMGetHyperDR7(pVCpu));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Sync the debug state now if any breakpoint is armed. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Disable DRx move intercepts. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Save the host and load the guest debug state. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* IA32_DEBUGCTL MSR. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo do we really ever need this? */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXWriteVmcs(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * 64-bit guest mode.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_MSR)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Update these as wrmsr might have changed them. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS_GUEST_FS_BASE, pCtx->fs.u64Base);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS_GUEST_GS_BASE, pCtx->gs.u64Base);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Store all guest MSRs in the VM-entry load area, so they will be loaded
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * during VM-entry and restored into the VM-exit store area during VM-exit.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync PVMXMSR pMsr = (PVMXMSR)pVCpu->hm.s.vmx.pvGuestMsr;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync unsigned idxMsr = 0;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMGetGuestCpuId(pVCpu, 0x80000001, &u32Temp, &u32Temp, &u32Temp, &u32GstExtFeatures);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (u32GstExtFeatures & (X86_CPUID_EXT_FEATURE_EDX_NX | X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* VT-x will complain if only MSR_K6_EFER_LME is set. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pMsr->u64Value &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (u32GstExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pMsr->u64Value = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pMsr->u64Value = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pMsr->u64Value = pCtx->msrSFMASK; /* syscall flag mask */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* The KERNEL_GS_BASE MSR doesn't work reliably with auto load/store. See @bugref{6208} */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pMsr->u64Value = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( pVCpu->hm.s.vmx.u64ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && (u32GstExtFeatures & X86_CPUID_EXT_FEATURE_EDX_RDTSCP))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pMsr->u64Value);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, idxMsr);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, idxMsr);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync uint64_t cTicksToDeadline = TMCpuTickGetDeadlineAndTscOffset(pVCpu, &fOffsettedTsc, &pVCpu->hm.s.vmx.u64TSCOffset);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Make sure the returned values have sane upper and lower boundaries. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync uint64_t u64CpuHz = SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync cTicksToDeadline = RT_MIN(cTicksToDeadline, u64CpuHz / 64); /* 1/64 of a second */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync cTicksToDeadline = RT_MAX(cTicksToDeadline, u64CpuHz / 2048); /* 1/2048th of a second */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync cTicksToDeadline >>= pVM->hm.s.vmx.cPreemptTimerShift;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync uint32_t cPreemptionTickCount = (uint32_t)RT_MIN(cTicksToDeadline, UINT32_MAX - 16);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE, cPreemptionTickCount);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync fOffsettedTsc = TMCpuTickCanUseRealTSC(pVCpu, &pVCpu->hm.s.vmx.u64TSCOffset);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (u64CurTSC + pVCpu->hm.s.vmx.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET, applies to RDTSCP too. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, pVCpu->hm.s.vmx.u64TSCOffset);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Fall back to rdtsc, rdtscp emulation as we would otherwise pass decreasing tsc values to the guest. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.u64TSCOffset, u64CurTSC + pVCpu->hm.s.vmx.u64TSCOffset,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVCpu->hm.s.vmx.u64TSCOffset,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Done with the major changes */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_ALL_GUEST;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Minimal guest state update (ESP, EIP, EFLAGS mostly) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Syncs back the guest state from VMCS.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Pointer to the guest CPU context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncDECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* First sync back EIP, ESP, and EFLAGS. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXReadCachedVmcs(VMX_VMCS_GUEST_RFLAGS, &val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Take care of instruction fusing (sti, mov ss) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc |= VMXReadCachedVmcs(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(uInterruptState <= 2); /* only sti & mov ss */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("uInterruptState %x eip=%RGv\n", (uint32_t)uInterruptState, pCtx->rip));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Control registers. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXReadCachedVmcs(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val = (valShadow & pVCpu->hm.s.vmx.cr0_mask) | (val & ~pVCpu->hm.s.vmx.cr0_mask);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXReadCachedVmcs(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val = (valShadow & pVCpu->hm.s.vmx.cr4_mask) | (val & ~pVCpu->hm.s.vmx.cr4_mask);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * No reason to sync back the CRx registers. They can't be changed by the guest unless in
8b90eb0585fa16024709ca374c69f1eb5d5a5a7cvboxsync * the nested paging case where CR3 & CR4 can be changed by the guest.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && CPUMIsGuestInPagedProtectedModeEx(pCtx)) /** @todo check if we will always catch mode switches and such... */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Can be updated behind our back in the nested paging case. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Sync back DR7. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* System MSRs */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXReadCachedVmcs(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXReadCachedVmcs(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXReadCachedVmcs(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXReadCachedVmcs(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXReadCachedVmcs(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Real mode emulation using v86 mode. */
0d18f5b89ac6eb5d44c3e3d5453e55ab8cd7e804vboxsync /* Hide our emulation flags */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Restore original IOPL setting as we always use 0. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCtx->eflags.Bits.u2IOPL = pVCpu->hm.s.vmx.RealMode.eflags.Bits.u2IOPL;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Force a TR resync every time in case we switch modes. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_TR;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync * Save the possibly changed MSRs that we automatically restore and save during a world switch.
0db6a029780d9f9b347500e117320a8d5661efe5vboxsync for (unsigned i = 0; i < pVCpu->hm.s.vmx.cGuestMsrs; i++)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync PVMXMSR pMsr = (PVMXMSR)pVCpu->hm.s.vmx.pvGuestMsr;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* The KERNEL_GS_BASE MSR doesn't work reliably with auto load/store. See @bugref{6208} */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMSetGuestMsr(pVCpu, MSR_K8_TSC_AUX, pMsr->u64Value);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* EFER can't be changed without causing a VM-exit. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Assert(pCtx->msrEFER == pMsr->u64Value); */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Dummy placeholder for TLB flush handling before VM-entry. Used in the case
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * where neither EPT nor VPID is supported by the CPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic DECLCALLBACK(void) hmR0VmxSetupTLBDummy(PVM pVM, PVMCPU pVCpu)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Setup the tagged TLB for EPT+VPID.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic DECLCALLBACK(void) hmR0VmxSetupTLBBoth(PVM pVM, PVMCPU pVCpu)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * This can happen both for start & resume due to long jumps back to ring-3.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * or the host Cpu is online after a suspend/resume, so we cannot reuse the current ASID anymore.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync bool fNewAsid = false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Check for explicit TLB shootdowns.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCpu->uCurrentAsid = 1; /* start at 1; host uses 0 */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxFlushVPID(pVM, pVCpu, pVM->hm.s.vmx.enmFlushVpid, 0 /* GCPtr */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxFlushVPID(pVM, pVCpu, VMX_FLUSH_VPID_SINGLE_CONTEXT, 0 /* GCPtr */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxFlushEPT(pVM, pVCpu, pVM->hm.s.vmx.enmFlushEpt);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pVCpu->hm.s.uCurrentAsid && pCpu->uCurrentAsid,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ("hm->uCurrentAsid=%lu hm->cTlbFlushes=%lu cpu->uCurrentAsid=%lu cpu->cTlbFlushes=%lu\n",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * not be executed. See hmQueueInvlPage() where it is commented
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * out. Support individual entry flushing someday. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Flush individual guest entries using VPID from the TLB or as little as possible with EPT
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * as supported by the CPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync for (unsigned i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxFlushVPID(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, pVCpu->hm.s.TlbShootdown.aPages[i]);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxFlushEPT(pVM, pVCpu, pVM->hm.s.vmx.enmFlushEpt);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Update VMCS with the VPID. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync int rc = VMXWriteVmcs(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hm.s.uCurrentAsid);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Setup the tagged TLB for EPT only.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic DECLCALLBACK(void) hmR0VmxSetupTLBEPT(PVM pVM, PVMCPU pVCpu)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * This can happen both for start & resume due to long jumps back to ring-3.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * A change in the TLB flush count implies the host Cpu is online after a suspend/resume.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Check for explicit TLB shootdown flushes.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxFlushEPT(pVM, pVCpu, pVM->hm.s.vmx.enmFlushEpt);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * not be executed. See hmQueueInvlPage() where it is commented
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * out. Support individual entry flushing someday. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * We cannot flush individual entries without VPID support. Flush using EPT.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxFlushEPT(pVM, pVCpu, pVM->hm.s.vmx.enmFlushEpt);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo r=ramshankar: this is not accurate anymore with the VPID+EPT
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * handling. Should be fixed later. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Setup the tagged TLB for VPID.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic DECLCALLBACK(void) hmR0VmxSetupTLBVPID(PVM pVM, PVMCPU pVCpu)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * This can happen both for start & resume due to long jumps back to ring-3.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * or the host Cpu is online after a suspend/resume, so we cannot reuse the current ASID anymore.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Force a TLB flush on VM entry. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Check for explicit TLB shootdown flushes.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCpu->uCurrentAsid = 1; /* start at 1; host uses 0 */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxFlushVPID(pVM, pVCpu, pVM->hm.s.vmx.enmFlushVpid, 0 /* GCPtr */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pVCpu->hm.s.uCurrentAsid && pCpu->uCurrentAsid,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ("hm->uCurrentAsid=%lu hm->cTlbFlushes=%lu cpu->uCurrentAsid=%lu cpu->cTlbFlushes=%lu\n",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * not be executed. See hmQueueInvlPage() where it is commented
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * out. Support individual entry flushing someday. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Flush individual guest entries using VPID from the TLB or as little as possible with EPT
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * as supported by the CPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
824104c3b60b9c8d5c03c40658e33ecd6c4fa9e8vboxsync for (unsigned i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxFlushVPID(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, pVCpu->hm.s.TlbShootdown.aPages[i]);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync hmR0VmxFlushVPID(pVM, pVCpu, pVM->hm.s.vmx.enmFlushVpid, 0 /* GCPtr */);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync ("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync int rc = VMXWriteVmcs(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hm.s.uCurrentAsid);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /** @todo r=ramshankar: this is not accurate anymore with EPT+VPID handling.
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * Should be fixed later. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Runs guest code in a VT-x VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Pointer to the guest CPU context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync RTGCUINTREG exitReason = (RTGCUINTREG)VMX_EXIT_INVALID;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync unsigned cResume = 0;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(!(pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync || (pVCpu->hm.s.vmx.pbVAPIC && pVM->hm.s.vmx.pbApicAccess));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Check if we need to use TPR shadowing.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync || ( (( pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* This is not ideal, but if we don't clear the event injection in the VMCS right here,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * we may end up injecting some stale event into a VM, including injecting an event that
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * originated before a VM reset *after* the VM has been reset. See @bugref{6220}.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = VMXReadVmcs(VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS, &val2);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val2));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* allowed zero */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ((val2 & pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* allowed one */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ((val2 & ~pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = VMXReadVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, &val2);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val2));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Must be set according to the MSR, but can be cleared if nested paging is used.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync val2 |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* allowed zero */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ((val2 & pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* allowed one */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ((val2 & ~pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = VMXReadVmcs(VMX_VMCS32_CTRL_ENTRY_CONTROLS, &val2);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val2));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* allowed zero */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ((val2 & pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* allowed one */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ((val2 & ~pVM->hm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = VMXReadVmcs(VMX_VMCS32_CTRL_EXIT_CONTROLS, &val2);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val2));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* allowed zero */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync if ((val2 & pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* allowed one */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ((val2 & ~pVM->hm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#endif /* VBOX_STRICT */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * We can jump to this point to resume execution after determining that a VM-exit is innocent.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (!STAM_REL_PROFILE_ADV_IS_RUNNING(&pVCpu->hm.s.StatEntry))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_REL_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit2, &pVCpu->hm.s.StatEntry, x);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync (int)pVCpu->hm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Not allowed to switch modes without reloading the host state (32->64 switcher)!! */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(fWasInLongMode == CPUMIsGuestInLongModeEx(pCtx));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Safety precaution; looping for too long here can have a very bad effect on the host.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (RT_UNLIKELY(++cResume > pVM->hm.s.cMaxResumeLoops))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Check for IRQ inhibition due to instruction fusing (sti, mov ss).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Irq inhibition is no longer active; clear the corresponding VMX state. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = VMXWriteVmcs(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Irq inhibition is no longer active; clear the corresponding VMX state. */
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync rc2 = VMXWriteVmcs(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Check for pending actions that force us to go back to ring-3.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( VM_FF_ISPENDING(pVM, VM_FF_HM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Check if a sync operation is pending. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Pending pool sync is forcing us back to ring 3; rc=%d\n", VBOXSTRICTRC_VAL(rc)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Intercept X86_XCPT_DB if stepping is enabled */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Check if a pgm pool flush is in progress. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VM_FF_ISPENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Check if DMA work is pending (2nd+ run). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VM_FF_ISPENDING(pVM, VM_FF_PDM_DMA) && cResume > 1)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Exit to ring-3 preemption/work is pending.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Interrupts are disabled before the call to make sure we don't miss any interrupt
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * further down, but hmR0VmxCheckPendingInterrupt makes that impossible.)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * shootdowns rely on this.
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPreemptPending);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * When external interrupts are pending, we should exit the VM when IF is set.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Note: *After* VM_FF_INHIBIT_INTERRUPTS check!
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = hmR0VmxCheckPendingInterrupt(pVM, pVCpu, pCtx);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo check timers?? */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * TPR caching using CR8 is only available in 64-bit mode.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Note: The 32-bit exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but this appears missing in Intel CPUs.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Note: We can't do this in LoadGuestState() as PDMApicGetTPR can jump back to ring-3 (lock)!! (no longer true) .
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo query and update the TPR only when it could have been changed (mmio
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * access & wrsmr (x2apic) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* TPR caching in CR8 */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* The TPR can be found at offset 0x80 in the APIC mmio page. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Two options here:
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * - external interrupt pending, but masked by the TPR value.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * -> a CR8 update that lower the current TPR value should cause an exit
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * - no pending interrupts
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteVmcs(VMX_VMCS32_CTRL_TPR_THRESHOLD, (fPending) ? (u8LastTPR >> 4) : 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Our patch code uses LSTAR for TPR caching. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo r=ramshankar: we should check for MSR-bitmap support here. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* A TPR change could activate a pending interrupt, so catch lstar writes. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * No interrupts are pending, so we don't need to be explicitely notified.
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * There are enough world switches for detecting pending interrupts.
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync hmR0VmxSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hm.s.idLastCpu,
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync else if (pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hm.s.cTlbFlushes,
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync else if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH))
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING-3!
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * (until the actual world switch)
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * Save the host state first.
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_CONTEXT)
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * Load the guest state.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Disable interrupts to make sure a poke will interrupt execution.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Non-register state Guest Context */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo change me according to cpu state */
75ef08b33f9c67a8dd50748ece1117aed8098d51vboxsync rc2 = VMXWriteVmcs(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_VMCS_GUEST_ACTIVITY_ACTIVE);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Set TLB flush state as checked until we return from the world switch. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync /* Deal with tagged TLB setup and invalidation. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Manual save and restore:
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * - General purpose registers except RIP, RSP
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * - CR2 (we don't care)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * - LDTR (reset to 0)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * - DRx (presumably not changed at all)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * - DR7 (reset to 0x400)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * - EFLAGS (reset to RT_BIT(1); not relevant)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* All done! Let's start VM execution. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Save the current TPR value in the LSTAR MSR so our patches can access it.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( (pVCpu->hm.s.vmx.u64ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && !(pVCpu->hm.s.vmx.u64ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.u64HostTSCAux = ASMRdMsr(MSR_K8_TSC_AUX);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64GuestTSCAux);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = hmR0VMXStartVMWrapXMM(pVCpu->hm.s.fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu, pVCpu->hm.s.vmx.pfnStartVM);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = pVCpu->hm.s.vmx.pfnStartVM(pVCpu->hm.s.fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Possibly the last TSC value seen by the guest (too high) (only when we're in TSC offset mode). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (!(pVCpu->hm.s.vmx.u64ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Restore host's TSC_AUX. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVCpu->hm.s.vmx.u64ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTSCAux);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ASMReadTSC() + pVCpu->hm.s.vmx.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Restore the host LSTAR MSR if the guest could have changed it.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.pbVAPIC[0x80] = pCtx->msrLSTAR = ASMRdMsr(MSR_K8_LSTAR);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(!pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries=%d\n",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* In case we execute a goto ResumeExecution later on. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Success. Query the guest state and figure out what has happened. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Investigate why there was a VM-exit. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = VMXReadCachedVmcs(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 |= VMXReadCachedVmcs(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 |= VMXReadCachedVmcs(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 |= VMXReadCachedVmcs(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 |= VMXReadCachedVmcs(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 |= VMXReadCachedVmcs(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc2 |= VMXReadCachedVmcs(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Sync back the guest state.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Note! NOW IT'S SAFE FOR LOGGING! */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Check if an injected event was interrupted prematurely.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = VMXReadCachedVmcs(VMX_VMCS32_RO_IDT_INFO, &val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hm.s.Event.intInfo)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Ignore 'int xx' as they'll be restarted anyway. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Ignore software exceptions (such as int3) as they'll reoccur when we restart the instruction anyway. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Error code present? */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hm.s.Event.intInfo))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = VMXReadCachedVmcs(VMX_VMCS32_RO_IDT_ERRCODE, &val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hm.s.Event.intInfo,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync else if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hm.s.Event.intInfo)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("E%d: New EIP=%x:%RGv\n", (uint32_t)exitReason, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("Interruption error code %d\n", (uint32_t)errCode));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Sync back the TPR if it was changed.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = PDMApicSetTPR(pVCpu, pVCpu->hm.s.vmx.pbVAPIC[0x80]);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync RTTraceBufAddMsgF(pVM->CTX_SUFF(hTraceBuf), "vmexit %08x %016RX64 at %04:%08RX64 %RX64",
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync exitReason, (uint64_t)exitQualification, pCtx->cs.Sel, pCtx->rip, (uint64_t)intInfo);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(rc == VINF_SUCCESS); /* might consider VERR_IPE_UNINITIALIZED_STATUS here later... */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_EXCEPTION_NMI: /* 0 Exception or non-maskable interrupt (NMI). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* External interrupt; leave to allow it to be dispatched again. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExit2Sub3, y3);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* External interrupt; leave to allow it to be dispatched again. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertFailed(); /* can't come here; fails the first check. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* no break */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("Hardware/software interrupt %d\n", vector));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Continue execution. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub3, y3);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub3, y3);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * A genuine pagefault. Forward the trap to the guest by injecting the exception and resuming execution.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Guest page fault at %RGv cr2=%RGv error code %RGv rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Now we must update CR2. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub3, y3);
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync && pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = PGMGstGetPage(pVCpu, (RTGCPTR)exitQualification, NULL, &GCPhys);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Only attempt to patch the instruction once. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Exit qualification contains the linear address of the page fault. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Shortcut for APIC TPR reads and writes. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = PGMGstGetPage(pVCpu, (RTGCPTR)exitQualification, NULL, &GCPhys);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Log(("Enable VT-x virtual APIC access filtering\n"));
b7cee253391f5ff9d7908b200e6a69f98b63bc2cvboxsync rc2 = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hm.s.vmx.HCPhysApicAccess, X86_PTE_RW | X86_PTE_P);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync { /* We've successfully synced our shadow pages, so let's just continue execution. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub3, y3);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * A genuine pagefault. Forward the trap to the guest by injecting the exception and resuming execution.
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* The error code might have been changed. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Now we must update CR2. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
3689d0733b6efa19676293c493337c8b6948c8c8vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub3, y3);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Log2(("PGMTrap0eHandler failed with %d\n", VBOXSTRICTRC_VAL(rc)));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Need to go back to the recompiler to emulate the instruction. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* If event delivery caused the #PF (shadow or not), tell TRPM. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* old style FPU error reporting needs some extra work. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /** @todo don't fall back to the recompiler, but do it manually. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub3, y3);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * Exit qualification bits:
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * 3:0 B0-B3 which breakpoint condition was met
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * 12:4 Reserved (0)
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * 13 BD - debug register access detected
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * 14 BS - single step execution or branch taken
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * 63:15 Reserved (0)
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Note that we don't support guest and host-initiated debugging at the same time. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), uDR6);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Update DR6 here. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Resync DR6 if the debug state is active. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* X86_DR7_GD will be cleared if DRx accesses should be trapped inside the guest. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Paranoia. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Resync DR7 */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc2 = VMXWriteVmcs64(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Log(("Trap %x (debug) at %RGv exit qualification %RX64 dr6=%x dr7=%x\n", vector, (RTGCPTR)pCtx->rip,
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync exitQualification, (uint32_t)pCtx->dr[6], (uint32_t)pCtx->dr[7]));
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub3, y3);
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync /* Return to ring 3 to deal with the debug exit code. */
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs.Sel, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx));
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync Log(("Guest #BP at %04x:%RGv\n", pCtx->cs.Sel, pCtx->rip));
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub3, y3);
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub3, y3);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs.Sel, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync case X86_XCPT_GP: /* General protection failure exception. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Log(("Trap %x at %04X:%RGv errorCode=%RGv\n", vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, errCode));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub3, y3);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync LogFlow(("Real mode X86_XCPT_GP instruction emulation at %x:%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc2 = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + pDis->cbInstr);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = VMXWriteVmcs(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE,
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync rc2 = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync rc2 = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask));
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* RF cleared when popped in real mode; see pushf description in AMD manual. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc2 = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pDis->fPrefix & (DISPREFIX_OPSIZE | DISPREFIX_ADDRSIZE))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogFlow(("iret to %04x:%x\n", pCtx->cs.Sel, pCtx->ip));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogFlow(("Realmode: INT %x\n", pDis->Param1.uValue & 0xff));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = EMInterpretInstructionDisasState(pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCtx->rip += cbOp; /* Move on to the next instruction. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * LIDT, LGDT can end up here. In the future CRx changes as well. Just reload the
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * whole context to be done with it.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Only resume if successful. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub3, y3);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case X86_XCPT_NP: /* Segment not present exception. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE); break;
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD); break;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS); break;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP); break;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF); break;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub3, y3);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs.Sel, pCtx->eip, errCode));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertRC(VBOXSTRICTRC_VAL(rc)); /* Strict RC check below. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Go back to ring-3 in case of a triple fault. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub3, y3);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync } /* switch (vector) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsgFailed(("Unexpected interruption code %x\n", intInfo));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub3, y3);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * by the configuration of the EPT paging structures.
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc2 = VMXReadVmcs64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Determine the kind of violation. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* If the page is present, then it's a page level protection fault. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Shortcut for APIC TPR reads and writes. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && GCPhys > 0x1000000 /* to skip VGA frame buffer accesses */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Enable VT-x virtual APIC access filtering\n"));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hm.s.vmx.HCPhysApicAccess, X86_PTE_RW | X86_PTE_P);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* GCPhys contains the guest physical address of the page fault. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Handle the pagefault trap for the nested shadow table. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment below, @bugref{6043}.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* We've successfully synced our shadow pages, so let's just continue execution. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogFlow(("PGMTrap0eHandlerNestedPaging at %RGv failed with %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Need to go back to the recompiler to emulate the instruction. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = VMXReadVmcs64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("VMX_EXIT_EPT_MISCONFIG for %RGp\n", GCPhys));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Shortcut for APIC TPR reads and writes. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync && GCPhys > 0x1000000 /* to skip VGA frame buffer accesses */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Enable VT-x virtual APIC access filtering\n"));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc2 = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hm.s.vmx.HCPhysApicAccess, X86_PTE_RW | X86_PTE_P);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, CPUMCTX2CORE(pCtx), GCPhys, UINT32_MAX);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * If we succeed, resume execution.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Or, if fail in interpreting the instruction because we couldn't get the guest physical address
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * of the page containing the instruction via the guest's page tables (we would invalidate the guest page
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * weird case. See @bugref{6043}.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhys, (RTGCPTR)pCtx->rip));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> %Rrc\n", GCPhys, (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Clear VM-exit on IF=1 change. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync goto ResumeExecution; /* we check for pending guest interrupts there */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Skip instruction and continue directly. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Continue execution.*/
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Update EIP and continue execution. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Update EIP and continue execution. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Update EIP and continue execution. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync case VMX_EXIT_RDTSCP: /* 51 Guest software attempted to execute RDTSCP. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Update EIP and continue execution. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync case VMX_EXIT_INVLPG: /* 14 Guest software attempted to execute INVLPG. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), exitQualification);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Update EIP and continue execution. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, VBOXSTRICTRC_VAL(rc)));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pCtx));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Update EIP and continue execution. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: monitor failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync Log(("VMX: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync /* Our patch code uses LSTAR for TPR caching. */
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync /* Skip the instruction and continue. */
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync /* Only resume if successful. */
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_MSR;
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync /* no break */
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync STAM_COUNTER_INC((exitReason == VMX_EXIT_RDMSR) ? &pVCpu->hm.s.StatExitRdmsr : &pVCpu->hm.s.StatExitWrmsr);
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync * Note: The Intel spec. claims there's an REX version of RDMSR that's slightly different,
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync * so we play safe by completely disassembling the instruction.
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
152d786a21a506f9e2a2e16ba8efdc2bcae133abvboxsync rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* EIP has been updated already. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Only resume if successful. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n",
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", VBOXSTRICTRC_VAL(rc)));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExit2Sub2, y2);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_CR3;
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Assert(!pVM->hm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR3;
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR4;
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* CR8 contains the APIC TPR */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Assert(!(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != DISCREG_CR3);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Assert( VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync || !(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Update EIP if no error occurred. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Only resume if successful. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub2, y2);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub2, y2);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Disable DRx move intercepts. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc2 = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Save the host and load the guest debug state. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Log(("VMX_EXIT_DRX_MOVE: write DR%d genreg %d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Log(("VMX_EXIT_DRX_MOVE: read DR%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification)));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync * time and restore DRx registers afterwards */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync Log2(("VMX: mov DRx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Update EIP if no error occurred. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Only resume if successful. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExit2Sub1, y1);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /** @todo necessary to make the distinction? */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4)) /* paranoia */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync rc = fIOWrite ? VINF_IOM_R3_IOPORT_WRITE : VINF_IOM_R3_IOPORT_READ;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub1, y1);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Disassemble manually to deal with segment prefixes. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
dba0e7f8f385de972564b6917e305b8f53ea3480vboxsync /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
4d4628e1fe67e333b01942cc6ac92818832fd0edvboxsync Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
4d4628e1fe67e333b01942cc6ac92818832fd0edvboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4d4628e1fe67e333b01942cc6ac92818832fd0edvboxsync rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->fPrefix, (DISCPUMODE)pDis->uAddrMode, cbSize);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->fPrefix, (DISCPUMODE)pDis->uAddrMode, cbSize);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Normal in/out */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pCtx->rip + cbInstr, uPort, uAndVal, cbSize);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Write back to the EAX register. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pCtx->rip + cbInstr, uPort, uAndVal, cbSize);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Handled the I/O return codes.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
23631945c9cb3df68ca51c69ed0b77e90164b402vboxsync /* Update EIP and continue execution. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync for (unsigned i = 0; i < 4; i++)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Clear all breakpoint status flags and set the one we just hit. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Note: AMD64 Architecture Programmer's Manual 13.1:
c7b0001a9846d83269a0a71ee53736ae2ab6421fvboxsync * Bits 15:13 of the DR6 register is never cleared by the processor and must
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * be cleared by software after the contents have been read.
c7ff622115966b69b482bd2896662e40d823b22fvboxsync /* X86_DR7_GD will be cleared if DRx accesses should be trapped inside the guest. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Paranoia. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Resync DR7 */
6da7ae3144a7be1443dd37052b24370bf210fda1vboxsync rc2 = VMXWriteVmcs64(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
6da7ae3144a7be1443dd37052b24370bf210fda1vboxsync /* Construct inject info. */
6da7ae3144a7be1443dd37052b24370bf210fda1vboxsync intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
6da7ae3144a7be1443dd37052b24370bf210fda1vboxsync intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
6da7ae3144a7be1443dd37052b24370bf210fda1vboxsync Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
6da7ae3144a7be1443dd37052b24370bf210fda1vboxsync rc2 = hmR0VmxInjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo),
6da7ae3144a7be1443dd37052b24370bf210fda1vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub1, y1);
6da7ae3144a7be1443dd37052b24370bf210fda1vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub1, y1);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub1, y1);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rc)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2Sub1, y1);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync on the APIC-access page. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync unsigned uAccessType = VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(exitQualification);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(exitQualification);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = IOMMMIOPhysHandler(pVM, (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* The rest is handled after syncing the entire CPU state. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Note: The guest state is not entirely synced back at this stage!
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Investigate why there was a VM-exit. (part 2) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_EXCEPTION_NMI: /* 0 Exception or non-maskable interrupt (NMI). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_EPT_MISCONFIG: /* 49 EPT misconfig is used by the PGM/MMIO optimizations. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Already handled above. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VINF_EM_RESET; /* Triple fault equals a reset. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_TASK_SWITCH: /* 9 Task switch: too complicated to emulate, so fall back to the recompiler */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync Log(("VMX_EXIT_TASK_SWITCH: exit=%RX64\n", exitQualification));
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync if ( (VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(exitQualification) == VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT)
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync /* Caused by an injected interrupt. */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync Log(("VMX_EXIT_TASK_SWITCH: reassert trap %d\n", VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVCpu->hm.s.Event.intInfo)));
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync Assert(!VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hm.s.Event.intInfo));
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync //@todo: Why do we assume this had to be a hardware interrupt? What about software interrupts or exceptions?
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync rc2 = TRPMAssertTrap(pVCpu, VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVCpu->hm.s.Event.intInfo), TRPM_HARDWARE_INT);
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync /* else Exceptions and software interrupts can just be restarted. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Check if external interrupts are pending; if so, don't switch back. */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
46a78ba0ce1d037aaed54f3df16ebd9c0b70ed39vboxsync /* Update EIP and continue execution. */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync /* Check if external interrupts are pending; if so, don't switch back. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_MTF: /* 37 Exit due to Monitor Trap Flag. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogFlow(("VMX_EXIT_MTF at %RGv\n", (RTGCPTR)pCtx->rip));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.u64ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /** @todo inject #UD immediately */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_INVLPG: /* 14 Guest software attempted to execute INVLPG. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_RDTSCP: /* 51 Guest software attempted to execute RDTSCP. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* already handled above */
a9f41cb889f53e8407561a6155052c441eb0fc5fvboxsync case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync on the APIC-access page. */
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync * If we decided to emulate them here, then we must sync the MSRs that could have been changed (sysenter, FS/GS base)
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val2));
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val2));
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val2));
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val2));
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val2));
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val2));
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync#endif /* VBOX_STRICT */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync /* We now going back to ring-3, so clear the action flag. */
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync * Signal changes for the recompiler.
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync * If we executed vmlaunch/vmresume and an external IRQ was pending, then we don't have to do a full sync the next time.
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync /* On the next entry we'll only sync the host context. */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_HOST_CONTEXT;
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync /* On the next entry we'll sync everything. */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync /** @todo we can do better than this */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync /* Not in the VINF_PGM_CHANGE_MODE though! */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync /* Translate into a less severe return code */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync /* Try to extract more information about what might have gone wrong here. */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync VMXGetActivateVMCS(&pVCpu->hm.s.vmx.lasterror.u64VMCSPhys);
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync pVCpu->hm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hm.s.vmx.pvVMCS;
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync pVCpu->hm.s.vmx.lasterror.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync pVCpu->hm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync /* Just set the correct state here instead of trying to catch every goto above. */
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync /* Restore interrupts if we exited after disabling them. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Enters the VT-x session.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCpu Pointer to the CPU info struct.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync /* Activate the VMCS. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync int rc = VMXActivateVMCS(pVCpu->hm.s.vmx.HCPhysVMCS);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Leaves the VT-x session.
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync * @returns VBox status code.
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync * @param pVM Pointer to the VM.
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync * @param pVCpu Pointer to the VMCPU.
62216cc0be0cc0f0b57b124939d208d0a6007fdfvboxsync * @param pCtx Pointer to the guests CPU context.
62216cc0be0cc0f0b57b124939d208d0a6007fdfvboxsyncVMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
62216cc0be0cc0f0b57b124939d208d0a6007fdfvboxsync Assert(pVCpu->hm.s.vmx.u64ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync * Save the guest debug state if necessary.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Enable DRx move intercepts again. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.u64ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync int rc = VMXWriteVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, pVCpu->hm.s.vmx.u64ProcCtls);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Resync the debug registers the next time. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(pVCpu->hm.s.vmx.u64ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Clear VMCS, marking it inactive, clearing implementation-specific data and writing
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * VMCS data back to memory.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Flush the TLB using EPT.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param enmFlush Type of flush.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic void hmR0VmxFlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH_EPT enmFlush)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync descriptor[1] = 0; /* MBZ. Intel spec. 33.3 VMX Instructions */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(rc == VINF_SUCCESS, ("VMXR0InvEPT %x %RGv failed with %d\n", enmFlush, pVCpu->hm.s.vmx.GCPhysEPTP, rc));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushNestedPaging);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Flush the TLB using VPID.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU (can be NULL depending on @a
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * enmFlush).
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync * @param enmFlush Type of flush.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param GCPtr Virtual address of the page to flush (can be 0 depending
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * on @a enmFlush).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic void hmR0VmxFlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH_VPID enmFlush, RTGCPTR GCPtr)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pVCpu->hm.s.uCurrentAsid != 0, ("VMXR0InvVPID invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pVCpu->hm.s.uCurrentAsid <= UINT16_MAX, ("VMXR0InvVPID invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync int rc = VMXR0InvVPID(enmFlush, &descriptor[0]); NOREF(rc);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ("VMXR0InvVPID %x %x %RGv failed with %d\n", enmFlush, pVCpu ? pVCpu->hm.s.uCurrentAsid : 0, GCPtr, rc));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Invalidates a guest page by guest virtual address. Only relevant for
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * EPT/VPID, otherwise there is nothing really to invalidate.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param GCVirt Guest virtual address of the page to invalidate.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync bool fFlushPending = VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * We must invalidate the guest TLB entry in either case, we cannot ignore it even for the EPT case
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * See @bugref{6043} and @bugref{6177}
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Set the VMCPU_FF_TLB_FLUSH force flag and flush before VMENTRY in hmR0VmxSetupTLB*() as this
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * function maybe called in a loop with individual addresses.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* If we can flush just this page do it, otherwise flush as little as possible. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync hmR0VmxFlushVPID(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, GCVirt);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Invalidates a guest page by physical address. Only relevant for EPT/VPID,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * otherwise there is nothing really to invalidate.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * NOTE: Assumes the current instruction references this physical page though a virtual address!!
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param GCPhys Guest physical address of the page to invalidate.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * We cannot flush a page by guest-physical address. invvpid takes only a linear address
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * while invept only flushes by EPT not individual addresses. We update the force flag here
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * and flush before VMENTRY in hmR0VmxSetupTLB*(). This function might be called in a loop.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Report world switch error and dump some useful debug info.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param rc Return code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Pointer to the current guest CPU context (not updated).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic void hmR0VmxReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc, PCPUMCTX pCtx)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 = VMXReadVmcs(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc2 |= VMXReadVmcs(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.lasterror.ulInstrError = instrError;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pVCpu->hm.s.vmx.lasterror.ulExitReason = exitReason;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXReadVmcs(VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS, &val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync VMXReadVmcs(VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS, &val);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pDesc = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pDesc = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pDesc = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pDesc = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pDesc = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pDesc = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pDesc = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Log(("MSR_K8_KERNEL_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_KERNEL_GS_BASE)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#endif /* VBOX_STRICT */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* impossible */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsgFailed(("%Rrc (%#x)\n", VBOXSTRICTRC_VAL(rc), VBOXSTRICTRC_VAL(rc)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
b8c36c1c1ce39852b741fbb6eca62adb3f15a25evboxsync * Prepares for and executes VMLAUNCH (64 bits guest mode).
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param fResume Whether to vmlauch/vmresume.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Pointer to the guest CPU context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCache Pointer to the VMCS cache.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncDECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCache->pSwitcher = (uint64_t)pVM->hm.s.pfnHost32ToGuest64R0;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync aParam[0] = (uint32_t)(HCPhysCpuPage); /* Param 1: VMXON physical address - Lo. */
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsync aParam[1] = (uint32_t)(HCPhysCpuPage >> 32); /* Param 1: VMXON physical address - Hi. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync aParam[2] = (uint32_t)(pVCpu->hm.s.vmx.HCPhysVMCS); /* Param 2: VMCS physical address - Lo. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync aParam[3] = (uint32_t)(pVCpu->hm.s.vmx.HCPhysVMCS >> 32); /* Param 2: VMCS physical address - Hi. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 1;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(*(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) == 5);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 0xff;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pCache->TestIn.HCPhysCpuPage== HCPhysCpuPage, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysCpuPage, HCPhysCpuPage));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pCache->TestIn.HCPhysVMCS == pVCpu->hm.s.vmx.HCPhysVMCS, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVMCS,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pCache->TestIn.HCPhysVMCS == pCache->TestOut.HCPhysVMCS, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVMCS,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache),
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache)));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx,
4946f90c5c7016131555f0c925091d4ede6bdde0vboxsyncstatic bool hmR0VmxIsValidReadField(uint32_t idxField)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return true;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncstatic bool hmR0VmxIsValidWriteField(uint32_t idxField)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return true;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync return false;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync# endif /* VBOX_STRICT */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Executes the specified handler in 64-bit mode.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVM Pointer to the VM.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pVCpu Pointer to the VMCPU.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pCtx Pointer to the guest CPU context.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param pfnHandler Pointer to the RC handler function.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param cbParam Number of parameters.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @param paParam Array of 32-bit parameters.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsyncVMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VMCSCache.Write.aField));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(pVCpu->hm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VMCSCache.Read.aField));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync for (unsigned i=0;i<pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries;i++)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(hmR0VmxIsValidWriteField(pVCpu->hm.s.vmx.VMCSCache.Write.aField[i]));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync for (unsigned i=0;i<pVCpu->hm.s.vmx.VMCSCache.Read.cValidEntries;i++)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync Assert(hmR0VmxIsValidReadField(pVCpu->hm.s.vmx.VMCSCache.Read.aField[i]));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Disable interrupts. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Clear VMCS. Marking it inactive, clearing implementation-specific data and writing VMCS data back to memory. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Leave VMX Root Mode. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Call switcher. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Make sure the VMX instructions don't cause #UD faults. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Enter VMX Root Mode */
f27e44a5e1633e2fb4c44f962a2c503c451c1418vboxsync#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
c1e8287e038e789c1eefcee00a2e63258ca22d48vboxsync * Executes VMWRITE.
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * @returns VBox status code
f27e44a5e1633e2fb4c44f962a2c503c451c1418vboxsync * @param pVCpu Pointer to the VMCPU.
f27e44a5e1633e2fb4c44f962a2c503c451c1418vboxsync * @param idxField VMCS field index.
f27e44a5e1633e2fb4c44f962a2c503c451c1418vboxsync * @param u64Val 16, 32 or 64 bits value.
f27e44a5e1633e2fb4c44f962a2c503c451c1418vboxsyncVMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
f27e44a5e1633e2fb4c44f962a2c503c451c1418vboxsync /* These fields consist of two parts, which are both writable in 32 bits mode. */
f27e44a5e1633e2fb4c44f962a2c503c451c1418vboxsync rc |= VMXWriteVmcs32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync rc = VMXWriteCachedVmcsEx(pVCpu, idxField, u64Val);
b28326220af580dde4a61f15930f51fe584dc896vboxsync AssertMsgFailed(("Unexpected field %x\n", idxField));
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync * Cache VMCS writes for running 64 bits guests on 32 bits hosts.
b28326220af580dde4a61f15930f51fe584dc896vboxsync * @param pVCpu Pointer to the VMCPU.
b28326220af580dde4a61f15930f51fe584dc896vboxsync * @param idxField VMCS field index.
b28326220af580dde4a61f15930f51fe584dc896vboxsync * @param u64Val 16, 32 or 64 bits value.
b28326220af580dde4a61f15930f51fe584dc896vboxsyncVMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
b28326220af580dde4a61f15930f51fe584dc896vboxsync AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1,
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync /* Make sure there are no duplicates. */
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync for (unsigned i = 0; i < pCache->Write.cValidEntries; i++)
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
f687f34bd232be13744edbc0cc5155fa5d4540edvboxsync pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
9dca051a5f8ff457ef1692990f6ecfa280daf265vboxsync#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_HYBRID_32BIT_KERNEL */