HWSVMR0.cpp revision efeeb32d6a72bbaa4742a7cf07f6526365bf20f4
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * HM SVM (AMD-V) - Host Context Ring-0.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * Copyright (C) 2006-2013 Oracle Corporation
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * available from http://www.virtualbox.org. This file is free software;
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * you can redistribute it and/or modify it under the terms of the GNU
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * General Public License (GPL) as published by the Free Software
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync/*******************************************************************************
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync* Header Files *
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync*******************************************************************************/
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync/*******************************************************************************
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync* Internal Functions *
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync*******************************************************************************/
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsyncstatic int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsyncstatic int hmR0SvmEmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsyncstatic void hmR0SvmSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync/*******************************************************************************
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync* Defined Constants And Macros *
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync*******************************************************************************/
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync/** Convert hidden selector attribute word between VMX and SVM formats. */
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync#define SVM_HIDSEGATTR_VMX2SVM(a) (a & 0xFF) | ((a & 0xF000) >> 4)
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync#define SVM_HIDSEGATTR_SVM2VMX(a) (a & 0xFF) | ((a & 0x0F00) << 4)
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync pVmcb->guest.REG.u16Attr = SVM_HIDSEGATTR_VMX2SVM(pCtx->reg.Attr.u); \
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync } while (0)
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync pCtx->reg.Attr.u = SVM_HIDSEGATTR_SVM2VMX(pVmcb->guest.REG.u16Attr); \
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync } while (0)
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync/*******************************************************************************
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync* Global Variables *
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync*******************************************************************************/
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync/* IO operation lookup arrays. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsyncstatic uint32_t const g_aIOSize[8] = {0, 1, 2, 0, 4, 0, 0, 0};
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsyncstatic uint32_t const g_aIOOpAnd[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * Sets up and activates AMD-V on the current CPU.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @returns VBox status code.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @param pCpu Pointer to the CPU info struct.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @param pVM Pointer to the VM (can be NULL after a resume!).
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @param pvCpuPage Pointer to the global CPU page.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @param HCPhysCpuPage Physical address of the global CPU page.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsyncVMMR0DECL(int) SVMR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * We must turn on AMD-V and setup the host state physical address, as those MSRs are per cpu/core.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V.
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Turn on AMD-V in the EFER MSR. */
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync /* Write the physical page address where the CPU will store the host state while executing the VM. */
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * to flush the TLB with before using a new ASID.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * Deactivates AMD-V on the current CPU.
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * @returns VBox status code.
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * @param pCpu Pointer to the CPU info struct.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * @param pvCpuPage Pointer to the global CPU page.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * @param HCPhysCpuPage Physical address of the global CPU page.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsyncVMMR0DECL(int) SVMR0DisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync /* Turn off AMD-V in the EFER MSR. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Invalidate host state physical address. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * Does global AMD-V initialization (called during module initialization).
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @returns VBox status code.
9523921c89c66f4bececdbd5ac95aed0039eda1bvboxsync * Does global VT-x termination (called during module termination).
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync * Does Ring-0 per VM AMD-V init.
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync * @returns VBox status code.
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync * @param pVM Pointer to the VM.
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync rc = RTR0MemObjAllocCont(&pVM->hm.s.svm.hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync pVM->hm.s.svm.pvIOBitmap = RTR0MemObjAddress(pVM->hm.s.svm.hMemObjIOBitmap);
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync pVM->hm.s.svm.HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(pVM->hm.s.svm.hMemObjIOBitmap, 0);
ed9d3db07648c7e3a979105c15ad752ee9ea18devboxsync /* Set all bits to intercept all IO accesses. */
ed9d3db07648c7e3a979105c15ad752ee9ea18devboxsync ASMMemFill32(pVM->hm.s.svm.pvIOBitmap, 3 << PAGE_SHIFT, 0xffffffff);
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
9523921c89c66f4bececdbd5ac95aed0039eda1bvboxsync Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Allocate VMCBs for all guest CPUs. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Allocate one page for the host context */
06ea6bcf23874b662d499b3f130024c98b2dd7a6vboxsync rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Allocate one page for the VM control block (VMCB). */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
5f2b03bf7695dabd71222dba123532a3f76828c1vboxsync pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0);
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync /* Set all bits to intercept all MSR accesses. */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
5f2b03bf7695dabd71222dba123532a3f76828c1vboxsync * Does Ring-0 per VM AMD-V termination.
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync * @returns VBox status code.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @param pVM Pointer to the VM.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync if (pVM->hm.s.svm.hMemObjIOBitmap != NIL_RTR0MEMOBJ)
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync RTR0MemObjFree(pVM->hm.s.svm.hMemObjIOBitmap, false);
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * Sets up AMD-V for the specified VM.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * @returns VBox status code.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * @param pVM Pointer to the VM.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * Program the control fields. Most of them never have to be changed again.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * CR0/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * Note: CR0 & CR4 can be safely read when guest and shadow copies are identical.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* CR0/4 writes must be intercepted for obvious reasons. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4);
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync /* Intercept all DRx reads and writes by default. Changed later on. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Intercept traps; only #NM is always intercepted. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync pVmcb->ctrl.u32InterceptException = RT_BIT(X86_XCPT_NM);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync pVmcb->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_PF);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync pVmcb->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_BP)
7e8ef90d3160234df0f254131b87af4243d79476vboxsync /* Set up instruction and miscellaneous intercepts. */
7e8ef90d3160234df0f254131b87af4243d79476vboxsync pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
06ea6bcf23874b662d499b3f130024c98b2dd7a6vboxsync | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync guest (host thinks the cpu load is high) */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync Log(("pVmcb->ctrl.u32InterceptException = %x\n", pVmcb->ctrl.u32InterceptException));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("pVmcb->ctrl.u32InterceptCtrl1 = %x\n", pVmcb->ctrl.u32InterceptCtrl1));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("pVmcb->ctrl.u32InterceptCtrl2 = %x\n", pVmcb->ctrl.u32InterceptCtrl2));
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync /* Ignore the priority in the TPR; just deliver it when we tell it to. */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync /* Set IO and MSR bitmap addresses. */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync pVmcb->ctrl.u64IOPMPhysAddr = pVM->hm.s.svm.HCPhysIOBitmap;
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* No LBR virtualization. */
1cd59fdf671ca60c64d77e3f7046aaecf7003824vboxsync /* The ASID must start at 1; the host uses 0. */
1cd59fdf671ca60c64d77e3f7046aaecf7003824vboxsync * Setup the PAT MSR (nested paging only)
1cd59fdf671ca60c64d77e3f7046aaecf7003824vboxsync * The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
1cd59fdf671ca60c64d77e3f7046aaecf7003824vboxsync * so choose type 6 for all PAT slots.
1cd59fdf671ca60c64d77e3f7046aaecf7003824vboxsync /* If nested paging is not in use, additional intercepts have to be set up. */
1cd59fdf671ca60c64d77e3f7046aaecf7003824vboxsync /* CR3 reads/writes must be intercepted; our shadow values are different from guest's. */
1cd59fdf671ca60c64d77e3f7046aaecf7003824vboxsync * We must also intercept:
1cd59fdf671ca60c64d77e3f7046aaecf7003824vboxsync * - INVLPG (must go through shadow paging)
1cd59fdf671ca60c64d77e3f7046aaecf7003824vboxsync * - task switches (may change CR3/EFLAGS/LDT)
1cd59fdf671ca60c64d77e3f7046aaecf7003824vboxsync pVmcb->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_INVLPG
1cd59fdf671ca60c64d77e3f7046aaecf7003824vboxsync /* Page faults must be intercepted to implement shadow paging. */
1cd59fdf671ca60c64d77e3f7046aaecf7003824vboxsync pVmcb->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_PF);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * to modify them directly.
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync hmR0SvmSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync hmR0SvmSetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync hmR0SvmSetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync hmR0SvmSetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync hmR0SvmSetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync hmR0SvmSetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync hmR0SvmSetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync hmR0SvmSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync hmR0SvmSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync hmR0SvmSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * Sets the permission bits for the specified MSR.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @param pVCpu Pointer to the VMCPU.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @param ulMSR MSR value.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @param fRead Whether reading is allowed.
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync * @param fWrite Whether writing is allowed.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsyncstatic void hmR0SvmSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync uint8_t *pvMsrBitmap = (uint8_t *)pVCpu->hm.s.svm.pvMsrBitmap;
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Pentium-compatible MSRs */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync /* AMD Seventh and Eighth Generation Processor MSRs */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * Posts a pending event (trap or external interrupt). An injected event should only
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * be written to the VMCB immediately before VMRUN, otherwise we might have stale events
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * injected across VM resets and suchlike. See @bugref{6220}.
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * @param pVCpu Pointer to the VMCPU.
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * @param pCtx Pointer to the guest CPU context.
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * @param pIntInfo Pointer to the SVM interrupt info.
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsyncDECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, SVMEVENT *pEvent)
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync Log(("SVM: Set pending event: intInfo=%016llx\n", pEvent->u));
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* If there's an event pending already, we're in trouble... */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Set pending event state. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * Injects an event (trap or external interrupt).
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * @param pVCpu Pointer to the VMCPU.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * @param pVmcb Pointer to the VMCB.
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * @param pCtx Pointer to the guest CPU context.
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * @param pIntInfo Pointer to the SVM interrupt info.
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsyncDECLINLINE(void) hmR0SvmInjectEvent(PVMCPU pVCpu, PSVMVMCB pVmcb, CPUMCTX *pCtx, SVMEVENT *pEvent)
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector,
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->u));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Set event injection state. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * Checks for pending guest interrupts and injects them.
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync * @returns VBox status code.
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync * @param pVM Pointer to the VM.
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync * @param pVCpu Pointer to the VMCPU.
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync * @param pVmcb Pointer to the VMCB.
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync * @param pCtx Pointer to the guest CPU Context.
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsyncstatic int hmR0SvmCheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, PSVMVMCB pVmcb, CPUMCTX *pCtx)
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync * Dispatch any pending interrupts (injected before, but a VM-exit occurred prematurely).
5f2b03bf7695dabd71222dba123532a3f76828c1vboxsync Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hm.s.Event.u64IntrInfo, pVCpu->hm.s.Event.u32ErrCode,
b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync * If an active trap is already pending, we must forward it first!
5366e994777f9d9391cf809dc77610f57270d75dvboxsync if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync /** @todo SMI interrupts. */
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync * When external interrupts are pending, we should exit the VM when IF is set.
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n",
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /** @todo Use virtual interrupt method to inject a pending IRQ; dispatched as
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync * soon as guest.IF is set. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync pVmcb->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync /* Just continue */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, NULL, NULL, NULL);
ca3db470494a8b6eaec69ea37468a5cda65e2da8vboxsync && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* If a new event is pending, then dispatch it now. */
ca3db470494a8b6eaec69ea37468a5cda65e2da8vboxsync rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, NULL, NULL);
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* Clear the pending trap. */
8bc8d66f188d5357155b8340e2d489573be2b607vboxsync /* Valid error codes. */
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync } /* if (interrupts can be dispatched) */
8bc8d66f188d5357155b8340e2d489573be2b607vboxsync * Save the host state.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * @returns VBox status code.
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync * @param pVM Pointer to the VM.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * @param pVCpu Pointer to the VMCPU.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsyncVMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync /* Nothing to do here. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * Loads the guest state.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * NOTE: Don't do anything here that can cause a jump back to ring-3!!!
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * @returns VBox status code.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * @param pVM Pointer to the VM.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * @param pVCpu Pointer to the VMCPU.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * @param pCtx Pointer to the guest CPU context.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsyncVMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Setup AMD SVM. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync /* Guest CPU context: LDTR. */
cc1ef2ef9bbc6a0ff964928d61b7298e5bfcce5fvboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync /* Guest CPU context: TR. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Guest CPU context: GDTR. */
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync /* Guest CPU context: IDTR. */
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * Sysenter MSRs (unconditional)
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Control registers */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync /* Always use #NM exceptions to load the FPU/XMM state on demand. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /** @todo check if we support the old style mess correctly. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync pVmcb->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Always enable caching. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * Note: In nested paging mode, the guest is allowed to run with paging disabled; the guest-physical to host-physical
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * translation will remain active.
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync val |= X86_CR0_WP; /* Must set this as we rely on protecting various pages and supervisor writes must be caught. */
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync /* CR2 as well */
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Save our shadow CR3 register. */
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync Assert(pVmcb->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync case PGMMODE_PROTECTED: /* Protected mode, no paging. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /** Must use PAE paging as we could use physical memory > 4 GB */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync default: /* shut up gcc */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Debug registers. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG)
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Sync the hypervisor debug state now if any breakpoint is armed. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Save the host and load the hypervisor debug state. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* DRx intercepts remain enabled. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Override dr6 & dr7 with the hypervisor values. */
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync /* Sync the debug state now if any breakpoint is armed. */
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Disable drx move intercepts. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Save the host and load the guest debug state. */
d8e12fa5dd1c35282b98cb165e42b6b395cf971bvboxsync int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
d8e12fa5dd1c35282b98cb165e42b6b395cf971bvboxsync /* EIP, ESP and EFLAGS */
d8e12fa5dd1c35282b98cb165e42b6b395cf971bvboxsync /* Set CPL */
d8e12fa5dd1c35282b98cb165e42b6b395cf971bvboxsync /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* vmrun will fail without MSR_K6_EFER_SVME. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync pVmcb->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
5366e994777f9d9391cf809dc77610f57270d75dvboxsync /* 64 bits guest mode? */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync /* Unconditionally update these as wrmsr might have changed them. (HM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync /* TSC offset. */
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync if (TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset))
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync if (u64CurTSC + pVmcb->ctrl.u64TSCOffset > TMCpuTickGetLastSeen(pVCpu))
3ff8aa7d3c74cfbe8da5f77b8ea6c748cc79213avboxsync pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
5366e994777f9d9391cf809dc77610f57270d75dvboxsync pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
e378dfdadd62aadc0a012c9953322d979d7606e6vboxsync /* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
e378dfdadd62aadc0a012c9953322d979d7606e6vboxsync LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC,
e378dfdadd62aadc0a012c9953322d979d7606e6vboxsync pVmcb->ctrl.u64TSCOffset, u64CurTSC + pVmcb->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu),
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVmcb->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync pVmcb->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync pVmcb->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
e378dfdadd62aadc0a012c9953322d979d7606e6vboxsync pVmcb->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync pVmcb->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* Sync the various MSRs for 64-bit mode. */
e378dfdadd62aadc0a012c9953322d979d7606e6vboxsync pVmcb->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
e378dfdadd62aadc0a012c9953322d979d7606e6vboxsync pVmcb->guest.u64LSTAR = pCtx->msrLSTAR; /* 64-bit mode syscall rip */
e378dfdadd62aadc0a012c9953322d979d7606e6vboxsync pVmcb->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync pVmcb->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* SWAPGS exchange value */
b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync /* Intercept X86_XCPT_DB if stepping is enabled */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync pVmcb->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
e378dfdadd62aadc0a012c9953322d979d7606e6vboxsync pVmcb->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
5f2b03bf7695dabd71222dba123532a3f76828c1vboxsync /* Done. */
5f2b03bf7695dabd71222dba123532a3f76828c1vboxsync pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_ALL_GUEST;
40c1a23e86c79b24a917a43c186b2e54504d12c1vboxsync * Setup TLB for ASID.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * @param pVM Pointer to the VM.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * @param pVCpu Pointer to the VMCPU.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * This can happen both for start & resume due to long jumps back to ring-3.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * so we cannot reuse the ASIDs without flushing.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync bool fNewAsid = false;
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * Set TLB flush state as checked until we return from the world switch.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * Check for TLB shootdown flushes.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync pCpu->uCurrentAsid = 1; /* start at 1; host uses 0 */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * not be executed. See hmQueueInvlPage() where it is commented
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * out. Support individual entry flushing someday. */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync /* Update VMCB with the ASID. */
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync ("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync ("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync || pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * Runs guest code in an AMD-V VM.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * @returns VBox status code.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * @param pVM Pointer to the VM.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * @param pVCpu Pointer to the VMCPU.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * @param pCtx Pointer to the guest CPU context.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsyncVMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync bool fSyncTPR = false;
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync unsigned cResume = 0;
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync uint8_t u8LastTPR = 0; /* Initialized for potentially stupid compilers. */
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * We can jump to this point to resume execution after determining that a VM-exit is innocent.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if (!STAM_PROFILE_ADV_IS_RUNNING(&pVCpu->hm.s.StatEntry))
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit2, &pVCpu->hm.s.StatEntry, x);
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * Safety precaution; looping for too long here can have a very bad effect on the host.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if (RT_UNLIKELY(++cResume > pVM->hm.s.cMaxResumeLoops))
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * Check for IRQ inhibition due to instruction fusing (sti, mov ss).
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync /* Irq inhibition is no longer active; clear the corresponding SVM state. */
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync /* Irq inhibition is no longer active; clear the corresponding SVM state. */
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync * Check for pending actions that force us to go back to ring-3.
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync if ( VM_FF_ISPENDING(pVM, VM_FF_HM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync /* Check if a sync operation is pending. */
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("Pending pool sync is forcing us back to ring 3; rc=%d\n", VBOXSTRICTRC_VAL(rc)));
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync /* Intercept X86_XCPT_DB if stepping is enabled */
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync /* Check if a pgm pool flush is in progress. */
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync if (VM_FF_ISPENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync /* Check if DMA work is pending (2nd+ run). */
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync if (VM_FF_ISPENDING(pVM, VM_FF_PDM_DMA) && cResume > 1)
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * Exit to ring-3 preemption/work is pending.
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync * Interrupts are disabled before the call to make sure we don't miss any interrupt
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * further down, but hmR0SvmCheckPendingInterrupt makes that impossible.)
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * shootdowns rely on this.
5366e994777f9d9391cf809dc77610f57270d75dvboxsync * When external interrupts are pending, we should exit the VM when IF is set.
5366e994777f9d9391cf809dc77610f57270d75dvboxsync * Note: *After* VM_FF_INHIBIT_INTERRUPTS check!!
5366e994777f9d9391cf809dc77610f57270d75dvboxsync rc = hmR0SvmCheckPendingInterrupt(pVM, pVCpu, pVmcb, pCtx);
5366e994777f9d9391cf809dc77610f57270d75dvboxsync * TPR caching using CR8 is only available in 64-bit mode or with 32-bit guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync * supported.
cc1ef2ef9bbc6a0ff964928d61b7298e5bfcce5fvboxsync * Note: we can't do this in LoddGuestState as PDMApicGetTPR can jump back to ring 3 (lock)! (no longer true)
5366e994777f9d9391cf809dc77610f57270d75dvboxsync /** @todo query and update the TPR only when it could have been changed (mmio access)
5366e994777f9d9391cf809dc77610f57270d75dvboxsync /* TPR caching in CR8 */
5366e994777f9d9391cf809dc77610f57270d75dvboxsync rc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending, NULL /* pu8PendingIrq */);
5366e994777f9d9391cf809dc77610f57270d75dvboxsync /* Our patch code uses LSTAR for TPR caching. */
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync /* A TPR change could activate a pending interrupt, so catch lstar writes. */
ed9d3db07648c7e3a979105c15ad752ee9ea18devboxsync hmR0SvmSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
7e8ef90d3160234df0f254131b87af4243d79476vboxsync * No interrupts are pending, so we don't need to be explicitely notified.
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync * There are enough world switches for detecting pending interrupts.
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync hmR0SvmSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
e2489bd9ef063ae006feaebc3318ffa4143f6e16vboxsync /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
e2489bd9ef063ae006feaebc3318ffa4143f6e16vboxsync /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync * No interrupts are pending, so we don't need to be explicitly notified.
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync * There are enough world switches for detecting pending interrupts.
5f2b03bf7695dabd71222dba123532a3f76828c1vboxsync /* All done! Let's start VM execution. */
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
5f2b03bf7695dabd71222dba123532a3f76828c1vboxsync pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
5f2b03bf7695dabd71222dba123532a3f76828c1vboxsync LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
5f2b03bf7695dabd71222dba123532a3f76828c1vboxsync else if (pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
5f2b03bf7695dabd71222dba123532a3f76828c1vboxsync LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
5f2b03bf7695dabd71222dba123532a3f76828c1vboxsync else if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH))
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
6b9d50a0f466bd5a61458ed53925480ab28a3c17vboxsync * (until the actual world switch)
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync * Load the guest state; *must* be here as it sets up the shadow CR0 for lazy FPU syncing!
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync * Disable interrupts to make sure a poke will interrupt execution.
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync /* Setup TLB control and ASID in the VMCB. */
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync /* In case we execute a goto ResumeExecution later on. */
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync pVCpu->hm.s.fForceTLBFlush = pVM->hm.s.svm.fAlwaysFlushTLB;
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync Assert(pVmcb->ctrl.u64IOPMPhysAddr == pVM->hm.s.svm.HCPhysIOBitmap);
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync Assert(pVmcb->ctrl.u64MSRPMPhysAddr == pVCpu->hm.s.svm.HCPhysMsrBitmap);
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync * Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync * RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync u32HostExtFeatures = pVM->hm.s.cpuid.u32AMDFeatureEDX;
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync if ( (u32HostExtFeatures & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync && !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64GuestTscAux);
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false);
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync /* Possibly the last TSC value seen by the guest (too high) (only when we're in TSC offset mode). */
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync /* Restore host's TSC_AUX. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if (u32HostExtFeatures & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync pVmcb->ctrl.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING-3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Reason for the VM exit */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("ctrl.u16InterceptRdCRx %x\n", pVmcb->ctrl.u16InterceptRdCRx));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("ctrl.u16InterceptWrCRx %x\n", pVmcb->ctrl.u16InterceptWrCRx));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("ctrl.u16InterceptRdDRx %x\n", pVmcb->ctrl.u16InterceptRdDRx));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("ctrl.u16InterceptWrDRx %x\n", pVmcb->ctrl.u16InterceptWrDRx));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("ctrl.u32InterceptException %x\n", pVmcb->ctrl.u32InterceptException));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("ctrl.u32InterceptCtrl1 %x\n", pVmcb->ctrl.u32InterceptCtrl1));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("ctrl.u32InterceptCtrl2 %x\n", pVmcb->ctrl.u32InterceptCtrl2));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.u64TSCOffset %RX64\n", pVmcb->ctrl.u64TSCOffset));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.TLBCtrl.u32ASID %x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.TLBCtrl.u8TLBFlush %x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.IntCtrl.u8VTPR %x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.IntCtrl.u7Reserved %x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.IntCtrl.u3Reserved %x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.IntCtrl.u6Reserved %x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.IntCtrl.u24Reserved %x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.u64IntShadow %RX64\n", pVmcb->ctrl.u64IntShadow));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.u64ExitCode %RX64\n", pVmcb->ctrl.u64ExitCode));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.u64ExitInfo1 %RX64\n", pVmcb->ctrl.u64ExitInfo1));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.u64ExitInfo2 %RX64\n", pVmcb->ctrl.u64ExitInfo2));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.ExitIntInfo.u3Type %x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.NestedPaging %RX64\n", pVmcb->ctrl.NestedPaging.u));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.EventInject.u8Vector %x\n", pVmcb->ctrl.EventInject.n.u8Vector));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.EventInject.u3Type %x\n", pVmcb->ctrl.EventInject.n.u3Type));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.EventInject.u19Reserved %x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.EventInject.u1Valid %x\n", pVmcb->ctrl.EventInject.n.u1Valid));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.EventInject.u32ErrorCode %x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("ctrl.u64LBRVirt %RX64\n", pVmcb->ctrl.u64LBRVirt));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("guest.CS.u16Sel %04X\n", pVmcb->guest.CS.u16Sel));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("guest.CS.u16Attr %04X\n", pVmcb->guest.CS.u16Attr));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("guest.CS.u32Limit %X\n", pVmcb->guest.CS.u32Limit));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("guest.CS.u64Base %RX64\n", pVmcb->guest.CS.u64Base));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("guest.DS.u16Sel %04X\n", pVmcb->guest.DS.u16Sel));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("guest.DS.u16Attr %04X\n", pVmcb->guest.DS.u16Attr));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("guest.DS.u32Limit %X\n", pVmcb->guest.DS.u32Limit));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("guest.DS.u64Base %RX64\n", pVmcb->guest.DS.u64Base));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("guest.ES.u16Sel %04X\n", pVmcb->guest.ES.u16Sel));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Log(("guest.ES.u16Attr %04X\n", pVmcb->guest.ES.u16Attr));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Log(("guest.ES.u32Limit %X\n", pVmcb->guest.ES.u32Limit));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Log(("guest.ES.u64Base %RX64\n", pVmcb->guest.ES.u64Base));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Log(("guest.FS.u16Sel %04X\n", pVmcb->guest.FS.u16Sel));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Log(("guest.FS.u16Attr %04X\n", pVmcb->guest.FS.u16Attr));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Log(("guest.FS.u32Limit %X\n", pVmcb->guest.FS.u32Limit));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Log(("guest.FS.u64Base %RX64\n", pVmcb->guest.FS.u64Base));
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync Log(("guest.GS.u16Sel %04X\n", pVmcb->guest.GS.u16Sel));
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync Log(("guest.GS.u16Attr %04X\n", pVmcb->guest.GS.u16Attr));
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync Log(("guest.GS.u32Limit %X\n", pVmcb->guest.GS.u32Limit));
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync Log(("guest.GS.u64Base %RX64\n", pVmcb->guest.GS.u64Base));
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync Log(("guest.GDTR.u32Limit %X\n", pVmcb->guest.GDTR.u32Limit));
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync Log(("guest.GDTR.u64Base %RX64\n", pVmcb->guest.GDTR.u64Base));
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync Log(("guest.LDTR.u16Sel %04X\n", pVmcb->guest.LDTR.u16Sel));
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync Log(("guest.LDTR.u16Attr %04X\n", pVmcb->guest.LDTR.u16Attr));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Log(("guest.LDTR.u32Limit %X\n", pVmcb->guest.LDTR.u32Limit));
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync Log(("guest.LDTR.u64Base %RX64\n", pVmcb->guest.LDTR.u64Base));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Log(("guest.IDTR.u32Limit %X\n", pVmcb->guest.IDTR.u32Limit));
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync Log(("guest.IDTR.u64Base %RX64\n", pVmcb->guest.IDTR.u64Base));
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync Log(("guest.TR.u16Sel %04X\n", pVmcb->guest.TR.u16Sel));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Log(("guest.TR.u16Attr %04X\n", pVmcb->guest.TR.u16Attr));
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync Log(("guest.TR.u32Limit %X\n", pVmcb->guest.TR.u32Limit));
88cc9bf61296bc5526344415167bb2625ae1dd99vboxsync Log(("guest.TR.u64Base %RX64\n", pVmcb->guest.TR.u64Base));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Log(("guest.u64CR0 %RX64\n", pVmcb->guest.u64CR0));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Log(("guest.u64CR2 %RX64\n", pVmcb->guest.u64CR2));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Log(("guest.u64CR3 %RX64\n", pVmcb->guest.u64CR3));
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync Log(("guest.u64CR4 %RX64\n", pVmcb->guest.u64CR4));
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync Log(("guest.u64DR6 %RX64\n", pVmcb->guest.u64DR6));
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync Log(("guest.u64DR7 %RX64\n", pVmcb->guest.u64DR7));
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync Log(("guest.u64RIP %RX64\n", pVmcb->guest.u64RIP));
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync Log(("guest.u64RSP %RX64\n", pVmcb->guest.u64RSP));
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync Log(("guest.u64RAX %RX64\n", pVmcb->guest.u64RAX));
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync Log(("guest.u64RFlags %RX64\n", pVmcb->guest.u64RFlags));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("guest.u64SysEnterCS %RX64\n", pVmcb->guest.u64SysEnterCS));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("guest.u64SysEnterEIP %RX64\n", pVmcb->guest.u64SysEnterEIP));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("guest.u64SysEnterESP %RX64\n", pVmcb->guest.u64SysEnterESP));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Log(("guest.u64EFER %RX64\n", pVmcb->guest.u64EFER));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("guest.u64STAR %RX64\n", pVmcb->guest.u64STAR));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("guest.u64LSTAR %RX64\n", pVmcb->guest.u64LSTAR));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("guest.u64CSTAR %RX64\n", pVmcb->guest.u64CSTAR));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync Log(("guest.u64SFMASK %RX64\n", pVmcb->guest.u64SFMASK));
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync Log(("guest.u64KernelGSBase %RX64\n", pVmcb->guest.u64KernelGSBase));
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync Log(("guest.u64GPAT %RX64\n", pVmcb->guest.u64GPAT));
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync Log(("guest.u64DBGCTL %RX64\n", pVmcb->guest.u64DBGCTL));
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync Log(("guest.u64BR_FROM %RX64\n", pVmcb->guest.u64BR_FROM));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("guest.u64BR_TO %RX64\n", pVmcb->guest.u64BR_TO));
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync Log(("guest.u64LASTEXCPFROM %RX64\n", pVmcb->guest.u64LASTEXCPFROM));
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync Log(("guest.u64LASTEXCPTO %RX64\n", pVmcb->guest.u64LASTEXCPTO));
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync /* Let's first sync back EIP, ESP, and EFLAGS. */
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync /* eax is saved/restore across the vmrun instruction */
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync * Save all the MSRs that can be changed by the guest without causing a world switch.
f9ce005e61f0fbb51a2cabc53d58c3485151faa9vboxsync * FS & GS base are saved with SVM_READ_SELREG.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync pCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync pCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync pCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync pCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync pCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync /* Can be updated behind our back in the nested paging case. */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * Correct the hidden CS granularity flag. Haven't seen it being wrong in any other
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * register (yet).
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync ("%#x %#x %#llx\n", pCtx->reg.u32Limit, pCtx->reg.Attr.u, pCtx->reg.u64Base))
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * Correct the hidden SS DPL field. It can be wrong on certain CPUs
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * sometimes (seen it on AMD Fusion CPUs with 64-bit guests). The CPU
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * always uses the CPL field in the VMCB instead of the DPL in the hidden
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * SS (chapter AMD spec. 15.5.1 Basic operation).
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * Remaining guest CPU context: TR, IDTR, GDTR, LDTR;
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * must sync everything otherwise we can get out of sync when jumping back to ring-3.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * No reason to sync back the CRx and DRx registers as they cannot be changed by the guest
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * unless in the nested paging case where CR3 can be changed by the guest.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync /* Note! NOW IT'S SAFE FOR LOGGING! */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync /* Take care of instruction fusing (sti, mov ss) (see AMD spec. 15.20.5 Interrupt Shadows) */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync Log(("uInterruptState %x rip=%RGv\n", pVmcb->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync /* Sync back DR6 as it could have been changed by hitting breakpoints. */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync /* Check if an injected event was interrupted prematurely. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync pVCpu->hm.s.Event.u64IntrInfo = pVmcb->ctrl.ExitIntInfo.u;
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* we don't care about 'int xx' as the instruction will be restarted. */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync && pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT)
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hm.s.Event.u64IntrInfo, (RTGCPTR)pCtx->rip, exitCode));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Error code present? (redundant) */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync pVCpu->hm.s.Event.u32ErrCode = pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode;
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Sync back the TPR if it was changed. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Our patch code uses LSTAR for TPR caching. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync if ((uint8_t)(u8LastTPR >> 4) != pVmcb->ctrl.IntCtrl.n.u8VTPR)
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync rc2 = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync RTTraceBufAddMsgF(pVM->CTX_SUFF(hTraceBuf), "vmexit %08x at %04:%08RX64 %RX64 %RX64 %RX64",
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2, pVmcb->ctrl.ExitIntInfo.u);
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, exitCode, pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2,
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Deal with the reason of the VM-exit. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Pending trap. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log2(("Hardware/software interrupt %d\n", vector));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Note that we don't support guest and host-initiated debugging at the same time. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Assert(DBGFIsStepping(pVCpu) || CPUMIsHyperDebugStateActive(pVCpu));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Reinject the exception. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Return to ring 3 to deal with the debug exit code. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs.Sel, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Continue execution. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync uint32_t errCode = pVmcb->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * A genuine pagefault. Forward the trap to the guest by injecting the exception and resuming execution.
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip,
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync /* Now we must update CR2. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync && pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync /* Only attempt to patch the instruction once. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync /* Exit qualification contains the linear address of the page fault. */
d8e12fa5dd1c35282b98cb165e42b6b395cf971bvboxsync /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync /* We've successfully synced our shadow pages, so let's just continue execution. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync * A genuine pagefault. Forward the trap to the guest by injecting the exception and resuming execution.
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync /* The error code might have been changed. */
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync /* Now we must update CR2. */
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync LogFlow(("PGMTrap0eHandler failed with %d\n", VBOXSTRICTRC_VAL(rc)));
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync /* Need to go back to the recompiler to emulate the instruction. */
c99b597540585068d22dde4c9f74730305f24097vboxsync /* old style FPU error reporting needs some extra work. */
c99b597540585068d22dde4c9f74730305f24097vboxsync /** @todo don't fall back to the recompiler, but do it manually. */
c99b597540585068d22dde4c9f74730305f24097vboxsync Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync case X86_XCPT_GP: /* General protection failure exception.*/
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync case X86_XCPT_NP: /* Segment not present exception. */
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
0fd108a555ae02f2fb557d5f2c40281999b60d15vboxsync /** Saves the wrong EIP on the stack (pointing to the int3 instead of the next instruction. */
c99b597540585068d22dde4c9f74730305f24097vboxsync Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
c99b597540585068d22dde4c9f74730305f24097vboxsync Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
c99b597540585068d22dde4c9f74730305f24097vboxsync Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, pCtx->esi));
c99b597540585068d22dde4c9f74730305f24097vboxsync AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
c99b597540585068d22dde4c9f74730305f24097vboxsync } /* switch (vector) */
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync uint32_t errCode = pVmcb->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync RTGCPHYS GCPhysFault = pVmcb->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, GCPhysFault, errCode));
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync || (errCode & (X86_TRAP_PF_P | X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P | X86_TRAP_PF_RSVD) /* mmio optimization */)
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync && pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
5366e994777f9d9391cf809dc77610f57270d75dvboxsync /* Only attempt to patch the instruction once. */
5366e994777f9d9391cf809dc77610f57270d75dvboxsync PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync /* Handle the pagefault trap for the nested shadow table. */
b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync#if HC_ARCH_BITS == 32 /** @todo shadow this in a variable. */
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync /* MMIO optimization */
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync Assert((errCode & (X86_TRAP_PF_RSVD | X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync if ((errCode & (X86_TRAP_PF_RSVD | X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD | X86_TRAP_PF_P))
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync rc = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmShwPagingMode, CPUMCTX2CORE(pCtx), GCPhysFault, errCode);
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync * If we succeed, resume execution.
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync * Or, if fail in interpreting the instruction because we couldn't get the guest physical address
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync * of the page containing the instruction via the guest's page tables (we would invalidate the guest page
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync * in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
35e6d303696e46d969aaf9a59cc381333a483b0bvboxsync * weird case. See @bugref{6043}.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhysFault, (RTGCPTR)pCtx->rip));
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhysFault, (RTGCPTR)pCtx->rip));
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync /* Exit qualification contains the linear address of the page fault. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), GCPhysFault);
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* We've successfully synced our shadow pages, so let's just continue execution. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, GCPhysFault, errCode));
b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", VBOXSTRICTRC_VAL(rc)));
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* Need to go back to the recompiler to emulate the instruction. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* A virtual interrupt is about to be delivered, which means IF=1. */
36f3c24e4ad9c6b813767db1faeabbe7e2ecc057vboxsync Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* External interrupt; leave to allow it to be dispatched again. */
58c0567dee3cc3ebe62dec1e27f8e35bac4ddeb0vboxsync case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Skip instruction and continue directly. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Continue execution.*/
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
58c0567dee3cc3ebe62dec1e27f8e35bac4ddeb0vboxsync Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
58c0567dee3cc3ebe62dec1e27f8e35bac4ddeb0vboxsync rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
58c0567dee3cc3ebe62dec1e27f8e35bac4ddeb0vboxsync /* Update EIP and continue execution. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
58c0567dee3cc3ebe62dec1e27f8e35bac4ddeb0vboxsync rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Update EIP and continue execution. */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Update EIP and continue execution. */
8bc8d66f188d5357155b8340e2d489573be2b607vboxsync case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
8bc8d66f188d5357155b8340e2d489573be2b607vboxsync /* Update EIP and continue execution. */
8bc8d66f188d5357155b8340e2d489573be2b607vboxsync AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
8bc8d66f188d5357155b8340e2d489573be2b607vboxsync case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVLPG. */
8bc8d66f188d5357155b8340e2d489573be2b607vboxsync /* Truly a pita. Why can't SVM give the same information as VT-x? */
8bc8d66f188d5357155b8340e2d489573be2b607vboxsync rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
9523921c89c66f4bececdbd5ac95aed0039eda1bvboxsync case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR3;
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR4;
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* EIP has been updated already. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* Only resume if successful. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* EIP has been updated already. */
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync /* Only resume if successful. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Disable drx move intercepts. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Save the host and load the guest debug state. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync /* EIP has been updated already. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Only resume if successful. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
06ea6bcf23874b662d499b3f130024c98b2dd7a6vboxsync /* Disable DRx move intercepts. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Save the host and load the guest debug state. */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* EIP has been updated already. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Only resume if successful. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo r=ramshankar: would this really fall back to the recompiler and work? */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync /* Disassemble manually to deal with segment prefixes. */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync rc = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync rc = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync /* Normal in/out */
7862f4bd000f1eb6c86289f5ac2849e9cf943ca9vboxsync Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal,
7862f4bd000f1eb6c86289f5ac2849e9cf943ca9vboxsync rc = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port,
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync rc = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, uIOSize);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Write back to the EAX register. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
7862f4bd000f1eb6c86289f5ac2849e9cf943ca9vboxsync Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal,
7862f4bd000f1eb6c86289f5ac2849e9cf943ca9vboxsync HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port,
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * Handled the I/O return codes.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Update EIP and continue execution. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync pCtx->rip = pVmcb->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* IO operation lookup arrays. */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync for (unsigned i = 0; i < 4; i++)
58c0567dee3cc3ebe62dec1e27f8e35bac4ddeb0vboxsync unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
58c0567dee3cc3ebe62dec1e27f8e35bac4ddeb0vboxsync if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
58c0567dee3cc3ebe62dec1e27f8e35bac4ddeb0vboxsync /* Clear all breakpoint status flags and set the one we just hit. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync * Note: AMD64 Architecture Programmer's Manual 13.1:
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync * by software after the contents have been read.
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* Paranoia. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
58c0567dee3cc3ebe62dec1e27f8e35bac4ddeb0vboxsync /* Inject the exception. */
58c0567dee3cc3ebe62dec1e27f8e35bac4ddeb0vboxsync Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
9e17ca2e9d797e845e3284141dd4086a4b817ae5vboxsync Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize,
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rc)));
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* Check if external interrupts are pending; if so, don't switch back. */
5366e994777f9d9391cf809dc77610f57270d75dvboxsync rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
5366e994777f9d9391cf809dc77610f57270d75dvboxsync /* Update EIP and continue execution. */
5366e994777f9d9391cf809dc77610f57270d75dvboxsync pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
5366e994777f9d9391cf809dc77610f57270d75dvboxsync /* Check if external interrupts are pending; if so, don't switch back. */
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pCtx));
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync /* Update EIP and continue execution. */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: monitor failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync /* no break */
5366e994777f9d9391cf809dc77610f57270d75dvboxsync /* Unsupported instructions. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync /* Emulate in ring-3. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync Log(("SVM: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync /* Our patch code uses LSTAR for TPR caching. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* Skip the instruction and continue. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* Only resume if successful. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync * The Intel spec. claims there's an REX version of RDMSR that's slightly different,
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync * so we play safe by completely disassembling the instruction.
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync STAM_COUNTER_INC((pVmcb->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hm.s.StatExitRdmsr : &pVCpu->hm.s.StatExitWrmsr);
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync Log(("SVM: %s\n", (pVmcb->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync /* EIP has been updated already. */
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync /* Only resume if successful. */
4121d226ac899f17e13aff3aff42b603c8b5c1fevboxsync AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVmcb->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr",
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync case SVM_EXIT_TASK_SWITCH: /* too complicated to emulate, so fall back to the recompiler */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync Log(("SVM_EXIT_TASK_SWITCH: exit2=%RX64\n", pVmcb->ctrl.u64ExitInfo2));
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync if ( !(pVmcb->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET | SVM_EXIT2_TASK_SWITCH_JMP))
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync /* Caused by an injected interrupt. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync Log(("SVM_EXIT_TASK_SWITCH: reassert trap %d\n", Event.n.u8Vector));
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync rc2 = TRPMAssertTrap(pVCpu, Event.n.u8Vector, TRPM_HARDWARE_INT);
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* Exceptions and software interrupts can just be restarted. */
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Unexpected exit codes. */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * We are now going back to ring-3, so clear the forced action flag.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * Signal changes to the recompiler.
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync * If we executed vmrun and an external IRQ was pending, then we don't have to do a full sync the next time.
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync /* On the next entry we'll only sync the host context. */
d4a9d525e6f2111d462d2d96462dced6b9ec00efvboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_HOST_CONTEXT;
5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync /* On the next entry we'll sync everything. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /** @todo we can do better than this */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Not in the VINF_PGM_CHANGE_MODE though! */
06ea6bcf23874b662d499b3f130024c98b2dd7a6vboxsync /* Translate into a less severe return code */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Just set the correct state here instead of trying to catch every goto above. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync /* Restore interrupts if we exitted after disabling them. */
5f2b03bf7695dabd71222dba123532a3f76828c1vboxsync * Emulate simple mov tpr instruction.
907b6adfa052386a0666d5557bee9bdbc100c2e5vboxsync * @returns VBox status code.
907b6adfa052386a0666d5557bee9bdbc100c2e5vboxsync * @param pVM Pointer to the VM.
907b6adfa052386a0666d5557bee9bdbc100c2e5vboxsync * @param pVCpu Pointer to the VMCPU.
ed9d3db07648c7e3a979105c15ad752ee9ea18devboxsync * @param pCtx Pointer to the guest CPU context.
45655563f818c5d5bbf4b3d14aa48cbd92a871f1vboxsyncstatic int hmR0SvmEmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
907b6adfa052386a0666d5557bee9bdbc100c2e5vboxsync LogFlow(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
ed9d3db07648c7e3a979105c15ad752ee9ea18devboxsync PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7862f4bd000f1eb6c86289f5ac2849e9cf943ca9vboxsync /* TPR caching in CR8 */
5f2b03bf7695dabd71222dba123532a3f76828c1vboxsync rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
907b6adfa052386a0666d5557bee9bdbc100c2e5vboxsync rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
907b6adfa052386a0666d5557bee9bdbc100c2e5vboxsync /* Fetch the new TPR value */
462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
ed9d3db07648c7e3a979105c15ad752ee9ea18devboxsync AssertMsgFailedReturn(("Unexpected type %d\n", pPatch->enmType), VERR_SVM_UNEXPECTED_PATCH_TYPE);
ed9d3db07648c7e3a979105c15ad752ee9ea18devboxsync * Enters the AMD-V session.
c55bf74b54ecdfb5ebc4e5d90b620d0fee31737evboxsync * @returns VBox status code.
c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync * @param pVM Pointer to the VM.
ed9d3db07648c7e3a979105c15ad752ee9ea18devboxsync * @param pVCpu Pointer to the VMCPU.
ed9d3db07648c7e3a979105c15ad752ee9ea18devboxsync * @param pCpu Pointer to the CPU info struct.
ed9d3db07648c7e3a979105c15ad752ee9ea18devboxsyncVMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
ed9d3db07648c7e3a979105c15ad752ee9ea18devboxsync LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.uCurrentAsid));
ed9d3db07648c7e3a979105c15ad752ee9ea18devboxsync /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_LDTR;
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * Leaves the AMD-V session.
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync * @returns VBox status code.
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync * @param pVM Pointer to the VM.
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync * @param pVCpu Pointer to the VMCPU.
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync * @param pCtx Pointer to the guest CPU context.
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsyncVMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync /* Save the guest debug state if necessary. */
687794577e2e35c3cae67e692a7f2130d1262a82vboxsync CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
ed9d3db07648c7e3a979105c15ad752ee9ea18devboxsync /* Intercept all DRx reads and writes again. Changed later on. */
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /* Resync the debug registers the next time. */
06ea6bcf23874b662d499b3f130024c98b2dd7a6vboxsync pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xFFFF && pVmcb->ctrl.u16InterceptWrDRx == 0xFFFF);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * Worker for Interprets INVLPG.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @return VBox status code.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @param pVCpu Pointer to the VMCPU.
9523921c89c66f4bececdbd5ac95aed0039eda1bvboxsync * @param pCpu Pointer to the CPU info struct.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @param pRegFrame Pointer to the register frame.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsyncstatic int hmR0svmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame)
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, ¶m1, DISQPVWHICH_SRC);
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync if (!(param1.flags & (DISQPV_FLAG_32 | DISQPV_FLAG_64)))
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync /** @todo is addr always a flat linear address or ds based
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * (in absence of segment override prefixes)????
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * Interprets INVLPG.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @returns VBox status code.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @retval VINF_* Scheduling instructions.
9523921c89c66f4bececdbd5ac95aed0039eda1bvboxsync * @retval VERR_EM_INTERPRETER Something we can't cope with.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @retval VERR_* Fatal errors.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @param pVM Pointer to the VM.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * @param pRegFrame Pointer to the register frame.
702a8ee2dc1de96f2f77e97135015d3e243186fdvboxsync * @remarks Updates the EIP if an instruction was executed successfully.
2f3883b126a405f92b19e829472f614c7352b4f9vboxsyncstatic int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
2f3883b126a405f92b19e829472f614c7352b4f9vboxsync * Only allow 32 & 64 bit code.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync if (RT_SUCCESS(rc) && pDis->pCurInstr->uOpcode == OP_INVLPG)
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync rc = hmR0svmInterpretInvlPgEx(pVCpu, pDis, pRegFrame);
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * Invalidates a guest page by guest virtual address.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * @returns VBox status code.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * @param pVM Pointer to the VM.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * @param pVCpu Pointer to the VMCPU.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * @param GCVirt Guest virtual address of the page to invalidate.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsyncVMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB | VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync /* Skip it if a TLB flush is already pending. */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync#if 0 /* obsolete, but left here for clarification. */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * Invalidates a guest page by physical address.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * @returns VBox status code.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * @param pVM Pointer to the VM.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * @param pVCpu Pointer to the VMCPU.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync * @param GCPhys Guest physical address of the page to invalidate.
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsyncVMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgPhys);
9bff17fe6983cfda2ddd98f1979841bcb48e78e7vboxsync#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
int rc;
rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
return rc;