HWSVMR0.cpp revision ee5858e9d955811dae9e6b8ecbb336cc6d0e7197
/* $Id$ */
/** @file
* HWACCM SVM - Host Context Ring 0.
*/
/*
* Copyright (C) 2006-2007 Sun Microsystems, Inc.
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
* Clara, CA 95054 USA or visit http://www.sun.com if you need
* additional information or have any questions.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_HWACCM
#include "HWACCMInternal.h"
#include <VBox/hwacc_svm.h>
#include <VBox/disopcode.h>
#include "HWSVMR0.h"
/**
* Sets up and activates AMD-V on the current CPU
*
* @returns VBox status code.
* @param pCpu CPU info struct
* @param pVM The VM to operate on.
* @param pvPageCpu Pointer to the global cpu page
* @param pPageCpuPhys Physical address of the global cpu page
*/
HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
{
/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
#ifdef LOG_ENABLED
SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
#endif
/* Turn on AMD-V in the EFER MSR. */
if (!(val & MSR_K6_EFER_SVME))
/* Write the physical page address where the CPU will store the host state while executing the VM. */
pCpu->cTLBFlushes = 0;
return VINF_SUCCESS;
}
/**
* Deactivates AMD-V on the current CPU
*
* @returns VBox status code.
* @param pCpu CPU info struct
* @param pvPageCpu Pointer to the global cpu page
* @param pPageCpuPhys Physical address of the global cpu page
*/
{
#ifdef LOG_ENABLED
#endif
/* Turn off AMD-V in the EFER MSR. */
/* Invalidate host state physical address. */
pCpu->uCurrentASID = 0;
return VINF_SUCCESS;
}
/**
* Does Ring-0 per VM AMD-V init.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
int rc;
/* Allocate one page for the VM control block (VMCB). */
rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
if (RT_FAILURE(rc))
return rc;
/* Allocate one page for the host context */
rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
if (RT_FAILURE(rc))
return rc;
/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
if (RT_FAILURE(rc))
return rc;
/* Set all bits to intercept all IO accesses. */
/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
if (RT_FAILURE(rc))
return rc;
pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
/* Set all bits to intercept all MSR accesses. */
/* Erratum 170 which requires a forced TLB flush for each world switch:
*
* All BH-G1/2 and DH-G1/2 models include a fix:
* Athlon X2: 0x6b 1/2
* 0x68 1/2
* Athlon 64: 0x7f 1
* 0x6f 2
* Sempron: 0x7f 1/2
* 0x6f 2
* 0x6c 2
* 0x7c 2
* Turion 64: 0x68 2
*
*/
if ( u32Family == 0xf
{
Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
}
/* Invalidate the last cpu we were running on. */
return VINF_SUCCESS;
}
/**
* Does Ring-0 per VM AMD-V termination.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
{
}
{
}
{
}
{
}
return VINF_SUCCESS;
}
/**
* Sets up AMD-V for the specified VM
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
int rc = VINF_SUCCESS;
/* Program the control fields. Most of them never have to be changed again. */
/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
/* Note: CR8 reads will refer to V_TPR, so no need to catch them. */
/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
else
/*
* CR0/3/4 writes must be intercepted for obvious reasons.
*/
else
/* Intercept all DRx reads and writes. */
pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7);
pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7);
/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
* All breakpoints are automatically cleared when the VM exits.
*/
| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
;
/* With nested paging we don't care about invlpg anymore. */
| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
;
/* Set IO and MSR bitmap addresses. */
/* No LBR virtualization. */
/** The ASID must start at 1; the host uses 0. */
return rc;
}
/**
* Injects an event (trap or external interrupt)
*
* @param pVM The VM to operate on.
* @param pVMCB SVM control block
* @param pCtx CPU Context
* @param pIntInfo SVM interrupt info
*/
{
#ifdef VBOX_STRICT
Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
else
Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
else
{
}
#endif
/* Set event injection state. */
}
/**
* Checks for pending guest interrupts and injects them
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVMCB SVM control block
* @param pCtx CPU Context
*/
{
int rc;
/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
{
Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
return VINF_SUCCESS;
}
/* When external interrupts are pending, we should exit the VM when IF is set. */
if ( !TRPMHasTrap(pVM)
{
{
{
Log(("Enable irq window exit!\n"));
/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
}
}
else
{
if (VBOX_SUCCESS(rc))
{
}
else
{
/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
/* Just continue */
}
}
else
}
#ifdef VBOX_STRICT
if (TRPMHasTrap(pVM))
{
}
#endif
&& TRPMHasTrap(pVM)
)
{
int rc;
/* If a new event is pending, then dispatch it now. */
/* Clear the pending trap. */
{
switch (u8Vector) {
case 8:
case 10:
case 11:
case 12:
case 13:
case 14:
case 17:
/* Valid error codes. */
break;
default:
break;
}
if (u8Vector == X86_XCPT_NMI)
else
}
else
} /* if (interrupts can be dispatched) */
return VINF_SUCCESS;
}
/**
* Loads the guest state
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pCtx Guest context
*/
{
return VERR_INVALID_PARAMETER;
/* Setup AMD SVM. */
/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
{
}
/* Guest CPU context: LDTR. */
{
}
/* Guest CPU context: TR. */
{
}
/* Guest CPU context: GDTR. */
{
}
/* Guest CPU context: IDTR. */
{
}
/*
* Sysenter MSRs
*/
{
}
/* Control registers */
{
if (CPUMIsGuestFPUStateActive(pVM) == false)
{
}
else
{
/** @todo check if we support the old style mess correctly. */
if (!(val & X86_CR0_NE))
{
Log(("Forcing X86_CR0_NE!!!\n"));
/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
{
}
}
val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
}
/* Always enable caching. */
/* Note: WP is not relevant in nested paging mode as we catch accesses on the (host) physical level. */
/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
{
val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
}
}
/* CR2 as well */
{
/* Save our shadow CR3 register. */
{
}
else
}
{
{
{
case PGMMODE_REAL:
case PGMMODE_PROTECTED: /* Protected mode, no paging. */
AssertFailed();
case PGMMODE_32_BIT: /* 32-bit paging. */
break;
case PGMMODE_PAE: /* PAE paging. */
case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
/** @todo use normal 32 bits paging */
val |= X86_CR4_PAE;
break;
case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
AssertFailed();
default: /* shut up gcc */
AssertFailed();
}
}
}
/* Debug registers. */
{
/** @todo DR0-6 */
#ifdef VBOX_STRICT
val = 0x400;
#endif
}
/* EIP, ESP and EFLAGS */
/* Set CPL */
/* vmrun will fail otherwise. */
/** TSC offset. */
else
/** @todo 64 bits stuff (?):
* - STAR
* - LSTAR
* - CSTAR
* - SFMASK
* - KernelGSBase
*/
#ifdef DEBUG
/* Intercept X86_XCPT_DB if stepping is enabled */
if (DBGFIsStepping(pVM))
else
#endif
/* Done. */
return VINF_SUCCESS;
}
/**
* Runs guest code in an SVM VM.
*
* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pCtx Guest context
* @param pCpu CPU info struct
*/
{
int rc = VINF_SUCCESS;
bool fGuestStateSynced = false;
unsigned cResume = 0;
/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
*/
/* Safety precaution; looping for too long here can have a very bad effect on the host */
if (++cResume > HWACCM_MAX_RESUME_LOOPS)
{
goto end;
}
/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
{
Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
{
/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
*/
/* Irq inhibition is no longer active; clear the corresponding SVM state. */
}
}
else
{
/* Irq inhibition is no longer active; clear the corresponding SVM state. */
}
/* Check for pending actions that force us to go back to ring 3. */
#ifdef DEBUG
/* Intercept X86_XCPT_DB if stepping is enabled */
if (!DBGFIsStepping(pVM))
#endif
{
{
goto end;
}
}
/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
{
goto end;
}
/* When external interrupts are pending, we should exit the VM when IF is set. */
/** @note *after* VM_FF_INHIBIT_INTERRUPTS check!!! */
if (VBOX_FAILURE(rc))
{
goto end;
}
/* Load the guest state */
if (rc != VINF_SUCCESS)
{
goto end;
}
fGuestStateSynced = true;
/* All done! Let's start VM execution. */
/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
{
/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
{
/* Force a TLB flush on VM entry. */
}
}
/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
{
{
pCpu->cTLBFlushes++;
}
else
}
else
{
/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
if (!pCpu->uCurrentASID)
}
AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
#ifdef VBOX_WITH_STATISTICS
else
#endif
/* In case we execute a goto ResumeExecution later on. */
| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
));
/**
* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
*/
/* Reason for the VM exit */
{
#ifdef DEBUG
#endif
goto end;
}
/* Let's first sync back eip, esp, and eflags. */
/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
{
}
/** @note NOW IT'S SAFE FOR LOGGING! */
/* Take care of instruction fusing (sti, mov ss) */
{
}
else
/* Check if an injected event was interrupted prematurely. */
&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
{
Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
/* Error code present? (redundant) */
{
}
else
}
/* Deal with the reason of the VM-exit. */
switch (exitCode)
{
case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
{
/* Pending trap. */
switch (vector)
{
#ifdef DEBUG
case X86_XCPT_DB:
break;
#endif
case X86_XCPT_NM:
{
/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
if (rc == VINF_SUCCESS)
{
/* CPUMHandleLazyFPU could have changed CR0; restore it. */
/* Continue execution. */
goto ResumeExecution;
}
Log(("Forward #NM fault to the guest\n"));
goto ResumeExecution;
}
case X86_XCPT_PF: /* Page fault */
{
/* Exit qualification contains the linear address of the page fault. */
/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
if (rc == VINF_SUCCESS)
{ /* We've successfully synced our shadow pages, so let's just continue execution. */
goto ResumeExecution;
}
else
if (rc == VINF_EM_RAW_GUEST_TRAP)
{ /* A genuine pagefault.
* Forward the trap to the guest by injecting the exception and resuming execution.
*/
Log2(("Forward page fault to the guest\n"));
/* The error code might have been changed. */
/* Now we must update CR2. */
goto ResumeExecution;
}
#ifdef VBOX_STRICT
if (rc != VINF_EM_RAW_EMULATE_INSTR)
#endif
/* Need to go back to the recompiler to emulate the instruction. */
break;
}
case X86_XCPT_MF: /* Floating point exception. */
{
{
/* old style FPU error reporting needs some extra work. */
/** @todo don't fall back to the recompiler, but do it manually. */
break;
}
goto ResumeExecution;
}
#ifdef VBOX_STRICT
case X86_XCPT_GP: /* General protection failure exception.*/
case X86_XCPT_UD: /* Unknown opcode exception. */
case X86_XCPT_DE: /* Debug exception. */
case X86_XCPT_SS: /* Stack segment exception. */
case X86_XCPT_NP: /* Segment not present exception. */
{
switch(vector)
{
case X86_XCPT_GP:
break;
case X86_XCPT_DE:
break;
case X86_XCPT_UD:
break;
case X86_XCPT_SS:
break;
case X86_XCPT_NP:
break;
}
goto ResumeExecution;
}
#endif
default:
break;
} /* switch (vector) */
break;
}
case SVM_EXIT_NPF:
{
/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
/* Exit qualification contains the linear address of the page fault. */
/* Handle the pagefault trap for the nested shadow table. */
rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetShadowMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
if (rc == VINF_SUCCESS)
{ /* We've successfully synced our shadow pages, so let's just continue execution. */
goto ResumeExecution;
}
#ifdef VBOX_STRICT
if (rc != VINF_EM_RAW_EMULATE_INSTR)
#endif
/* Need to go back to the recompiler to emulate the instruction. */
break;
}
case SVM_EXIT_VINTR:
/* A virtual interrupt is about to be delivered, which means IF=1. */
goto ResumeExecution;
case SVM_EXIT_FERR_FREEZE:
case SVM_EXIT_INTR:
case SVM_EXIT_NMI:
case SVM_EXIT_SMI:
case SVM_EXIT_INIT:
/* External interrupt; leave to allow it to be dispatched again. */
break;
case SVM_EXIT_WBINVD:
case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
/* Skip instruction and continue directly. */
/* Continue execution.*/
goto ResumeExecution;
case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
{
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
{
Log2(("SVM: Rdtsc\n"));
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
{
Log2(("SVM: invlpg\n"));
/* Truly a pita. Why can't SVM give the same information as VMX? */
if (rc == VINF_SUCCESS)
{
goto ResumeExecution; /* eip already updated */
}
break;
}
case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
{
switch (exitCode - SVM_EXIT_WRITE_CR0)
{
case 0:
break;
case 2:
break;
case 3:
break;
case 4:
break;
default:
AssertFailed();
}
/* Check if a sync operation is pending. */
{
rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
/** @note Force a TLB flush. SVM requires us to do it manually. */
}
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
break;
}
{
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
{
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
break;
}
{
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
break;
}
/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
case SVM_EXIT_IOIO: /* I/O instruction. */
{
/** @todo could use a lookup table here */
if (IoExitInfo.n.u1OP8)
{
uIOSize = 1;
uAndVal = 0xff;
}
else
if (IoExitInfo.n.u1OP16)
{
uIOSize = 2;
uAndVal = 0xffff;
}
else
if (IoExitInfo.n.u1OP32)
{
uIOSize = 4;
uAndVal = 0xffffffff;
}
else
{
AssertFailed(); /* should be fatal. */
break;
}
if (IoExitInfo.n.u1STR)
{
if (IoExitInfo.n.u1REP)
prefix |= PREFIX_REP;
if (IoExitInfo.n.u1Type == 0)
{
}
else
{
}
}
else
{
if (IoExitInfo.n.u1Type == 0)
{
Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
}
else
{
if (IOM_SUCCESS(rc))
{
/* Write back to the EAX register. */
Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
}
}
}
/*
* Handled the I/O return codes.
* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
*/
if (IOM_SUCCESS(rc))
{
/* Update EIP and continue execution. */
{
goto ResumeExecution;
}
Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize, rc));
break;
}
#ifdef VBOX_STRICT
if (rc == VINF_IOM_HC_IOPORT_READ)
else if (rc == VINF_IOM_HC_IOPORT_WRITE)
else
AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
#endif
break;
}
case SVM_EXIT_HLT:
/** Check if external interrupts are pending; if so, don't switch back. */
{
goto ResumeExecution;
}
break;
case SVM_EXIT_RSM:
case SVM_EXIT_INVLPGA:
case SVM_EXIT_VMRUN:
case SVM_EXIT_VMMCALL:
case SVM_EXIT_VMLOAD:
case SVM_EXIT_VMSAVE:
case SVM_EXIT_STGI:
case SVM_EXIT_CLGI:
case SVM_EXIT_SKINIT:
case SVM_EXIT_RDTSCP:
{
/* Unsupported instructions. */
goto ResumeExecution;
}
/* Emulate in ring 3. */
case SVM_EXIT_MONITOR:
case SVM_EXIT_RDPMC:
case SVM_EXIT_PAUSE:
case SVM_EXIT_MWAIT_UNCOND:
case SVM_EXIT_MWAIT_ARMED:
case SVM_EXIT_MSR:
case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
break;
case SVM_EXIT_SHUTDOWN:
break;
case SVM_EXIT_IDTR_READ:
case SVM_EXIT_GDTR_READ:
case SVM_EXIT_LDTR_READ:
case SVM_EXIT_TR_READ:
case SVM_EXIT_IDTR_WRITE:
case SVM_EXIT_GDTR_WRITE:
case SVM_EXIT_LDTR_WRITE:
case SVM_EXIT_TR_WRITE:
case SVM_EXIT_CR0_SEL_WRITE:
default:
/* Unexpected exit codes. */
break;
}
end:
if (fGuestStateSynced)
{
/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
/*
* System MSRs
*/
}
/* Signal changes for the recompiler. */
CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
if (exitCode == SVM_EXIT_INTR)
{
/* On the next entry we'll only sync the host context. */
}
else
{
/* On the next entry we'll sync everything. */
/** @todo we can do better than this */
}
/* translate into a less severe return code */
if (rc == VERR_EM_INTERPRETER)
return rc;
}
/**
* Enters the AMD-V session
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pCpu CPU info struct
*/
{
LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVM->hwaccm.s.svm.idLastCpu, pCpu->uCurrentASID));
/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
return VINF_SUCCESS;
}
/**
* Leaves the AMD-V session
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
return VINF_SUCCESS;
}
{
if(VBOX_FAILURE(rc))
return VERR_EM_INTERPRETER;
{
case PARMTYPE_IMMEDIATE:
case PARMTYPE_ADDRESS:
return VERR_EM_INTERPRETER;
break;
default:
return VERR_EM_INTERPRETER;
}
/** @todo is addr always a flat linear address or ds based
* (in absence of segment override prefixes)????
*/
if (VBOX_SUCCESS(rc))
{
/* Manually invalidate the page for the VM's TLB. */
return VINF_SUCCESS;
}
return rc;
}
/**
* Interprets INVLPG
*
* @returns VBox status code.
* @retval VINF_* Scheduling instructions.
* @retval VERR_EM_INTERPRETER Something we can't cope with.
* @retval VERR_* Fatal errors.
*
* @param pVM The VM handle.
* @param pRegFrame The register frame.
* @param ASID Tagged TLB id for the guest
*
* Updates the EIP if an instruction was executed successfully.
*/
{
/*
* Only allow 32-bit code.
*/
{
int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
if (VBOX_SUCCESS(rc))
{
{
if (VBOX_SUCCESS(rc))
{
}
return rc;
}
}
}
return VERR_EM_INTERPRETER;
}
/**
* Invalidates a guest page
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param GCVirt Page to invalidate
*/
{
/* Skip it if a TLB flush is already pending. */
if (!fFlushPending)
{
}
return VINF_SUCCESS;
}