ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#define LOG_GROUP LOG_GROUP_HWACCM

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <VBox/hwaccm.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include "HWACCMInternal.h"

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <VBox/vm.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <VBox/x86.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <VBox/hwacc_svm.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <VBox/pgm.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <VBox/pdm.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <VBox/err.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <VBox/log.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <VBox/selm.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <VBox/iom.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <VBox/dis.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <VBox/dbgf.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <VBox/disopcode.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <iprt/param.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <iprt/assert.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <iprt/asm.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <iprt/cpuset.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <iprt/mp.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include <iprt/time.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync# include <iprt/thread.h>

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#endif

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#include "HWSVMR0.h"

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsyncstatic int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsyncstatic int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsyncstatic void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsyncstatic uint32_t const g_aIOSize[4] = {1, 2, 0, 4};

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsyncVMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync{

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#if defined(LOG_ENABLED) && !defined(DEBUG_bird)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#endif

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync uint64_t val = ASMRdMsr(MSR_K6_EFER);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (val & MSR_K6_EFER_SVME)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VERR_SVM_IN_USE;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Turn on AMD-V in the EFER MSR. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Write the physical page address where the CPU will store the host state while executing the VM. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VINF_SUCCESS;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync}

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsyncVMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync{

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#if defined(LOG_ENABLED) && !defined(DEBUG_bird)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#endif

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Turn off AMD-V in the EFER MSR. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync uint64_t val = ASMRdMsr(MSR_K6_EFER);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Invalidate host state physical address. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VINF_SUCCESS;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync}

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsyncVMMR0DECL(int) SVMR0InitVM(PVM pVM)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync{

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync int rc;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (RT_FAILURE(rc))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return rc;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Set all bits to intercept all IO accesses. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Erratum 170 which requires a forced TLB flush for each world switch:

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync uint32_t u32Dummy;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync u32BaseFamily= (u32Version >> 8) & 0xf;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync u32Model = ((u32Version >> 4) & 0xf);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync u32Stepping = u32Version & 0xf;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if ( u32Family == 0xf

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Allocate VMCBs for all guest CPUs. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync for (VMCPUID i = 0; i < pVM->cCpus; i++)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync PVMCPU pVCpu = &pVM->aCpus[i];

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Allocate one page for the host context */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (RT_FAILURE(rc))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return rc;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Assert(pVCpu->hwaccm.s.svm.pVMCBHostPhys < _4G);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Allocate one page for the VM control block (VMCB). */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (RT_FAILURE(rc))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return rc;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Assert(pVCpu->hwaccm.s.svm.pVMCBPhys < _4G);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (RT_FAILURE(rc))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return rc;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Set all bits to intercept all MSR accesses. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ASMMemFill32(pVCpu->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VINF_SUCCESS;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync}

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsyncVMMR0DECL(int) SVMR0TermVM(PVM pVM)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync{

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync for (VMCPUID i = 0; i < pVM->cCpus; i++)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync PVMCPU pVCpu = &pVM->aCpus[i];

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pVMCBHost = 0;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pVMCB = 0;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pVMCBPhys = 0;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVCpu->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, false);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pMSRBitmap = 0;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pMSRBitmapPhys = 0;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVM->hwaccm.s.svm.pIOBitmap = 0;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVM->hwaccm.s.svm.pIOBitmapPhys = 0;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VINF_SUCCESS;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync}

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsyncVMMR0DECL(int) SVMR0SetupVM(PVM pVM)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync{

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync int rc = VINF_SUCCESS;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertReturn(pVM, VERR_INVALID_PARAMETER);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Assert(pVM->hwaccm.s.svm.fSupported);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync for (VMCPUID i = 0; i < pVM->cCpus; i++)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync PVMCPU pVCpu = &pVM->aCpus[i];

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVM_VMCB *pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Program the control fields. Most of them never have to be changed again. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (!pVM->hwaccm.s.fNestedPaging)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /*

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (!pVM->hwaccm.s.fNestedPaging)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Intercept all DRx reads and writes by default. Changed later on. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Currently we don't care about DRx reads or writes. DRx registers are trashed.

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#ifndef DEBUG

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVM->hwaccm.s.fNestedPaging)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#endif

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_VINTR

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_NMI

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_SMI

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_INIT

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_RDPMC

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_CPUID

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_RSM

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_HLT

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_INOUT_BITMAP

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_MSR_SHADOW

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_INVLPG

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_TASK_SWITCH

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* With nested paging we don't care about invlpg anymore. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVM->hwaccm.s.fNestedPaging)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL2_INTERCEPT_VMMCALL

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL2_INTERCEPT_VMLOAD

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL2_INTERCEPT_VMSAVE

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL2_INTERCEPT_STGI

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL2_INTERCEPT_CLGI

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL2_INTERCEPT_SKINIT

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL2_INTERCEPT_WBINVD

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Ignore the priority in the TPR; just deliver it when we tell it to. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Set IO and MSR bitmap addresses. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u64MSRPMPhysAddr = pVCpu->hwaccm.s.svm.pMSRBitmapPhys;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* No LBR virtualization. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u64LBRVirt = 0;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /** The ASID must start at 1; the host uses 0. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /** Setup the PAT msr (nested paging only) */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64GPAT = 0x0007040600070406ULL;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync svmR0SetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync svmR0SetMSRPermission(pVCpu, MSR_K6_STAR, true, true);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync svmR0SetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync svmR0SetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync svmR0SetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync svmR0SetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return rc;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync}

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsyncstatic void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync{

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync unsigned ulBit;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync uint8_t *pMSRBitmap = (uint8_t *)pVCpu->hwaccm.s.svm.pMSRBitmap;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (ulMSR <= 0x00001FFF)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Pentium-compatible MSRs */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ulBit = ulMSR * 2;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if ( ulMSR >= 0xC0000000

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync && ulMSR <= 0xC0001FFF)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* AMD Sixth Generation x86 Processor MSRs and SYSCALL */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ulBit = (ulMSR - 0xC0000000) * 2;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pMSRBitmap += 0x800;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if ( ulMSR >= 0xC0010000

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync && ulMSR <= 0xC0011FFF)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* AMD Seventh and Eighth Generation Processor MSRs */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ulBit = (ulMSR - 0xC0001000) * 2;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pMSRBitmap += 0x1000;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertFailed();

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Assert(ulBit < 16 * 1024 - 1);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (fRead)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ASMBitClear(pMSRBitmap, ulBit);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ASMBitSet(pMSRBitmap, ulBit);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (fWrite)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ASMBitClear(pMSRBitmap, ulBit + 1);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync ASMBitSet(pMSRBitmap, ulBit + 1);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync}

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsyncinline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync{

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#ifdef VBOX_WITH_STATISTICS

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#endif

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#ifdef VBOX_STRICT

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pEvent->n.u8Vector == 0xE)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pEvent->n.u8Vector < 0x20)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Assert(pCtx->eflags.u32 & X86_EFL_IF);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#endif

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Set event injection state. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync}

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsyncstatic int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync{

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync int rc;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVCpu->hwaccm.s.Event.fPending)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVM_EVENT Event;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.Event.fPending = false;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VINF_SUCCESS;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* If an active trap is already pending, then we must forward it first! */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (!TRPMHasTrap(pVCpu))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVM_EVENT Event;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Event.n.u8Vector = X86_XCPT_NMI;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Event.n.u1Valid = 1;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Event.n.u32ErrorCode = 0;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Event.n.u3Type = SVM_EVENT_NMI;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VINF_SUCCESS;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* @todo SMI interrupts. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* When external interrupts are pending, we should exit the VM when IF is set. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if ( !(pCtx->eflags.u32 & X86_EFL_IF)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync LogFlow(("Enable irq window exit!\n"));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync uint8_t u8Interrupt;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync rc = PDMGetInterrupt(pVCpu, &u8Interrupt);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (RT_SUCCESS(rc))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertRC(rc);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Can only happen in rare cases where a pending interrupt is cleared behind our back */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Just continue */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#ifdef VBOX_STRICT

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (TRPMHasTrap(pVCpu))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync uint8_t u8Vector;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertRC(rc);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#endif

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if ( (pCtx->eflags.u32 & X86_EFL_IF)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync && TRPMHasTrap(pVCpu)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync )

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync uint8_t u8Vector;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync int rc;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync TRPMEVENT enmType;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVM_EVENT Event;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync RTGCUINT u32ErrorCode;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Event.au64[0] = 0;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* If a new event is pending, then dispatch it now. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertRC(rc);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Assert(enmType != TRPM_SOFTWARE_INT);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Clear the pending trap. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync rc = TRPMResetTrap(pVCpu);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertRC(rc);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Event.n.u8Vector = u8Vector;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Event.n.u1Valid = 1;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Event.n.u32ErrorCode = u32ErrorCode;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (enmType == TRPM_TRAP)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync switch (u8Vector) {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync case 8:

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync case 10:

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync case 11:

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync case 12:

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync case 13:

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync case 14:

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync case 17:

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Valid error codes. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Event.n.u1ErrorCodeValid = 1;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync break;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync default:

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync break;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (u8Vector == X86_XCPT_NMI)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Event.n.u3Type = SVM_EVENT_NMI;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Event.n.u3Type = SVM_EVENT_EXCEPTION;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync } /* if (interrupts can be dispatched) */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VINF_SUCCESS;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync}

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsyncVMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync{

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync NOREF(pVM);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync NOREF(pVCpu);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Nothing to do here. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VINF_SUCCESS;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync}

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsyncVMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync{

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync RTGCUINTPTR val;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVM_VMCB *pVMCB;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVM == NULL)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VERR_INVALID_PARAMETER;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Setup AMD SVM. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Assert(pVM->hwaccm.s.svm.fSupported);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Guest CPU context: ES, CS, SS, DS, FS, GS. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVM_WRITE_SELREG(CS, cs);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVM_WRITE_SELREG(SS, ss);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVM_WRITE_SELREG(DS, ds);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVM_WRITE_SELREG(ES, es);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVM_WRITE_SELREG(FS, fs);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVM_WRITE_SELREG(GS, gs);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Guest CPU context: LDTR. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVM_WRITE_SELREG(LDTR, ldtr);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Guest CPU context: TR. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync SVM_WRITE_SELREG(TR, tr);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Guest CPU context: GDTR. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Guest CPU context: IDTR. */

67c73271505adae0686ddbc74eaeef778ef16792vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /*

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Control registers */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync val = pCtx->cr0;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (!CPUMIsGuestFPUStateActive(pVCpu))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Always use #NM exceptions to load the FPU/XMM state on demand. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /** @todo check if we support the old style mess correctly. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (!(val & X86_CR0_NE))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Log(("Forcing X86_CR0_NE!!!\n"));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Also catch floating point exceptions as we need to report them to the guest in a different way. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.fFPUOldStyleOverride = true;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Always enable caching. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync val &= ~(X86_CR0_CD|X86_CR0_NW);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (!pVM->hwaccm.s.fNestedPaging)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64CR0 = val;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* CR2 as well */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64CR2 = pCtx->cr2;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Save our shadow CR3 register. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVM->hwaccm.s.fNestedPaging)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync PGMMODE enmShwPagingMode;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#if HC_ARCH_BITS == 32

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (CPUMIsGuestInLongModeEx(pCtx))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync enmShwPagingMode = PGMMODE_AMD64_NX;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#endif

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync enmShwPagingMode = PGMGetHostMode(pVM);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Assert(pVMCB->ctrl.u64NestedPagingCR3);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64CR3 = pCtx->cr3;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync val = pCtx->cr4;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (!pVM->hwaccm.s.fNestedPaging)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync switch(pVCpu->hwaccm.s.enmShadowMode)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync case PGMMODE_REAL:

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync case PGMMODE_PROTECTED: /* Protected mode, no paging. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertFailed();

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync case PGMMODE_32_BIT: /* 32-bit paging. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync val &= ~X86_CR4_PAE;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync break;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync case PGMMODE_PAE: /* PAE paging. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /** @todo use normal 32 bits paging */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync val |= X86_CR4_PAE;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync break;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#ifdef VBOX_ENABLE_64_BITS_GUESTS

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync break;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertFailed();

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#endif

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync default: /* shut up gcc */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertFailed();

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64CR4 = val;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Debug registers. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pCtx->dr[7] |= 0x400; /* must be one */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64DR7 = pCtx->dr[7];

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64DR6 = pCtx->dr[6];

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#ifdef DEBUG

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Sync the hypervisor debug state now if any breakpoint is armed. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync && !CPUMIsHyperDebugStateActive(pVCpu)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync && !DBGFIsStepping(pVCpu))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Save the host and load the hypervisor debug state. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertRC(rc);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* DRx intercepts remain enabled. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Override dr6 & dr7 with the hypervisor values. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#endif

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Sync the debug state now if any breakpoint is armed. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync && !CPUMIsGuestDebugStateActive(pVCpu)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync && !DBGFIsStepping(pVCpu))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Disable drx move intercepts. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u16InterceptRdDRx = 0;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->ctrl.u16InterceptWrDRx = 0;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Save the host and load the guest debug state. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync AssertRC(rc);

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* EIP, ESP and EFLAGS */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64RIP = pCtx->rip;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64RSP = pCtx->rsp;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64RFlags = pCtx->eflags.u32;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Set CPL */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64RAX = pCtx->rax;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* vmrun will fail without MSR_K6_EFER_SVME. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* 64 bits guest mode? */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (CPUMIsGuestInLongModeEx(pCtx))

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#if !defined(VBOX_ENABLE_64_BITS_GUESTS)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync if (!pVM->hwaccm.s.fAllow64BitGuests)

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync# endif

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync#endif

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync }

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync else

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync {

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */

ae41886ba231ade1b868dd32ff24ee49813ebbabvboxsync pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;

pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;

}

/* TSC offset. */

if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))

{

uint64_t u64CurTSC = ASMReadTSC();

if (u64CurTSC + pVMCB->ctrl.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))

{

pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;

pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;

STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);

}

else

{

/* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */

LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC, pVMCB->ctrl.u64TSCOffset, u64CurTSC + pVMCB->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVMCB->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));

pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;

pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;

STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow);

}

}

else

{

pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;

pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;

STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);

}

/* Sync the various msrs for 64 bits mode. */

pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */

pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */

pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */

pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */

pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */

#ifdef DEBUG

/* Intercept X86_XCPT_DB if stepping is enabled */

if ( DBGFIsStepping(pVCpu)

|| CPUMIsHyperDebugStateActive(pVCpu))

pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);

else

pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);

#endif

/* Done. */

pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;

return VINF_SUCCESS;

}

VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)

{

int rc = VINF_SUCCESS;

uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;

SVM_VMCB *pVMCB;

bool fSyncTPR = false;

unsigned cResume = 0;

uint8_t u8LastTPR;

PHWACCM_CPUINFO pCpu = 0;

RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;

#ifdef VBOX_STRICT

RTCPUID idCpuCheck;

#endif

#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0

uint64_t u64LastTime = RTTimeMilliTS();

#endif

STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);

pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;

AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);

/* We can jump to this point to resume execution after determining that a VM-exit is innocent.

ResumeExecution:

Assert(!HWACCMR0SuspendPending());

/* Safety precaution; looping for too long here can have a very bad effect on the host */

if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))

{

STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);

rc = VINF_EM_RAW_INTERRUPT;

goto end;

}

/* Check for irq inhibition due to instruction fusing (sti, mov ss). */

if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))

{

Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));

if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))

{

/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.

VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);

/* Irq inhibition is no longer active; clear the corresponding SVM state. */

pVMCB->ctrl.u64IntShadow = 0;

}

}

else

{

/* Irq inhibition is no longer active; clear the corresponding SVM state. */

pVMCB->ctrl.u64IntShadow = 0;

}

#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0

if (RT_UNLIKELY(cResume & 0xf) == 0)

{

uint64_t u64CurTime = RTTimeMilliTS();

if (RT_UNLIKELY(u64CurTime > u64LastTime))

{

u64LastTime = u64CurTime;

TMTimerPollVoid(pVM, pVCpu);

}

}

#endif

/* Check for pending actions that force us to go back to ring 3. */

#ifdef DEBUG

/* Intercept X86_XCPT_DB if stepping is enabled */

if (!DBGFIsStepping(pVCpu))

#endif

{

if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)

|| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))

{

VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);

STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);

STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);

rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;

goto end;

}

}

/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */

if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)

|| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))

{

STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);

rc = VINF_EM_PENDING_REQUEST;

goto end;

}

#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION

/*

uOldEFlags = ASMIntDisableFlags();

if (RTThreadPreemptIsPending(NIL_RTTHREAD))

{

STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);

rc = VINF_EM_RAW_INTERRUPT;

goto end;

}

VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);

#endif

/* When external interrupts are pending, we should exit the VM when IF is set. */

/* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */

rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);

if (RT_FAILURE(rc))

{

STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);

goto end;

}

/* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */

/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! (no longer true)

if (pVM->hwaccm.s.fHasIoApic)

{

bool fPending;

/* TPR caching in CR8 */

int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);

AssertRC(rc);

if (pVM->hwaccm.s.svm.fTPRPatchingActive)

{

/* Our patch code uses LSTAR for TPR caching. */

pCtx->msrLSTAR = u8LastTPR;

if (fPending)

{

/* A TPR change could activate a pending interrupt, so catch lstar writes. */

svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);

}

else

/* No interrupts are pending, so we don't need to be explicitely notified.

svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);

}

else

{

pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */

if (fPending)

{

/* A TPR change could activate a pending interrupt, so catch cr8 writes. */

pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);

}

else

/* No interrupts are pending, so we don't need to be explicitely notified.

pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);

}

fSyncTPR = !fPending;

}

/* All done! Let's start VM execution. */

STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);

/* Enable nested paging if necessary (disabled each time after #VMEXIT). */

pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;

#ifdef LOG_ENABLED

pCpu = HWACCMR0GetCurrentCpu();

if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu

|| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)

{

if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)

LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));

else

LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));

}

if (pCpu->fFlushTLB)

LogFlow(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));

#endif

/*

#ifdef VBOX_STRICT

idCpuCheck = RTMpCpuId();

#endif

VMMR0LogFlushDisable(pVCpu);

/* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */

rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);

if (RT_UNLIKELY(rc != VINF_SUCCESS))

{

STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);

VMMR0LogFlushEnable(pVCpu);

goto end;

}

#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION

/* Disable interrupts to make sure a poke will interrupt execution.

uOldEFlags = ASMIntDisableFlags();

VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);

#endif

pCpu = HWACCMR0GetCurrentCpu();

/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */

/* Note that this can happen both for start and resume due to long jumps back to ring 3. */

if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu

/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */

|| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)

{

/* Force a TLB flush on VM entry. */

pVCpu->hwaccm.s.fForceTLBFlush = true;

}

else

Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);

pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;

/** Set TLB flush state as checked until we return from the world switch. */

ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, true);

/* Check for tlb shootdown flushes. */

if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))

pVCpu->hwaccm.s.fForceTLBFlush = true;

/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */

if ( pVCpu->hwaccm.s.fForceTLBFlush

&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)

{

if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID

|| pCpu->fFlushTLB)

{

pCpu->fFlushTLB = false;

pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */

pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */

pCpu->cTLBFlushes++;

}

else

STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);

pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;

pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;

}

else

{

Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);

/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */

if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)

pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;

Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);

pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;

if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB

&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))

{

/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */

STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);

for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)

SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);

}

}

pVCpu->hwaccm.s.TlbShootdown.cPages = 0;

VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);

AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));

AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));

AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));

pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;

#ifdef VBOX_WITH_STATISTICS

if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)

STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);

else

STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);

#endif

/* In case we execute a goto ResumeExecution later on. */

pVCpu->hwaccm.s.fResumeVM = true;

pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;

Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);

Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);

Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);

Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVCpu->hwaccm.s.svm.pMSRBitmapPhys);

Assert(pVMCB->ctrl.u64LBRVirt == 0);

#ifdef VBOX_STRICT

Assert(idCpuCheck == RTMpCpuId());

#endif

TMNotifyStartOfExecution(pVCpu);

#ifdef VBOX_WITH_KERNEL_USING_XMM

hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);

#else

pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);