HWSVMR0.cpp revision 78beca20d54333b15f350ad9daf91b18b131cfd9
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * HWACCM SVM - Host Context Ring 0.
c58f1213e628a545081c70e26c6b67a841cff880vboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * available from http://www.virtualbox.org. This file is free software;
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * you can redistribute it and/or modify it under the terms of the GNU
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * General Public License (GPL) as published by the Free Software
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
0d12c7f9423f2745f8e282523d0930f91bff03b3vboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
0d12c7f9423f2745f8e282523d0930f91bff03b3vboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
0d12c7f9423f2745f8e282523d0930f91bff03b3vboxsync * additional information or have any questions.
0d12c7f9423f2745f8e282523d0930f91bff03b3vboxsync/*******************************************************************************
0d12c7f9423f2745f8e282523d0930f91bff03b3vboxsync* Header Files *
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync*******************************************************************************/
c2046db2cc346cc299f0cd9b2d1e160179159cfcvboxsync/*******************************************************************************
9939c713bffcfc4305d99d994552aa2ad9bce097vboxsync* Internal Functions *
c2046db2cc346cc299f0cd9b2d1e160179159cfcvboxsync*******************************************************************************/
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsyncstatic int SVMR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
c2046db2cc346cc299f0cd9b2d1e160179159cfcvboxsync/*******************************************************************************
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync* Global Variables *
c2046db2cc346cc299f0cd9b2d1e160179159cfcvboxsync*******************************************************************************/
c2046db2cc346cc299f0cd9b2d1e160179159cfcvboxsync/* IO operation lookup arrays. */
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * Sets up and activates AMD-V on the current CPU
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * @returns VBox status code.
2d8870843ff566fee9bd3a6a5942414254106479vboxsync * @param pCpu CPU info struct
2d8870843ff566fee9bd3a6a5942414254106479vboxsync * @param pVM The VM to operate on. (can be NULL after a resume!!)
2d8870843ff566fee9bd3a6a5942414254106479vboxsync * @param pvPageCpu Pointer to the global cpu page
2d8870843ff566fee9bd3a6a5942414254106479vboxsync * @param pPageCpuPhys Physical address of the global cpu page
2d8870843ff566fee9bd3a6a5942414254106479vboxsyncVMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
2d8870843ff566fee9bd3a6a5942414254106479vboxsync AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
2d8870843ff566fee9bd3a6a5942414254106479vboxsync /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
044af0d1e6474076366759db86f101778c5f20ccvboxsync SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
044af0d1e6474076366759db86f101778c5f20ccvboxsync /* Turn on AMD-V in the EFER MSR. */
044af0d1e6474076366759db86f101778c5f20ccvboxsync /* Write the physical page address where the CPU will store the host state while executing the VM. */
044af0d1e6474076366759db86f101778c5f20ccvboxsync * Deactivates AMD-V on the current CPU
044af0d1e6474076366759db86f101778c5f20ccvboxsync * @returns VBox status code.
044af0d1e6474076366759db86f101778c5f20ccvboxsync * @param pCpu CPU info struct
044af0d1e6474076366759db86f101778c5f20ccvboxsync * @param pvPageCpu Pointer to the global cpu page
044af0d1e6474076366759db86f101778c5f20ccvboxsync * @param pPageCpuPhys Physical address of the global cpu page
044af0d1e6474076366759db86f101778c5f20ccvboxsyncVMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
044af0d1e6474076366759db86f101778c5f20ccvboxsync AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
044af0d1e6474076366759db86f101778c5f20ccvboxsync SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync /* Turn off AMD-V in the EFER MSR. */
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync /* Invalidate host state physical address. */
044af0d1e6474076366759db86f101778c5f20ccvboxsync * Does Ring-0 per VM AMD-V init.
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync * @returns VBox status code.
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync * @param pVM The VM to operate on.
044af0d1e6474076366759db86f101778c5f20ccvboxsync pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync /* Allocate one page for the host context */
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
7d80dfbe5d66fc4c6de6fe109ce96a081496dcd4vboxsync rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync /* Set all bits to intercept all IO accesses. */
a1df400bbe9d64aad400442e56eb637019300a5evboxsync ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync /* Set all bits to intercept all MSR accesses. */
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync /* Erratum 170 which requires a forced TLB flush for each world switch:
044af0d1e6474076366759db86f101778c5f20ccvboxsync * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * All BH-G1/2 and DH-G1/2 models include a fix:
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * Athlon X2: 0x6b 1/2
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * Athlon 64: 0x7f 1
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * Sempron: 0x7f 1/2
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * Turion 64: 0x68 2
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
044af0d1e6474076366759db86f101778c5f20ccvboxsync u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
044af0d1e6474076366759db86f101778c5f20ccvboxsync u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
7d80dfbe5d66fc4c6de6fe109ce96a081496dcd4vboxsync /* Allocate VMCBs for all guest CPUs. */
7d80dfbe5d66fc4c6de6fe109ce96a081496dcd4vboxsync pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
7d80dfbe5d66fc4c6de6fe109ce96a081496dcd4vboxsync /* Allocate one page for the VM control block (VMCB). */
7d80dfbe5d66fc4c6de6fe109ce96a081496dcd4vboxsync rc = RTR0MemObjAllocCont(&pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
7d80dfbe5d66fc4c6de6fe109ce96a081496dcd4vboxsync pVM->aCpus[i].hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB);
7d80dfbe5d66fc4c6de6fe109ce96a081496dcd4vboxsync pVM->aCpus[i].hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, 0);
7d80dfbe5d66fc4c6de6fe109ce96a081496dcd4vboxsync * Does Ring-0 per VM AMD-V termination.
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * @returns VBox status code.
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * @param pVM The VM to operate on.
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync if (pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync RTR0MemObjFree(pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB, false);
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVM->aCpus[i].hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync if (pVM->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * Sets up AMD-V for the specified VM
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * @returns VBox status code.
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * @param pVM The VM to operate on.
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /* Program the control fields. Most of them never have to be changed again. */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * CR0/3/4 writes must be intercepted for obvious reasons.
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8);
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /* Intercept all DRx reads and writes by default. Changed later on. */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * All breakpoints are automatically cleared when the VM exits.
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
0109a2240391a89f6556b1545e6cc57f9efab060vboxsync /* With nested paging we don't care about invlpg anymore. */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /* Ignore the priority in the TPR; just deliver it when we tell it to. */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /* Set IO and MSR bitmap addresses. */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /* No LBR virtualization. */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /** The ASID must start at 1; the host uses 0. */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /** Setup the PAT msr (nested paging only) */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * Injects an event (trap or external interrupt)
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * @param pVM The VM to operate on.
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * @param pVMCB SVM control block
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * @param pCtx CPU Context
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * @param pIntInfo SVM interrupt info
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsyncinline void SVMR0InjectEvent(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync Assert(!VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_INHIBIT_INTERRUPTS));
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /* Set event injection state. */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * Checks for pending guest interrupts and injects them
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * @returns VBox status code.
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * @param pVM The VM to operate on.
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * @param pVCpu The VM CPU to operate on.
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * @param pVMCB SVM control block
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * @param pCtx CPU Context
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsyncstatic int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
d6f8b76ab3b2ec0c270c96f9db6e2568fc41b5fevboxsync Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
d6f8b76ab3b2ec0c270c96f9db6e2568fc41b5fevboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync /* When external interrupts are pending, we should exit the VM when IF is set. */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
9af7167fa39f1f139899c989da973e59b9cccc3fvboxsync || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
6ba706e9f431401d425d16817fdcd6316f83b584vboxsync /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
d6f8b76ab3b2ec0c270c96f9db6e2568fc41b5fevboxsync Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /* Just continue */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* If a new event is pending, then dispatch it now. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Clear the pending trap. */
9939c713bffcfc4305d99d994552aa2ad9bce097vboxsync /* Valid error codes. */
9939c713bffcfc4305d99d994552aa2ad9bce097vboxsync } /* if (interrupts can be dispatched) */
31771163041e3661403a806eb3382d2a165c003bvboxsync * Save the host state
31771163041e3661403a806eb3382d2a165c003bvboxsync * @returns VBox status code.
31771163041e3661403a806eb3382d2a165c003bvboxsync * @param pVM The VM to operate on.
31771163041e3661403a806eb3382d2a165c003bvboxsync * @param pVCpu The VM CPU to operate on.
31771163041e3661403a806eb3382d2a165c003bvboxsyncVMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
31771163041e3661403a806eb3382d2a165c003bvboxsync /* Nothing to do here. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync * Loads the guest state
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync * @returns VBox status code.
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync * @param pVM The VM to operate on.
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync * @param pVCpu The VM CPU to operate on.
9939c713bffcfc4305d99d994552aa2ad9bce097vboxsync * @param pCtx Guest context
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsyncVMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Setup AMD SVM. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Guest CPU context: LDTR. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Guest CPU context: TR. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
9939c713bffcfc4305d99d994552aa2ad9bce097vboxsync /* Guest CPU context: GDTR. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
9939c713bffcfc4305d99d994552aa2ad9bce097vboxsync /* Guest CPU context: IDTR. */
9939c713bffcfc4305d99d994552aa2ad9bce097vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync * Sysenter MSRs (unconditional)
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Control registers */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
9939c713bffcfc4305d99d994552aa2ad9bce097vboxsync /* Always use #NM exceptions to load the FPU/XMM state on demand. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /** @todo check if we support the old style mess correctly. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
9939c713bffcfc4305d99d994552aa2ad9bce097vboxsync /* Always enable caching. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* CR2 as well */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Save our shadow CR3 register. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync case PGMMODE_PROTECTED: /* Protected mode, no paging. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /** @todo use normal 32 bits paging */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
ad27e1d5e48ca41245120c331cc88b50464813cevboxsync default: /* shut up gcc */
9b19ad593b379ebfcc8273f85b90763b14b1da63vboxsync /* Debug registers. */
9b19ad593b379ebfcc8273f85b90763b14b1da63vboxsync if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
9b19ad593b379ebfcc8273f85b90763b14b1da63vboxsync pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
9b19ad593b379ebfcc8273f85b90763b14b1da63vboxsync pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
9b19ad593b379ebfcc8273f85b90763b14b1da63vboxsync pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
9b19ad593b379ebfcc8273f85b90763b14b1da63vboxsync /* Sync the debug state now if any breakpoint is armed. */
9b19ad593b379ebfcc8273f85b90763b14b1da63vboxsync if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
9b19ad593b379ebfcc8273f85b90763b14b1da63vboxsync /* Disable drx move intercepts. */
9b19ad593b379ebfcc8273f85b90763b14b1da63vboxsync /* Save the host and load the guest debug state. */
9b19ad593b379ebfcc8273f85b90763b14b1da63vboxsync int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
9b19ad593b379ebfcc8273f85b90763b14b1da63vboxsync /* EIP, ESP and EFLAGS */
9b19ad593b379ebfcc8273f85b90763b14b1da63vboxsync /* Set CPL */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* vmrun will fail without MSR_K6_EFER_SVME. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync /* 64 bits guest mode? */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
88acfa6629a7976c0583c1712d2b5b22a87a5121vboxsync /* TSC offset. */
9d020a0622f95aec3aabaff436a495e88dbbd71avboxsync if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
2d8870843ff566fee9bd3a6a5942414254106479vboxsync pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
2d8870843ff566fee9bd3a6a5942414254106479vboxsync pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Sync the various msrs for 64 bits mode. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
2d8870843ff566fee9bd3a6a5942414254106479vboxsync pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Intercept X86_XCPT_DB if stepping is enabled */
2d8870843ff566fee9bd3a6a5942414254106479vboxsync pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Done. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
9d020a0622f95aec3aabaff436a495e88dbbd71avboxsync * Runs guest code in an AMD-V VM.
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync * @returns VBox status code.
9d020a0622f95aec3aabaff436a495e88dbbd71avboxsync * @param pVM The VM to operate on.
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync * @param pVCpu The VM CPU to operate on.
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync * @param pCtx Guest context
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsyncVMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
9d020a0622f95aec3aabaff436a495e88dbbd71avboxsync bool fSyncTPR = false;
9d020a0622f95aec3aabaff436a495e88dbbd71avboxsync unsigned cResume = 0;
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Safety precaution; looping for too long here can have a very bad effect on the host */
044af0d1e6474076366759db86f101778c5f20ccvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
044af0d1e6474076366759db86f101778c5f20ccvboxsync /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
044af0d1e6474076366759db86f101778c5f20ccvboxsync if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
044af0d1e6474076366759db86f101778c5f20ccvboxsync Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
044af0d1e6474076366759db86f101778c5f20ccvboxsync /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
044af0d1e6474076366759db86f101778c5f20ccvboxsync * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
044af0d1e6474076366759db86f101778c5f20ccvboxsync * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
044af0d1e6474076366759db86f101778c5f20ccvboxsync * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
044af0d1e6474076366759db86f101778c5f20ccvboxsync VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
044af0d1e6474076366759db86f101778c5f20ccvboxsync /* Irq inhibition is no longer active; clear the corresponding SVM state. */
5eda82e218d35ae0691febd531e1bfc0324cc4a6vboxsync /* Irq inhibition is no longer active; clear the corresponding SVM state. */
5eda82e218d35ae0691febd531e1bfc0324cc4a6vboxsync /* Check for pending actions that force us to go back to ring 3. */
5eda82e218d35ae0691febd531e1bfc0324cc4a6vboxsync /* Intercept X86_XCPT_DB if stepping is enabled */
5eda82e218d35ae0691febd531e1bfc0324cc4a6vboxsync || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync /** @todo This must be repeated (or moved down) after we've disabled interrupts
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * below because a rescheduling request (IPI) might arrive before we get
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync * there and we end up exceeding our timeslice. (Putting it here for
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync * now because I don't want to mess up anything.) */
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync /* When external interrupts are pending, we should exit the VM when IF is set. */
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync /* TPR caching in CR8 */
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync int rc = PDMApicGetTPR(pVCpu, &u8LastVTPR, &fPending);
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync /* No interrupts are pending, so we don't need to be explicitely notified.
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync * There are enough world switches for detecting pending interrupts.
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync /* All done! Let's start VM execution. */
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
31771163041e3661403a806eb3382d2a165c003bvboxsync * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
31771163041e3661403a806eb3382d2a165c003bvboxsync * (until the actual world switch)
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync /* Disable interrupts to make sure a poke will interrupt execution.
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync /* Force a TLB flush on VM entry. */
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync /* Check for tlb shootdown flushes. */
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
d90eec53c9dcaa0f3d1054e8734ed46875b9093avboxsync if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
d90eec53c9dcaa0f3d1054e8734ed46875b9093avboxsync pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
d90eec53c9dcaa0f3d1054e8734ed46875b9093avboxsync pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
ad27e1d5e48ca41245120c331cc88b50464813cevboxsync for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsync /* In case we execute a goto ResumeExecution later on. */
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsync pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsync Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsync Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsync Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsync pVCpu->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, x);
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync /* Reason for the VM exit */
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
ad27e1d5e48ca41245120c331cc88b50464813cevboxsync Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
044af0d1e6474076366759db86f101778c5f20ccvboxsync Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
a1df400bbe9d64aad400442e56eb637019300a5evboxsync Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
4a1654dd5b9f0ae4e149d909843a3ab07b8bec33vboxsync Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
a1df400bbe9d64aad400442e56eb637019300a5evboxsync Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Let's first sync back eip, esp, and eflags. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* eax is saved/restore across the vmrun instruction */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Can be updated behind our back in the nested paging case. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync * System MSRs
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Note! NOW IT'S SAFE FOR LOGGING! */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
2d8870843ff566fee9bd3a6a5942414254106479vboxsync Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Sync back DR6 as it could have been changed by hitting breakpoints. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Check if an injected event was interrupted prematurely. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Error code present? (redundant) */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Deal with the reason of the VM-exit. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
a1df400bbe9d64aad400442e56eb637019300a5evboxsync case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Pending trap. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log2(("Hardware/software interrupt %d\n", vector));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Note that we don't support guest and host-initiated debugging at the same time. */
a1df400bbe9d64aad400442e56eb637019300a5evboxsync rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Reinject the exception. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Return to ring 3 to deal with the debug exit code. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Continue execution. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync { /* A genuine pagefault.
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync * Forward the trap to the guest by injecting the exception and resuming execution.
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Now we must update CR2. */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* 0xF0, 0x0F, 0x22, 0xC0 = mov cr8, eax */
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, cbOp);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
3a4a6501d0ccd629d9951b644d380c7bb2d46086vboxsync rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, cbOp);
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync /* Exit qualification contains the linear address of the page fault. */
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
4dcf37df51439573b55cc16f53590c7b68cb1051vboxsync Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync { /* We've successfully synced our shadow pages, so let's just continue execution. */
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync { /* A genuine pagefault.
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync * Forward the trap to the guest by injecting the exception and resuming execution.
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync /* The error code might have been changed. */
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync /* Now we must update CR2. */
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync /* Need to go back to the recompiler to emulate the instruction. */
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync /* old style FPU error reporting needs some extra work. */
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync /** @todo don't fall back to the recompiler, but do it manually. */
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
feffb6492a600891a421e4c1bf0a2bcd2213568dvboxsync STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
26645f447bb6a819f33492c84e03e364092ec600vboxsync case X86_XCPT_GP: /* General protection failure exception.*/
590bfe12ce22cd3716448fbb9f4dc51664bfe5e2vboxsync case X86_XCPT_NP: /* Segment not present exception. */
switch(vector)
case X86_XCPT_GP:
case X86_XCPT_DE:
case X86_XCPT_UD:
case X86_XCPT_SS:
case X86_XCPT_NP:
goto ResumeExecution;
case SVM_EXIT_NPF:
/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
Log(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
goto ResumeExecution;
#ifdef VBOX_STRICT
case SVM_EXIT_VINTR:
goto ResumeExecution;
case SVM_EXIT_FERR_FREEZE:
case SVM_EXIT_INTR:
case SVM_EXIT_NMI:
case SVM_EXIT_SMI:
case SVM_EXIT_INIT:
case SVM_EXIT_WBINVD:
goto ResumeExecution;
goto ResumeExecution;
goto ResumeExecution;
goto ResumeExecution;
goto ResumeExecution;
case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
AssertFailed();
rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || PGMGetGuestMode(pVCpu) <= PGMMODE_PROTECTED || pVCpu->hwaccm.s.fForceTLBFlush,
("rc=%Rrc mode=%d fForceTLBFlush=%RTbool\n", rc, PGMGetGuestMode(pVCpu), pVCpu->hwaccm.s.fForceTLBFlush));
goto ResumeExecution;
goto ResumeExecution;
case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
goto ResumeExecution;
goto ResumeExecution;
goto ResumeExecution;
goto ResumeExecution;
/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
goto ResumeExecution;
goto ResumeExecution;
Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
#ifdef VBOX_STRICT
AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
case SVM_EXIT_HLT:
goto ResumeExecution;
case SVM_EXIT_MWAIT_UNCOND:
goto ResumeExecution;
case SVM_EXIT_RSM:
case SVM_EXIT_INVLPGA:
case SVM_EXIT_VMRUN:
case SVM_EXIT_VMMCALL:
case SVM_EXIT_VMLOAD:
case SVM_EXIT_VMSAVE:
case SVM_EXIT_STGI:
case SVM_EXIT_CLGI:
case SVM_EXIT_SKINIT:
goto ResumeExecution;
case SVM_EXIT_MSR:
/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
goto ResumeExecution;
AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
case SVM_EXIT_MONITOR:
case SVM_EXIT_PAUSE:
case SVM_EXIT_MWAIT_ARMED:
case SVM_EXIT_SHUTDOWN:
case SVM_EXIT_IDTR_READ:
case SVM_EXIT_GDTR_READ:
case SVM_EXIT_LDTR_READ:
case SVM_EXIT_TR_READ:
case SVM_EXIT_IDTR_WRITE:
case SVM_EXIT_GDTR_WRITE:
case SVM_EXIT_LDTR_WRITE:
case SVM_EXIT_TR_WRITE:
case SVM_EXIT_CR0_SEL_WRITE:
end:
CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
return rc;
LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
return VINF_SUCCESS;
return VINF_SUCCESS;
static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
return VERR_EM_INTERPRETER;
case PARMTYPE_IMMEDIATE:
case PARMTYPE_ADDRESS:
return VERR_EM_INTERPRETER;
return VERR_EM_INTERPRETER;
return VINF_SUCCESS;
return rc;
DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
return rc;
return VERR_EM_INTERPRETER;
if (!fFlushPending)
/* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
return VINF_SUCCESS;
/* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
return VINF_SUCCESS;
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
int rc;
return rc;