HWSVMR0.cpp revision 6ca4e5aa3635ceff1141c84761528848805e1037
/* $Id$ */
/** @file
* HM SVM (AMD-V) - Host Context Ring-0.
*/
/*
* Copyright (C) 2006-2012 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_HM
#include "HMInternal.h"
#include <VBox/disopcode.h>
#include <iprt/asm-amd64-x86.h>
#endif
#include "HWSVMR0.h"
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
/** Convert hidden selector attribute word between VMX and SVM formats. */
do \
{ \
} while (0)
do \
{ \
} while (0)
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/* IO operation lookup arrays. */
/**
* Sets up and activates AMD-V on the current CPU.
*
* @returns VBox status code.
* @param pCpu Pointer to the CPU info struct.
* @param pVM Pointer to the VM (can be NULL after a resume!).
* @param pvCpuPage Pointer to the global CPU page.
* @param HCPhysCpuPage Physical address of the global CPU page.
*/
VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
{
/*
*/
if (fEfer & MSR_K6_EFER_SVME)
{
/*
* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V.
*/
if ( pVM
{
pCpu->fIgnoreAMDVInUseError = true;
}
if (!pCpu->fIgnoreAMDVInUseError)
return VERR_SVM_IN_USE;
}
/* Turn on AMD-V in the EFER MSR. */
/* Write the physical page address where the CPU will store the host state while executing the VM. */
/*
* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
* to flush the TLB with before using a new ASID.
*/
pCpu->fFlushAsidBeforeUse = true;
/*
* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
*/
++pCpu->cTlbFlushes;
return VINF_SUCCESS;
}
/**
* Deactivates AMD-V on the current CPU.
*
* @returns VBox status code.
* @param pCpu Pointer to the CPU info struct.
* @param pvCpuPage Pointer to the global CPU page.
* @param HCPhysCpuPage Physical address of the global CPU page.
*/
{
/* Turn off AMD-V in the EFER MSR. */
/* Invalidate host state physical address. */
return VINF_SUCCESS;
}
/**
* Does Ring-0 per VM AMD-V init.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
int rc;
/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
if (RT_FAILURE(rc))
return rc;
/* Set all bits to intercept all IO accesses. */
/*
* Erratum 170 which requires a forced TLB flush for each world switch:
*
* All BH-G1/2 and DH-G1/2 models include a fix:
* Athlon X2: 0x6b 1/2
* 0x68 1/2
* Athlon 64: 0x7f 1
* 0x6f 2
* Sempron: 0x7f 1/2
* 0x6f 2
* 0x6c 2
* 0x7c 2
* Turion 64: 0x68 2
*/
if ( u32Family == 0xf
{
Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
}
/* Allocate VMCBs for all guest CPUs. */
{
/* Allocate one page for the host context */
rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVMCBHost, 1 << PAGE_SHIFT, false /* fExecutable */);
if (RT_FAILURE(rc))
return rc;
/* Allocate one page for the VM control block (VMCB). */
if (RT_FAILURE(rc))
return rc;
/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
if (RT_FAILURE(rc))
return rc;
/* Set all bits to intercept all MSR accesses. */
}
return VINF_SUCCESS;
}
/**
* Does Ring-0 per VM AMD-V termination.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
{
{
}
{
}
{
}
}
{
}
return VINF_SUCCESS;
}
/**
* Sets up AMD-V for the specified VM.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
int rc = VINF_SUCCESS;
{
/*
* Program the control fields. Most of them never have to be changed again.
* CR0/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's.
* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical.
*/
/* CR0/4 writes must be intercepted for obvious reasons. */
/* Intercept all DRx reads and writes by default. Changed later on. */
/* Intercept traps; only #NM is always intercepted. */
#ifdef VBOX_ALWAYS_TRAP_PF
#endif
#ifdef VBOX_STRICT
;
#endif
/* Set up instruction and miscellaneous intercepts. */
| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
;
| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the
guest (host thinks the cpu load is high) */
/* Ignore the priority in the TPR; just deliver it when we tell it to. */
/* Set IO and MSR bitmap addresses. */
/* No LBR virtualization. */
/* The ASID must start at 1; the host uses 0. */
/*
* Setup the PAT MSR (nested paging only)
* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
* so choose type 6 for all PAT slots.
*/
/* If nested paging is not in use, additional intercepts have to be set up. */
{
/*
* We must also intercept:
* - INVLPG (must go through shadow paging)
*/
/* Page faults must be intercepted to implement shadow paging. */
}
/*
* to modify them directly.
*/
}
return rc;
}
/**
* Sets the permission bits for the specified MSR.
*
* @param pVCpu Pointer to the VMCPU.
* @param ulMSR MSR value.
* @param fRead Whether reading is allowed.
* @param fWrite Whether writing is allowed.
*/
{
unsigned ulBit;
if (ulMSR <= 0x00001FFF)
{
/* Pentium-compatible MSRs */
}
else if ( ulMSR >= 0xC0000000
&& ulMSR <= 0xC0001FFF)
{
/* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
pvMsrBitmap += 0x800;
}
else if ( ulMSR >= 0xC0010000
&& ulMSR <= 0xC0011FFF)
{
/* AMD Seventh and Eighth Generation Processor MSRs */
pvMsrBitmap += 0x1000;
}
else
{
AssertFailed();
return;
}
if (fRead)
else
if (fWrite)
else
}
/**
* Posts a pending event (trap or external interrupt). An injected event should only
* be written to the VMCB immediately before VMRUN, otherwise we might have stale events
* injected across VM resets and suchlike. See @bugref{6220}.
*
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest CPU context.
* @param pIntInfo Pointer to the SVM interrupt info.
*/
{
#ifdef VBOX_STRICT
#endif
/* If there's an event pending already, we're in trouble... */
/* Set pending event state. */
}
/**
* Injects an event (trap or external interrupt).
*
* @param pVCpu Pointer to the VMCPU.
* @param pvVMCB Pointer to the VMCB.
* @param pCtx Pointer to the guest CPU context.
* @param pIntInfo Pointer to the SVM interrupt info.
*/
DECLINLINE(void) hmR0SvmInjectEvent(PVMCPU pVCpu, SVM_VMCB *pvVMCB, CPUMCTX *pCtx, SVM_EVENT *pEvent)
{
#ifdef VBOX_WITH_STATISTICS
#endif
#ifdef VBOX_STRICT
{
}
Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
else
{
}
#endif
/* Set event injection state. */
}
/**
* Checks for pending guest interrupts and injects them.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pvVMCB Pointer to the VMCB.
* @param pCtx Pointer to the guest CPU Context.
*/
{
int rc;
/*
* Dispatch any pending interrupts (injected before, but a VM-exit occurred prematurely).
*/
{
Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hm.s.Event.u64IntrInfo, pVCpu->hm.s.Event.u32ErrCode,
return VINF_SUCCESS;
}
/*
* If an active trap is already pending, we must forward it first!
*/
if (!TRPMHasTrap(pVCpu))
{
{
Event.n.u32ErrorCode = 0;
return VINF_SUCCESS;
}
/** @todo SMI interrupts. */
/*
* When external interrupts are pending, we should exit the VM when IF is set.
*/
{
{
{
LogFlow(("Enable irq window exit!\n"));
else
{
Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n",
}
/** @todo Use virtual interrupt method to inject a pending IRQ; dispatched as
* soon as guest.IF is set. */
}
}
else
{
if (RT_SUCCESS(rc))
{
}
else
{
/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
/* Just continue */
}
}
}
}
#ifdef VBOX_STRICT
if (TRPMHasTrap(pVCpu))
{
}
#endif
&& TRPMHasTrap(pVCpu)
)
{
/* If a new event is pending, then dispatch it now. */
/* Clear the pending trap. */
{
switch (u8Vector)
{
case X86_XCPT_DF:
case X86_XCPT_TS:
case X86_XCPT_NP:
case X86_XCPT_SS:
case X86_XCPT_GP:
case X86_XCPT_PF:
case X86_XCPT_AC:
/* Valid error codes. */
break;
default:
break;
}
if (u8Vector == X86_XCPT_NMI)
else
}
else
} /* if (interrupts can be dispatched) */
return VINF_SUCCESS;
}
/**
* Save the host state.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
*/
{
/* Nothing to do here. */
return VINF_SUCCESS;
}
/**
* Loads the guest state.
*
* NOTE: Don't do anything here that can cause a jump back to ring-3!!!
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest CPU context.
*/
{
return VERR_INVALID_PARAMETER;
/* Setup AMD SVM. */
/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
{
}
/* Guest CPU context: LDTR. */
{
}
/* Guest CPU context: TR. */
{
}
/* Guest CPU context: GDTR. */
{
}
/* Guest CPU context: IDTR. */
{
}
/*
* Sysenter MSRs (unconditional)
*/
/* Control registers */
{
if (!CPUMIsGuestFPUStateActive(pVCpu))
{
}
else
{
/** @todo check if we support the old style mess correctly. */
if (!(val & X86_CR0_NE))
{
Log(("Forcing X86_CR0_NE!!!\n"));
/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
{
}
}
val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
}
/* Always enable caching. */
/*
* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level.
* Note: In nested paging mode, the guest is allowed to run with paging disabled; the guest-physical to host-physical
* translation will remain active.
*/
{
val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
val |= X86_CR0_WP; /* Must set this as we rely on protecting various pages and supervisor writes must be caught. */
}
}
/* CR2 as well */
{
/* Save our shadow CR3 register. */
{
#if HC_ARCH_BITS == 32
if (CPUMIsGuestInLongModeEx(pCtx))
else
#endif
}
else
{
Assert(pvVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
}
}
{
{
{
case PGMMODE_REAL:
case PGMMODE_PROTECTED: /* Protected mode, no paging. */
AssertFailed();
case PGMMODE_32_BIT: /* 32-bit paging. */
val &= ~X86_CR4_PAE;
break;
case PGMMODE_PAE: /* PAE paging. */
case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
/** Must use PAE paging as we could use physical memory > 4 GB */
val |= X86_CR4_PAE;
break;
case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
#ifdef VBOX_ENABLE_64_BITS_GUESTS
break;
#else
AssertFailed();
#endif
default: /* shut up gcc */
AssertFailed();
}
}
}
/* Debug registers. */
{
#ifdef DEBUG
/* Sync the hypervisor debug state now if any breakpoint is armed. */
&& !DBGFIsStepping(pVCpu))
{
/* Save the host and load the hypervisor debug state. */
/* DRx intercepts remain enabled. */
/* Override dr6 & dr7 with the hypervisor values. */
}
else
#endif
/* Sync the debug state now if any breakpoint is armed. */
&& !DBGFIsStepping(pVCpu))
{
/* Disable drx move intercepts. */
/* Save the host and load the guest debug state. */
}
}
/* EIP, ESP and EFLAGS */
/* Set CPL */
/* vmrun will fail without MSR_K6_EFER_SVME. */
/* 64 bits guest mode? */
if (CPUMIsGuestInLongModeEx(pCtx))
{
#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
#else
# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
# endif
#endif
/* Unconditionally update these as wrmsr might have changed them. (HM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
}
else
{
/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
}
/* TSC offset. */
{
{
}
else
{
/* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
}
}
else
{
}
/* Sync the various MSRs for 64-bit mode. */
#ifdef DEBUG
/* Intercept X86_XCPT_DB if stepping is enabled */
if ( DBGFIsStepping(pVCpu)
else
#endif
/* Done. */
return VINF_SUCCESS;
}
/**
* Setup TLB for ASID.
*
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
*/
{
pCpu = HMR0GetCurrentCpu();
/*
* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
* This can happen both for start & resume due to long jumps back to ring-3.
* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
* so we cannot reuse the ASIDs without flushing.
*/
bool fNewAsid = false;
{
fNewAsid = true;
}
/*
* Set TLB flush state as checked until we return from the world switch.
*/
/*
* Check for TLB shootdown flushes.
*/
{
/*
* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
*/
}
{
if (fNewAsid)
{
++pCpu->uCurrentAsid;
bool fHitASIDLimit = false;
{
pCpu->cTlbFlushes++;
fHitASIDLimit = true;
{
pCpu->fFlushAsidBeforeUse = true;
}
else
{
pCpu->fFlushAsidBeforeUse = false;
}
}
if ( !fHitASIDLimit
&& pCpu->fFlushAsidBeforeUse)
{
else
{
pCpu->fFlushAsidBeforeUse = false;
}
}
}
else
{
else
}
}
else
{
/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
* not be executed. See hmQueueInvlPage() where it is commented
* out. Support individual entry flushing someday. */
{
/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
}
}
/* Update VMCB with the ASID. */
("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
#ifdef VBOX_WITH_STATISTICS
{
}
else
#endif
}
/**
* Runs guest code in an AMD-V VM.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest CPU context.
*/
{
int rc2;
bool fSyncTPR = false;
unsigned cResume = 0;
PHMGLOBLCPUINFO pCpu = 0;
#ifdef VBOX_STRICT
#endif
#endif
/*
* We can jump to this point to resume execution after determining that a VM-exit is innocent.
*/
Assert(!HMR0SuspendPending());
/*
* Safety precaution; looping for too long here can have a very bad effect on the host.
*/
{
goto end;
}
/*
* Check for IRQ inhibition due to instruction fusing (sti, mov ss).
*/
{
Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
{
/*
* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
* break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
*/
/* Irq inhibition is no longer active; clear the corresponding SVM state. */
}
}
else
{
/* Irq inhibition is no longer active; clear the corresponding SVM state. */
}
{
{
}
}
#endif
/*
* Check for pending actions that force us to go back to ring-3.
*/
if ( VM_FF_ISPENDING(pVM, VM_FF_HM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
| VMCPU_FF_REQUEST))
{
/* Check if a sync operation is pending. */
{
rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
if (rc != VINF_SUCCESS)
{
goto end;
}
}
#ifdef DEBUG
/* Intercept X86_XCPT_DB if stepping is enabled */
if (!DBGFIsStepping(pVCpu))
#endif
{
{
rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
goto end;
}
}
/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
{
goto end;
}
/* Check if a pgm pool flush is in progress. */
{
goto end;
}
/* Check if DMA work is pending (2nd+ run). */
{
goto end;
}
}
/*
* Exit to ring-3 preemption/work is pending.
*
* Interrupts are disabled before the call to make sure we don't miss any interrupt
* that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
* further down, but hmR0SvmCheckPendingInterrupt makes that impossible.)
*
* Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
* shootdowns rely on this.
*/
{
goto end;
}
#endif
/*
* When external interrupts are pending, we should exit the VM when IF is set.
* Note: *After* VM_FF_INHIBIT_INTERRUPTS check!!
*/
if (RT_FAILURE(rc))
goto end;
/*
* TPR caching using CR8 is only available in 64-bit mode or with 32-bit guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is
* supported.
* Note: we can't do this in LoddGuestState as PDMApicGetTPR can jump back to ring 3 (lock)! (no longer true)
*/
/** @todo query and update the TPR only when it could have been changed (mmio access)
*/
{
/* TPR caching in CR8 */
bool fPending;
{
/* Our patch code uses LSTAR for TPR caching. */
if (fPending)
{
/* A TPR change could activate a pending interrupt, so catch lstar writes. */
}
else
{
/*
* No interrupts are pending, so we don't need to be explicitely notified.
* There are enough world switches for detecting pending interrupts.
*/
}
}
else
{
/* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
if (fPending)
{
/* A TPR change could activate a pending interrupt, so catch cr8 writes. */
}
else
{
/*
* No interrupts are pending, so we don't need to be explicitly notified.
* There are enough world switches for detecting pending interrupts.
*/
}
}
}
/* All done! Let's start VM execution. */
/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
#ifdef LOG_ENABLED
pCpu = HMR0GetCurrentCpu();
LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
LogFlow(("Manual TLB flush\n"));
#endif
/*
* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
* (until the actual world switch)
*/
#ifdef VBOX_STRICT
idCpuCheck = RTMpCpuId();
#endif
/*
* Load the guest state; *must* be here as it sets up the shadow CR0 for lazy FPU syncing!
*/
{
goto end;
}
/*
* Disable interrupts to make sure a poke will interrupt execution.
* This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
*/
#endif
/* Setup TLB control and ASID in the VMCB. */
/* In case we execute a goto ResumeExecution later on. */
#ifdef VBOX_STRICT
#endif
/*
* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
*/
{
uint64_t u64GuestTscAux = 0;
}
#ifdef VBOX_WITH_KERNEL_USING_XMM
#else
pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVMCBHost, pVCpu->hm.s.svm.HCPhysVMCB, pCtx, pVM, pVCpu);
#endif
/* Possibly the last TSC value seen by the guest (too high) (only when we're in TSC offset mode). */
{
/* Restore host's TSC_AUX. */
}
uOldEFlags = ~(RTCCUINTREG)0;
#endif
/*
* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING-3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
*/
/* Reason for the VM exit */
{
#ifdef DEBUG
#endif
goto end;
}
/* Let's first sync back EIP, ESP, and EFLAGS. */
/*
* Save all the MSRs that can be changed by the guest without causing a world switch.
* FS & GS base are saved with SVM_READ_SELREG.
*/
/* Can be updated behind our back in the nested paging case. */
/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
/*
* Correct the hidden CS granularity flag. Haven't seen it being wrong in any other
* register (yet).
*/
{
}
#define SVM_ASSERT_SEL_GRANULARITY(reg) \
/*
* Correct the hidden SS DPL field. It can be wrong on certain CPUs
* sometimes (seen it on AMD Fusion CPUs with 64-bit guests). The CPU
* always uses the CPL field in the VMCB instead of the DPL in the hidden
* SS (chapter AMD spec. 15.5.1 Basic operation).
*/
/*
* Remaining guest CPU context: TR, IDTR, GDTR, LDTR;
* must sync everything otherwise we can get out of sync when jumping back to ring-3.
*/
/*
* No reason to sync back the CRx and DRx registers as they cannot be changed by the guest
* unless in the nested paging case where CR3 can be changed by the guest.
*/
{
}
/* Note! NOW IT'S SAFE FOR LOGGING! */
/* Take care of instruction fusing (sti, mov ss) (see AMD spec. 15.20.5 Interrupt Shadows) */
{
}
else
/* Sync back DR6 as it could have been changed by hitting breakpoints. */
/* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
/* Check if an injected event was interrupted prematurely. */
/* we don't care about 'int xx' as the instruction will be restarted. */
{
Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hm.s.Event.u64IntrInfo, (RTGCPTR)pCtx->rip, exitCode));
#ifdef LOG_ENABLED
if ( exitCode == SVM_EXIT_EXCEPTION_E
{
Log(("Double fault!\n"));
}
#endif
/* Error code present? (redundant) */
else
}
#ifdef VBOX_WITH_STATISTICS
if (exitCode == SVM_EXIT_NPF)
else
#endif
/* Sync back the TPR if it was changed. */
if (fSyncTPR)
{
{
{
/* Our patch code uses LSTAR for TPR caching. */
}
}
else
{
{
/* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
}
}
}
#ifdef DBGFTRACE_ENABLED /** @todo DTrace */
#endif
VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, exitCode, pvVMCB->ctrl.u64ExitInfo1, pvVMCB->ctrl.u64ExitInfo2,
#endif
/* Deal with the reason of the VM-exit. */
switch (exitCode)
{
case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
{
/* Pending trap. */
switch (vector)
{
case X86_XCPT_DB:
{
/* Note that we don't support guest and host-initiated debugging at the same time. */
if (rc == VINF_EM_RAW_GUEST_TRAP)
{
/* Reinject the exception. */
goto ResumeExecution;
}
/* Return to ring 3 to deal with the debug exit code. */
Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs.Sel, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
break;
}
case X86_XCPT_NM:
{
/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
if (rc == VINF_SUCCESS)
{
/* Continue execution. */
goto ResumeExecution;
}
Log(("Forward #NM fault to the guest\n"));
goto ResumeExecution;
}
case X86_XCPT_PF: /* Page fault */
{
#ifdef VBOX_ALWAYS_TRAP_PF
{
/*
* A genuine pagefault. Forward the trap to the guest by injecting the exception and resuming execution.
*/
Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip,
/* Now we must update CR2. */
goto ResumeExecution;
}
#endif
#ifdef VBOX_HM_WITH_GUEST_PATCHING
/* Shortcut for APIC TPR reads and writes; 32 bits guests only */
&& CPUMGetGuestCPL(pVCpu) == 0
{
if ( rc == VINF_SUCCESS
&& GCPhys == GCPhysApicBase)
{
/* Only attempt to patch the instruction once. */
if (!pPatch)
{
break;
}
}
}
#endif
/* Exit qualification contains the linear address of the page fault. */
/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
if (rc == VINF_SUCCESS)
{
/* We've successfully synced our shadow pages, so let's just continue execution. */
Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
goto ResumeExecution;
}
else if (rc == VINF_EM_RAW_GUEST_TRAP)
{
/*
* A genuine pagefault. Forward the trap to the guest by injecting the exception and resuming execution.
*/
Log2(("Forward page fault to the guest\n"));
/* The error code might have been changed. */
/* Now we must update CR2. */
goto ResumeExecution;
}
#ifdef VBOX_STRICT
#endif
/* Need to go back to the recompiler to emulate the instruction. */
break;
}
case X86_XCPT_MF: /* Floating point exception. */
{
{
/* old style FPU error reporting needs some extra work. */
/** @todo don't fall back to the recompiler, but do it manually. */
break;
}
goto ResumeExecution;
}
#ifdef VBOX_STRICT
case X86_XCPT_BP: /* Breakpoint. */
case X86_XCPT_GP: /* General protection failure exception.*/
case X86_XCPT_UD: /* Unknown opcode exception. */
case X86_XCPT_DE: /* Divide error. */
case X86_XCPT_SS: /* Stack segment exception. */
case X86_XCPT_NP: /* Segment not present exception. */
{
switch (vector)
{
case X86_XCPT_GP:
break;
case X86_XCPT_BP:
/** Saves the wrong EIP on the stack (pointing to the int3 instead of the next instruction. */
break;
case X86_XCPT_DE:
break;
case X86_XCPT_UD:
break;
case X86_XCPT_SS:
break;
case X86_XCPT_NP:
break;
}
goto ResumeExecution;
}
#endif
default:
break;
} /* switch (vector) */
break;
}
case SVM_EXIT_NPF:
{
/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, GCPhysFault, errCode));
#ifdef VBOX_HM_WITH_GUEST_PATCHING
/* Shortcut for APIC TPR reads and writes; 32 bits guests only */
|| (errCode & (X86_TRAP_PF_P | X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P | X86_TRAP_PF_RSVD) /* mmio optimization */)
&& CPUMGetGuestCPL(pVCpu) == 0
{
{
/* Only attempt to patch the instruction once. */
if (!pPatch)
{
break;
}
}
}
#endif
/* Handle the pagefault trap for the nested shadow table. */
if (CPUMIsGuestInLongModeEx(pCtx))
else
#endif
/* MMIO optimization */
{
rc = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmShwPagingMode, CPUMCTX2CORE(pCtx), GCPhysFault, errCode);
/*
* If we succeed, resume execution.
* Or, if fail in interpreting the instruction because we couldn't get the guest physical address
* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
* weird case. See @bugref{6043}.
*/
if ( rc == VINF_SUCCESS
|| rc == VERR_PAGE_NOT_PRESENT)
{
Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhysFault, (RTGCPTR)pCtx->rip));
goto ResumeExecution;
}
Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhysFault, (RTGCPTR)pCtx->rip));
break;
}
/* Exit qualification contains the linear address of the page fault. */
rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), GCPhysFault);
Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
/*
* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
*/
if ( rc == VINF_SUCCESS
|| rc == VERR_PAGE_NOT_PRESENT)
{
/* We've successfully synced our shadow pages, so let's just continue execution. */
Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, GCPhysFault, errCode));
goto ResumeExecution;
}
#ifdef VBOX_STRICT
if (rc != VINF_EM_RAW_EMULATE_INSTR)
#endif
/* Need to go back to the recompiler to emulate the instruction. */
break;
}
case SVM_EXIT_VINTR:
/* A virtual interrupt is about to be delivered, which means IF=1. */
goto ResumeExecution;
case SVM_EXIT_FERR_FREEZE:
case SVM_EXIT_INTR:
case SVM_EXIT_NMI:
case SVM_EXIT_SMI:
case SVM_EXIT_INIT:
/* External interrupt; leave to allow it to be dispatched again. */
break;
case SVM_EXIT_WBINVD:
case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
/* Skip instruction and continue directly. */
/* Continue execution.*/
goto ResumeExecution;
case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
{
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
{
Log2(("SVM: Rdtsc\n"));
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
{
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
{
Log2(("SVM: Rdtscp\n"));
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVLPG. */
{
Log2(("SVM: invlpg\n"));
/* Truly a pita. Why can't SVM give the same information as VT-x? */
if (rc == VINF_SUCCESS)
{
goto ResumeExecution; /* eip already updated */
}
break;
}
case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
{
switch (exitCode - SVM_EXIT_WRITE_CR0)
{
case 0:
break;
case 2:
break;
case 3:
break;
case 4:
break;
case 8:
break;
default:
AssertFailed();
}
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
break;
}
{
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
{
if ( !DBGFIsStepping(pVCpu)
{
/* Disable drx move intercepts. */
/* Save the host and load the guest debug state. */
goto ResumeExecution;
}
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
break;
}
{
if (!DBGFIsStepping(pVCpu))
{
/* Disable DRx move intercepts. */
/* Save the host and load the guest debug state. */
goto ResumeExecution;
}
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
break;
}
/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
case SVM_EXIT_IOIO: /* I/O instruction. */
{
if (RT_UNLIKELY(!uIOSize))
{
AssertFailed(); /* should be fatal. */
rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo r=ramshankar: would this really fall back to the recompiler and work? */
break;
}
if (IoExitInfo.n.u1STR)
{
/* Disassemble manually to deal with segment prefixes. */
if (rc == VINF_SUCCESS)
{
if (IoExitInfo.n.u1Type == 0)
{
}
else
{
}
}
else
}
else
{
if (IoExitInfo.n.u1Type == 0)
{
Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal,
uIOSize));
if (rc == VINF_IOM_R3_IOPORT_WRITE)
{
}
}
else
{
if (IOM_SUCCESS(rc))
{
/* Write back to the EAX register. */
Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal,
uIOSize));
}
else if (rc == VINF_IOM_R3_IOPORT_READ)
{
}
}
}
/*
* Handled the I/O return codes.
* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
*/
if (IOM_SUCCESS(rc))
{
/* Update EIP and continue execution. */
{
/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
{
/* IO operation lookup arrays. */
for (unsigned i = 0; i < 4; i++)
{
{
/* Clear all breakpoint status flags and set the one we just hit. */
/*
* Note: AMD64 Architecture Programmer's Manual 13.1:
* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared
* by software after the contents have been read.
*/
/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
/* Paranoia. */
/* Inject the exception. */
goto ResumeExecution;
}
}
}
goto ResumeExecution;
}
Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize,
VBOXSTRICTRC_VAL(rc)));
break;
}
#ifdef VBOX_STRICT
if (rc == VINF_IOM_R3_IOPORT_READ)
else if (rc == VINF_IOM_R3_IOPORT_WRITE)
else
{
|| rc == VINF_EM_RAW_EMULATE_INSTR
|| rc == VINF_EM_RAW_GUEST_TRAP
}
#endif
break;
}
case SVM_EXIT_HLT:
/* Check if external interrupts are pending; if so, don't switch back. */
goto ResumeExecution;
rc = VINF_EM_HALT;
break;
case SVM_EXIT_MWAIT_UNCOND:
Log2(("SVM: mwait\n"));
if ( rc == VINF_EM_HALT
|| rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
/* Check if external interrupts are pending; if so, don't switch back. */
if ( rc == VINF_SUCCESS
|| ( rc == VINF_EM_HALT
)
goto ResumeExecution;
}
AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
break;
case SVM_EXIT_MONITOR:
{
Log2(("SVM: monitor\n"));
if (rc == VINF_SUCCESS)
{
/* Update EIP and continue execution. */
goto ResumeExecution;
}
break;
}
case SVM_EXIT_VMMCALL:
if (rc == VINF_SUCCESS)
{
goto ResumeExecution; /* rip already updated. */
}
/* no break */
case SVM_EXIT_RSM:
case SVM_EXIT_INVLPGA:
case SVM_EXIT_VMRUN:
case SVM_EXIT_VMLOAD:
case SVM_EXIT_VMSAVE:
case SVM_EXIT_STGI:
case SVM_EXIT_CLGI:
case SVM_EXIT_SKINIT:
{
/* Unsupported instructions. */
goto ResumeExecution;
}
/* Emulate in ring-3. */
case SVM_EXIT_MSR:
{
/* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
{
{
/* Our patch code uses LSTAR for TPR caching. */
}
/* Skip the instruction and continue. */
/* Only resume if successful. */
goto ResumeExecution;
}
/*
* The Intel spec. claims there's an REX version of RDMSR that's slightly different,
* so we play safe by completely disassembling the instruction.
*/
STAM_COUNTER_INC((pvVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hm.s.StatExitRdmsr : &pVCpu->hm.s.StatExitWrmsr);
if (rc == VINF_SUCCESS)
{
/* EIP has been updated already. */
/* Only resume if successful. */
goto ResumeExecution;
}
AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pvVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr",
VBOXSTRICTRC_VAL(rc)));
break;
}
case SVM_EXIT_TASK_SWITCH: /* too complicated to emulate, so fall back to the recompiler */
{
/* Caused by an injected interrupt. */
{
case SVM_EVENT_EXTERNAL_IRQ:
case SVM_EVENT_NMI:
break;
default:
/* Exceptions and software interrupts can just be restarted. */
break;
}
}
break;
case SVM_EXIT_PAUSE:
case SVM_EXIT_MWAIT_ARMED:
break;
case SVM_EXIT_SHUTDOWN:
break;
case SVM_EXIT_IDTR_READ:
case SVM_EXIT_GDTR_READ:
case SVM_EXIT_LDTR_READ:
case SVM_EXIT_TR_READ:
case SVM_EXIT_IDTR_WRITE:
case SVM_EXIT_GDTR_WRITE:
case SVM_EXIT_LDTR_WRITE:
case SVM_EXIT_TR_WRITE:
case SVM_EXIT_CR0_SEL_WRITE:
default:
/* Unexpected exit codes. */
break;
}
end:
/*
* We are now going back to ring-3, so clear the forced action flag.
*/
/*
* Signal changes to the recompiler.
*/
/*
* If we executed vmrun and an external IRQ was pending, then we don't have to do a full sync the next time.
*/
if (exitCode == SVM_EXIT_INTR)
{
/* On the next entry we'll only sync the host context. */
}
else
{
/* On the next entry we'll sync everything. */
/** @todo we can do better than this */
/* Not in the VINF_PGM_CHANGE_MODE though! */
}
/* Translate into a less severe return code */
if (rc == VERR_EM_INTERPRETER)
/* Just set the correct state here instead of trying to catch every goto above. */
/* Restore interrupts if we exitted after disabling them. */
if (uOldEFlags != ~(RTCCUINTREG)0)
#endif
return VBOXSTRICTRC_TODO(rc);
}
/**
* Emulate simple mov tpr instruction.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest CPU context.
*/
{
int rc;
for (;;)
{
bool fPending;
if (!pPatch)
break;
{
case HMTPRINSTR_READ:
/* TPR caching in CR8 */
LogFlow(("Emulated read successfully\n"));
break;
case HMTPRINSTR_WRITE_REG:
case HMTPRINSTR_WRITE_IMM:
/* Fetch the new TPR value */
{
}
else
LogFlow(("Emulated write successfully\n"));
break;
default:
}
}
return VINF_SUCCESS;
}
/**
* Enters the AMD-V session.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCpu Pointer to the CPU info struct.
*/
{
LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.uCurrentAsid));
/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
return VINF_SUCCESS;
}
/**
* Leaves the AMD-V session.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest CPU context.
*/
{
#ifdef DEBUG
{
}
else
#endif
/* Save the guest debug state if necessary. */
{
/* Intercept all DRx reads and writes again. Changed later on. */
/* Resync the debug registers the next time. */
}
else
return VINF_SUCCESS;
}
/**
* Worker for Interprets INVLPG.
*
* @return VBox status code.
* @param pVCpu Pointer to the VMCPU.
* @param pCpu Pointer to the CPU info struct.
* @param pRegFrame Pointer to the register frame.
*/
{
if (RT_FAILURE(rc))
return VERR_EM_INTERPRETER;
{
case DISQPV_TYPE_IMMEDIATE:
case DISQPV_TYPE_ADDRESS:
return VERR_EM_INTERPRETER;
break;
default:
return VERR_EM_INTERPRETER;
}
/** @todo is addr always a flat linear address or ds based
* (in absence of segment override prefixes)????
*/
if (RT_SUCCESS(rc))
return VINF_SUCCESS;
return rc;
}
/**
* Interprets INVLPG.
*
* @returns VBox status code.
* @retval VINF_* Scheduling instructions.
* @retval VERR_EM_INTERPRETER Something we can't cope with.
* @retval VERR_* Fatal errors.
*
* @param pVM Pointer to the VM.
* @param pRegFrame Pointer to the register frame.
*
* @remarks Updates the EIP if an instruction was executed successfully.
*/
{
/*
* Only allow 32 & 64 bit code.
*/
{
{
if (RT_SUCCESS(rc))
return rc;
}
}
return VERR_EM_INTERPRETER;
}
/**
* Invalidates a guest page by guest virtual address.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param GCVirt Guest virtual address of the page to invalidate.
*/
{
/* Skip it if a TLB flush is already pending. */
if (!fFlushPending)
{
#if HC_ARCH_BITS == 32
/* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
if (CPUMIsGuestInLongMode(pVCpu))
else
#endif
{
}
}
return VINF_SUCCESS;
}
#if 0 /* obsolete, but left here for clarification. */
/**
* Invalidates a guest page by physical address.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param GCPhys Guest physical address of the page to invalidate.
*/
{
/* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
return VINF_SUCCESS;
}
#endif
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
/**
* Prepares for and executes VMRUN (64-bit guests from a 32-bit host).
*
* @returns VBox status code.
* @param HCPhysVMCBHost Physical address of host VMCB.
* @param HCPhysVMCB Physical address of the VMCB.
* @param pCtx Pointer to the guest CPU context.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
*/
DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVMCBHost, RTHCPHYS HCPhysVMCB, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
{
}
/**
* Executes the specified handler in 64-bit mode.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest CPU context.
* @param pfnHandler Pointer to the RC handler function.
* @param cbParam Number of parameters.
* @param paParam Array of 32-bit parameters.
*/
VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam,
{
int rc;
/* Disable interrupts. */
#endif
for (int i = (int)cbParam - 1; i >= 0; i--)
/* Call switcher. */
rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
return rc;
}
#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */