HWSVMR0.cpp revision 4e9f150666f4a6080824a98ee0c5881f39b1177c
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * HWACCM SVM - Host Context Ring 0.
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * available from http://www.virtualbox.org. This file is free software;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * you can redistribute it and/or modify it under the terms of the GNU
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * General Public License (GPL) as published by the Free Software
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * additional information or have any questions.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync/*******************************************************************************
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync* Header Files *
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync*******************************************************************************/
590bfe12ce22cd3716448fbb9f4dc51664bfe5e2vboxsync/*******************************************************************************
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync* Internal Functions *
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync*******************************************************************************/
223cf005b18af2c21352a70693ebaf0582f68ebcvboxsyncstatic int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync/*******************************************************************************
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync* Global Variables *
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync*******************************************************************************/
afed5ab737f4aacfae3fe73776f40e989190a7cavboxsync/* IO operation lookup arrays. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Sets up and activates AMD-V on the current CPU
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pCpu CPU info struct
0174432b2b1a760b89840ba696f7ba51def65dddvboxsync * @param pVM The VM to operate on. (can be NULL after a resume!!)
2daaccf68be3773aee600c5c3e48bcf5401418a6vboxsync * @param pvPageCpu Pointer to the global cpu page
0174432b2b1a760b89840ba696f7ba51def65dddvboxsync * @param pPageCpuPhys Physical address of the global cpu page
614cbe11a7e5588dc8d369e223174b1441a09359vboxsyncVMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
7666082b743c5e146a8cee6cc794ff4bc3fd0ffdvboxsync AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
7666082b743c5e146a8cee6cc794ff4bc3fd0ffdvboxsync /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
590bfe12ce22cd3716448fbb9f4dc51664bfe5e2vboxsync SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Turn on AMD-V in the EFER MSR. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Write the physical page address where the CPU will store the host state while executing the VM. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Deactivates AMD-V on the current CPU
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pCpu CPU info struct
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pvPageCpu Pointer to the global cpu page
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pPageCpuPhys Physical address of the global cpu page
22e281e75ed636601178296c6daebda8f1d17c59vboxsyncVMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
22e281e75ed636601178296c6daebda8f1d17c59vboxsync AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync /* Turn off AMD-V in the EFER MSR. */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync /* Invalidate host state physical address. */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * Does Ring-0 per VM AMD-V init.
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * @returns VBox status code.
7b80828e5760a8814fe6cd494d2715a4544fbddcvboxsync * @param pVM The VM to operate on.
22e281e75ed636601178296c6daebda8f1d17c59vboxsync pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
22e281e75ed636601178296c6daebda8f1d17c59vboxsync pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
22e281e75ed636601178296c6daebda8f1d17c59vboxsync pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
22e281e75ed636601178296c6daebda8f1d17c59vboxsync /* Allocate one page for the VM control block (VMCB). */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
d1cbbd799d8912978f5146960b6780f387bb414bvboxsync pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
c17f5c90f2cb60b38ecabebce128724c6ff2d036vboxsync /* Allocate one page for the host context */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Set all bits to intercept all IO accesses. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Set all bits to intercept all MSR accesses. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Erratum 170 which requires a forced TLB flush for each world switch:
b1c3cdef473df2fbc621d5da81acc82dbfb8a11avboxsync * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * All BH-G1/2 and DH-G1/2 models include a fix:
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Athlon X2: 0x6b 1/2
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Athlon 64: 0x7f 1
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Sempron: 0x7f 1/2
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Turion 64: 0x68 2
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Does Ring-0 per VM AMD-V termination.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM to operate on.
223cf005b18af2c21352a70693ebaf0582f68ebcvboxsync if (pVM->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (pVM->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
72ef2b9fc5ffc01d0dabd5052d6e8baa3a952773vboxsync if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Sets up AMD-V for the specified VM
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM to operate on.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Program the control fields. Most of them never have to be changed again. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * CR0/3/4 writes must be intercepted for obvious reasons.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
b978e5849454446957177fd47ee98609ab0457a6vboxsync pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Intercept all DRx reads and writes by default. Changed later on. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync * All breakpoints are automatically cleared when the VM exits.
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
6ae4b1c72625a8e5c369effea7f018b578d733c4vboxsync pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync /* With nested paging we don't care about invlpg anymore. */
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync /* Ignore the priority in the TPR; just deliver it when we tell it to. */
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync /* Set IO and MSR bitmap addresses. */
e50404712a2b5234c42bdf9740bddab5729ba188vboxsync pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
b978e5849454446957177fd47ee98609ab0457a6vboxsync pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync /* No LBR virtualization. */
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync /** The ASID must start at 1; the host uses 0. */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync /** Setup the PAT msr (nested paging only) */
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * Injects an event (trap or external interrupt)
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * @param pVM The VM to operate on.
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * @param pVMCB SVM control block
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * @param pCtx CPU Context
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * @param pIntInfo SVM interrupt info
6ae4b1c72625a8e5c369effea7f018b578d733c4vboxsyncinline void SVMR0InjectEvent(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
ebbb1f6c7e8bae363a4efda4b35b58c8467d24bcvboxsync Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
1843553dbdf4e46417158b4c6348c503adf10740vboxsync /* Set event injection state. */
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * Checks for pending guest interrupts and injects them
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * @returns VBox status code.
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * @param pVM The VM to operate on.
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * @param pVMCB SVM control block
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * @param pCtx CPU Context
1843553dbdf4e46417158b4c6348c503adf10740vboxsyncstatic int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("Reinjecting event %08x %08x at %RGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync /* When external interrupts are pending, we should exit the VM when IF is set. */
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
0e77737b0ba913683e614db11463b31ca67aacbevboxsync Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
0e77737b0ba913683e614db11463b31ca67aacbevboxsync /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
e08de24d4792d31b7f2aac29db5cb8840d940009vboxsync pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
e9a217d585085a6a6d129d27ca0d96a1b8e6d0eevboxsync pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
6ae4b1c72625a8e5c369effea7f018b578d733c4vboxsync /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
2d53f6e472561965d363674e17f48d3bdffc24d3vboxsync Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
0e77737b0ba913683e614db11463b31ca67aacbevboxsync STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Just continue */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync /* If a new event is pending, then dispatch it now. */
806d0b554daa555364af5f87bc96eccbe760db7avboxsync rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
806d0b554daa555364af5f87bc96eccbe760db7avboxsync Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
806d0b554daa555364af5f87bc96eccbe760db7avboxsync /* Clear the pending trap. */
806d0b554daa555364af5f87bc96eccbe760db7avboxsync /* Valid error codes. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync } /* if (interrupts can be dispatched) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Save the host state
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM to operate on.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Nothing to do here. */
79b24ef0ab7cd4a03a3571b3954c52ab8b573137vboxsync * Loads the guest state
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsync * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync * @returns VBox status code.
79b24ef0ab7cd4a03a3571b3954c52ab8b573137vboxsync * @param pVM The VM to operate on.
79b24ef0ab7cd4a03a3571b3954c52ab8b573137vboxsync * @param pCtx Guest context
e0b9d3c357adf9b7d05f55540e86f22943fc4b23vboxsyncVMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync /* Setup AMD SVM. */
5e797edc29f96c8367de4fbf5874171c24a89ba7vboxsync AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsync /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
5e797edc29f96c8367de4fbf5874171c24a89ba7vboxsync if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
79b24ef0ab7cd4a03a3571b3954c52ab8b573137vboxsync /* Guest CPU context: LDTR. */
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
22e281e75ed636601178296c6daebda8f1d17c59vboxsync /* Guest CPU context: TR. */
5e797edc29f96c8367de4fbf5874171c24a89ba7vboxsync if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
22e281e75ed636601178296c6daebda8f1d17c59vboxsync /* Guest CPU context: GDTR. */
e0b9d3c357adf9b7d05f55540e86f22943fc4b23vboxsync if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync /* Guest CPU context: IDTR. */
57399ab65e2825c324fb9dcb4642d4ae2c232509vboxsync if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
7bae75e0b207aa4d4cad2a951271ad1a0e8ab9fdvboxsync * Sysenter MSRs (unconditional)
79b24ef0ab7cd4a03a3571b3954c52ab8b573137vboxsync /* Control registers */
79b24ef0ab7cd4a03a3571b3954c52ab8b573137vboxsync if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync /* Always use #NM exceptions to load the FPU/XMM state on demand. */
7082d29724f6c3788977a51591b0379fd3acbf72vboxsync val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync /** @todo check if we support the old style mess correctly. */
f9147fe1eaa4e35287f8f39282c7f92f0d7de0b7vboxsync /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
f9147fe1eaa4e35287f8f39282c7f92f0d7de0b7vboxsync pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
5cf54b3ffeb7ee90685dcaec329ef71a729f5947vboxsync val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
f9147fe1eaa4e35287f8f39282c7f92f0d7de0b7vboxsync /* Always enable caching. */
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
6ae4b1c72625a8e5c369effea7f018b578d733c4vboxsync /* CR2 as well */
f9147fe1eaa4e35287f8f39282c7f92f0d7de0b7vboxsync if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync /* Save our shadow CR3 register. */
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
e149c362e69e5f0bbd82da11fd8163b2d29c3a72vboxsync if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync case PGMMODE_PROTECTED: /* Protected mode, no paging. */
f9147fe1eaa4e35287f8f39282c7f92f0d7de0b7vboxsync case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
f9147fe1eaa4e35287f8f39282c7f92f0d7de0b7vboxsync /** @todo use normal 32 bits paging */
7e960d3a0a8a3a84d7aba2cca45d72b1c31cc97bvboxsync case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync default: /* shut up gcc */
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync /* Debug registers. */
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
8e8844a522f5d335f177a0313b03067d79cce201vboxsync /* Sync the debug state now if any breakpoint is armed. */
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync /* Disable drx move intercepts. */
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync /* Save the host and load the guest debug state. */
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync int rc = CPUMR0LoadGuestDebugState(pVM, pCtx, false /* exclude DR6 */);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync /* EIP, ESP and EFLAGS */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync /* Set CPL */
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsync /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
e08de24d4792d31b7f2aac29db5cb8840d940009vboxsync /* vmrun will fail without MSR_K6_EFER_SVME. */
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsync pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsync /* 64 bits guest mode? */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync#if !defined(VBOX_WITH_64_BITS_GUESTS) || HC_ARCH_BITS != 64
46df4404c8dbbf3672e7aae8cd0b2770356e5b73vboxsync /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync /* TSC offset. */
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync /* Sync the various msrs for 64 bits mode. */
e08de24d4792d31b7f2aac29db5cb8840d940009vboxsync pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync /* Intercept X86_XCPT_DB if stepping is enabled */
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Done. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Runs guest code in an SVM VM.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM to operate on.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pCtx Guest context
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncVMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync bool fSyncTPR = false;
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync unsigned cResume = 0;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Safety precaution; looping for too long here can have a very bad effect on the host */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
e9a217d585085a6a6d129d27ca0d96a1b8e6d0eevboxsync /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
e9a217d585085a6a6d129d27ca0d96a1b8e6d0eevboxsync /* Irq inhibition is no longer active; clear the corresponding SVM state. */
5ace91141404400247438502a84a418fba00c8cfvboxsync /* Irq inhibition is no longer active; clear the corresponding SVM state. */
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync /* Check for pending actions that force us to go back to ring 3. */
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync /* Intercept X86_XCPT_DB if stepping is enabled */
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
5ace91141404400247438502a84a418fba00c8cfvboxsync /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
49748bb305bd71f672cd083af208f4bb08c5d6abvboxsync STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* When external interrupts are pending, we should exit the VM when IF is set. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* TPR caching using CR8 is only available in 64 bits mode */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
b9ca93dd1ad44cb8b27679dc5624be2f7b7f7af5vboxsync /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
b9ca93dd1ad44cb8b27679dc5624be2f7b7f7af5vboxsync /* TPR caching in CR8 */
7c3417bbf525c03163d54d151a277a981d5d61b6vboxsync int rc = PDMApicGetTPR(pVM, &u8LastVTPR, &fPending);
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
e9a217d585085a6a6d129d27ca0d96a1b8e6d0eevboxsync /* No interrupts are pending, so we don't need to be explicitely notified.
e9a217d585085a6a6d129d27ca0d96a1b8e6d0eevboxsync * There are enough world switches for detecting pending interrupts.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* All done! Let's start VM execution. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVM->hwaccm.s.idLastCpu, pCpu->idCpu));
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVM->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync * (until the actual world switch)
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync /* Force a TLB flush on VM entry. */
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
5ace91141404400247438502a84a418fba00c8cfvboxsync if (!pCpu->uCurrentASID || !pVM->hwaccm.s.uCurrentASID)
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync pVM->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVM->hwaccm.s.fForceTLBFlush);
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.fForceTLBFlush;
5ace91141404400247438502a84a418fba00c8cfvboxsync AssertMsg(pVM->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVM->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
5ace91141404400247438502a84a418fba00c8cfvboxsync AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync AssertMsg(pVM->hwaccm.s.uCurrentASID >= 1 && pVM->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVM->hwaccm.s.uCurrentASID));
5ace91141404400247438502a84a418fba00c8cfvboxsync pVMCB->ctrl.TLBCtrl.n.u32ASID = pVM->hwaccm.s.uCurrentASID;
247b55faa8d054157f2481e68caca36f4dc9542cvboxsync STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* In case we execute a goto ResumeExecution later on. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVM->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
3241f1be564f7351b07ce8a807673fa77a7847bcvboxsync | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
0975ae0a0fb615c945150c48e4a73187c1f4f84dvboxsync Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
42c1972c22e09797b4b24afbd0ec114ed076c37cvboxsync Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync pVM->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
5cf54b3ffeb7ee90685dcaec329ef71a729f5947vboxsync * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
5cf54b3ffeb7ee90685dcaec329ef71a729f5947vboxsync STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Reason for the VM exit */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
42c1972c22e09797b4b24afbd0ec114ed076c37cvboxsync Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
3241f1be564f7351b07ce8a807673fa77a7847bcvboxsync Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
3241f1be564f7351b07ce8a807673fa77a7847bcvboxsync Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
0975ae0a0fb615c945150c48e4a73187c1f4f84dvboxsync Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
0975ae0a0fb615c945150c48e4a73187c1f4f84dvboxsync Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1a25adaca81841abf5e6cdfed02eaff64941357dvboxsync Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
3e6d3b0af632bdcd931b5149915c7b8be1a732cdvboxsync Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
a11c569636fa6838bd423f4631a9660a5a84204bvboxsync Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
5b6e2c9a765c3c72295acc15791af8a700746956vboxsync Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
036d626c5d4722da925dc8292f9248a5e09b4588vboxsync Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
036d626c5d4722da925dc8292f9248a5e09b4588vboxsync Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
5cf54b3ffeb7ee90685dcaec329ef71a729f5947vboxsync Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
b3547e42ce5221377866e3fa041b3086b7cc1562vboxsync Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
5b6e2c9a765c3c72295acc15791af8a700746956vboxsync Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
b1c3cdef473df2fbc621d5da81acc82dbfb8a11avboxsync /* Let's first sync back eip, esp, and eflags. */
6778b34cb96bef0fef23ebc461eb6a429d2907c5vboxsync /* eax is saved/restore across the vmrun instruction */
6778b34cb96bef0fef23ebc461eb6a429d2907c5vboxsync pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
6778b34cb96bef0fef23ebc461eb6a429d2907c5vboxsync /* Can be updated behind our back in the nested paging case. */
614cbe11a7e5588dc8d369e223174b1441a09359vboxsync /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
614cbe11a7e5588dc8d369e223174b1441a09359vboxsync * System MSRs
614cbe11a7e5588dc8d369e223174b1441a09359vboxsync /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
b6d0062d24490dd07b4a424e5809b3b2bc910c5avboxsync /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
b6d0062d24490dd07b4a424e5809b3b2bc910c5avboxsync /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
fd69ca9bd8b533bfa9ade45c1c2ff3116854e84avboxsync /* Note! NOW IT'S SAFE FOR LOGGING! */
fd69ca9bd8b533bfa9ade45c1c2ff3116854e84avboxsync /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
b978e5849454446957177fd47ee98609ab0457a6vboxsync if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
b978e5849454446957177fd47ee98609ab0457a6vboxsync Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
5ace91141404400247438502a84a418fba00c8cfvboxsync /* Sync back DR6 as it could have been changed by hitting breakpoints. */
5ace91141404400247438502a84a418fba00c8cfvboxsync /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
5ace91141404400247438502a84a418fba00c8cfvboxsync /* Check if an injected event was interrupted prematurely. */
5ace91141404400247438502a84a418fba00c8cfvboxsync pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
5ace91141404400247438502a84a418fba00c8cfvboxsync && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
5a12b9772d9cf396a0ba7f54db399817ba7a65bavboxsync Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVM->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Error code present? (redundant) */
0f5d1b2abd9e82c7ee46f1327287c44856604bcbvboxsync pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitReasonNPF);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync rc = PDMApicSetTPR(pVM, pVMCB->ctrl.IntCtrl.n.u8VTPR);
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync /* Deal with the reason of the VM-exit. */
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync /* Pending trap. */
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log2(("Hardware/software interrupt %d\n", vector));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync /* Note that we don't support guest and host-initiated debugging at the same time. */
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Reinject the exception. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
28c928d1100d3b6a6d3506224cae25ad04732f73vboxsync /* Return to ring 3 to deal with the debug exit code. */
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync /* Continue execution. */
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
b978e5849454446957177fd47ee98609ab0457a6vboxsync uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync { /* A genuine pagefault.
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync * Forward the trap to the guest by injecting the exception and resuming execution.
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync /* Now we must update CR2. */
74735ec6edd6640eebac8885fbb2dadc86b89cf5vboxsync Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
74735ec6edd6640eebac8885fbb2dadc86b89cf5vboxsync /* Exit qualification contains the linear address of the page fault. */
74735ec6edd6640eebac8885fbb2dadc86b89cf5vboxsync /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
74735ec6edd6640eebac8885fbb2dadc86b89cf5vboxsync rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
74735ec6edd6640eebac8885fbb2dadc86b89cf5vboxsync Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
74735ec6edd6640eebac8885fbb2dadc86b89cf5vboxsync { /* We've successfully synced our shadow pages, so let's just continue execution. */
74735ec6edd6640eebac8885fbb2dadc86b89cf5vboxsync Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1171e4fb031146163c9a5a66bd9cbf3f2a5acdb6vboxsync { /* A genuine pagefault.
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync * Forward the trap to the guest by injecting the exception and resuming execution.
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync /* The error code might have been changed. */
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync /* Now we must update CR2. */
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync /* Need to go back to the recompiler to emulate the instruction. */
4b808cd07fd33b8a3edd0588dc43615686deb0e3vboxsync /* old style FPU error reporting needs some extra work. */
5b6e2c9a765c3c72295acc15791af8a700746956vboxsync /** @todo don't fall back to the recompiler, but do it manually. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
614cbe11a7e5588dc8d369e223174b1441a09359vboxsync case X86_XCPT_GP: /* General protection failure exception.*/
016bd61cdd14201a24f289559b0cc333d8c94748vboxsync case X86_XCPT_NP: /* Segment not present exception. */
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync Log(("Trap %x at %RGv esi=%x\n", vector, (RTGCPTR)pCtx->rip, pCtx->esi));
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync } /* switch (vector) */
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
2cd06fc737773d015b5268b9e4dfba5997915957vboxsync uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync Log(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Exit qualification contains the linear address of the page fault. */
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync /* Handle the pagefault trap for the nested shadow table. */
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync { /* We've successfully synced our shadow pages, so let's just continue execution. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync /* Need to go back to the recompiler to emulate the instruction. */
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync /* A virtual interrupt is about to be delivered, which means IF=1. */
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* External interrupt; leave to allow it to be dispatched again. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Skip instruction and continue directly. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Continue execution.*/
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
c39952b427f31961ee5281dcdd492ad847ca74bbvboxsync Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Update EIP and continue execution. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Update EIP and continue execution. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync AssertMsgFailed(("EMU: rdtsc failed with %Rrc\n", rc));
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1171e4fb031146163c9a5a66bd9cbf3f2a5acdb6vboxsync /* Truly a pita. Why can't SVM give the same information as VT-x? */
1171e4fb031146163c9a5a66bd9cbf3f2a5acdb6vboxsync rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1171e4fb031146163c9a5a66bd9cbf3f2a5acdb6vboxsync STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1171e4fb031146163c9a5a66bd9cbf3f2a5acdb6vboxsync case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1171e4fb031146163c9a5a66bd9cbf3f2a5acdb6vboxsync case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1171e4fb031146163c9a5a66bd9cbf3f2a5acdb6vboxsync case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
9b726ba798aabd1a27863e6f5cfeef1393bd198dvboxsync /* Check if a sync operation is pending. */
9b726ba798aabd1a27863e6f5cfeef1393bd198dvboxsync if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
9b726ba798aabd1a27863e6f5cfeef1393bd198dvboxsync && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
9b726ba798aabd1a27863e6f5cfeef1393bd198dvboxsync rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Must be set by PGMSyncCR3 */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync Assert(PGMGetGuestMode(pVM) <= PGMMODE_PROTECTED || pVM->hwaccm.s.fForceTLBFlush);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* EIP has been updated already. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Only resume if successful. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
3ecd8008b81f02a04220705ae0033142af363280vboxsync case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync /* EIP has been updated already. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Only resume if successful. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2cd06fc737773d015b5268b9e4dfba5997915957vboxsync case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxContextSwitch);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Disable drx move intercepts. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Save the host and load the guest debug state. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc = CPUMR0LoadGuestDebugState(pVM, pCtx, false /* exclude DR6 */);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync /* EIP has been updated already. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
d41220dff1068effe66bb6a11f444811ba58de40vboxsync /* Only resume if successful. */
d41220dff1068effe66bb6a11f444811ba58de40vboxsync Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
90466ec66c4fa6a8cd62f01fbf141b51189d33cbvboxsync case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
b9bd019c26def8e4d617c39121b62d7b8a826e96vboxsync case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
d41220dff1068effe66bb6a11f444811ba58de40vboxsync case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
d41220dff1068effe66bb6a11f444811ba58de40vboxsync case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
d41220dff1068effe66bb6a11f444811ba58de40vboxsync Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
90466ec66c4fa6a8cd62f01fbf141b51189d33cbvboxsync STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxContextSwitch);
d41220dff1068effe66bb6a11f444811ba58de40vboxsync /* Disable drx move intercepts. */
d41220dff1068effe66bb6a11f444811ba58de40vboxsync /* Save the host and load the guest debug state. */
d41220dff1068effe66bb6a11f444811ba58de40vboxsync rc = CPUMR0LoadGuestDebugState(pVM, pCtx, false /* exclude DR6 */);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* EIP has been updated already. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Only resume if successful. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /** @todo could use a lookup table here */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
b1c3cdef473df2fbc621d5da81acc82dbfb8a11avboxsync STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* normal in/out */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Write back to the EAX register. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Handled the I/O return codes.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Update EIP and continue execution. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
b45d66c0e496e2fd861479202f3d43aad592bd14vboxsync /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync for (unsigned i=0;i<4;i++)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync /* Clear all breakpoint status flags and set the one we just hit. */
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync /* Note: AMD64 Architecture Programmer's Manual 13.1:
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync * the contents have been read.
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
8b03ab0bcd5c238021bc8a43d887dd9d0870c0f5vboxsync /* Paranoia. */
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync /* Inject the exception. */
8b03ab0bcd5c238021bc8a43d887dd9d0870c0f5vboxsync Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
8b03ab0bcd5c238021bc8a43d887dd9d0870c0f5vboxsync Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
e85d76a7e5a047db3cdc8576ff5f412c7b73bbabvboxsync AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
e85d76a7e5a047db3cdc8576ff5f412c7b73bbabvboxsync Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
e85d76a7e5a047db3cdc8576ff5f412c7b73bbabvboxsync /** Check if external interrupts are pending; if so, don't switch back. */
e85d76a7e5a047db3cdc8576ff5f412c7b73bbabvboxsync && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Unsupported instructions. */
9b45880674da6f82ca27cc28b0272de3dd3cc7dfvboxsync Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Emulate in ring 3. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
5db1d52ffbcaa46c3d944c6c2d9c552306817d9avboxsync /* EIP has been updated already. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Only resume if successful. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
9b45880674da6f82ca27cc28b0272de3dd3cc7dfvboxsync case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = VINF_EM_RESET; /* Triple fault equals a reset. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Unexpected exit codes. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Signal changes for the recompiler. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* On the next entry we'll only sync the host context. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
6b022885f2cb6a55167609edecd89570cd80001dvboxsync /* On the next entry we'll sync everything. */
b45d66c0e496e2fd861479202f3d43aad592bd14vboxsync /** @todo we can do better than this */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Not in the VINF_PGM_CHANGE_MODE though! */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
e50404712a2b5234c42bdf9740bddab5729ba188vboxsync /* translate into a less severe return code */
74991d7531692858fd22acf371a7ee941567977cvboxsync * Enters the AMD-V session
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
57399ab65e2825c324fb9dcb4642d4ae2c232509vboxsync * @param pVM The VM to operate on.
3a21cbe769e7500039a2d17c794a911f7acb2dadvboxsync * @param pCpu CPU info struct
3a21cbe769e7500039a2d17c794a911f7acb2dadvboxsyncVMMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVM->hwaccm.s.idLastCpu, pVM->hwaccm.s.uCurrentASID));
6863baa4d9788245537c986d9caf02fb1893d2c6vboxsync /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
6863baa4d9788245537c986d9caf02fb1893d2c6vboxsync pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
74991d7531692858fd22acf371a7ee941567977cvboxsync * Leaves the AMD-V session
74991d7531692858fd22acf371a7ee941567977cvboxsync * @returns VBox status code.
74991d7531692858fd22acf371a7ee941567977cvboxsync * @param pVM The VM to operate on.
74991d7531692858fd22acf371a7ee941567977cvboxsync * @param pCtx CPU context
74991d7531692858fd22acf371a7ee941567977cvboxsync SVM_VMCB *pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
74991d7531692858fd22acf371a7ee941567977cvboxsync /* Save the guest debug state if necessary. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync CPUMR0SaveGuestDebugState(pVM, pCtx, false /* skip DR6 */);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Intercept all DRx reads and writes again. Changed later on. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Resync the debug registers the next time. */
0174432b2b1a760b89840ba696f7ba51def65dddvboxsync pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int svmR0InterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_SOURCE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @todo is addr always a flat linear address or ds based
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * (in absence of segment override prefixes)????
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Manually invalidate the page for the VM's TLB. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Interprets INVLPG
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @retval VINF_* Scheduling instructions.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @retval VERR_EM_INTERPRETER Something we can't cope with.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @retval VERR_* Fatal errors.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM handle.
b1c3cdef473df2fbc621d5da81acc82dbfb8a11avboxsync * @param pRegFrame The register frame.
c33db29e7b41467a35675031f5f5233839909083vboxsync * @param ASID Tagged TLB id for the guest
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Updates the EIP if an instruction was executed successfully.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Only allow 32 & 64 bits code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Assert(RT_FAILURE(rc) || Cpu.pCurInstr->opcode == OP_INVLPG);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (RT_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = svmR0InterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pRegFrame->rip += cbOp; /* Move on to the next instruction. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Invalidates a guest page
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM to operate on.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param GCVirt Page to invalidate
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncVMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | pVM->hwaccm.s.fForceTLBFlush;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Skip it if a TLB flush is already pending. */
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Invalidates a guest page by physical address
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM to operate on.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param GCPhys Page to invalidate
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncVMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */