HWACCMR0.cpp revision ce666b71b4eb6477625b0057689a08aaa7c11b64
/* $Id$ */
/** @file
* HWACCM - Host Context Ring 0.
*/
/*
* Copyright (C) 2006-2007 Sun Microsystems, Inc.
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
* Clara, CA 95054 USA or visit http://www.sun.com if you need
* additional information or have any questions.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_HWACCM
#include "HWACCMInternal.h"
#include <VBox/hwacc_vmx.h>
#include <VBox/hwacc_svm.h>
#include "HWVMXR0.h"
#include "HWSVMR0.h"
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
/*******************************************************************************
* Global Variables *
*******************************************************************************/
static struct
{
/** Ring 0 handlers for VT-x and AMD-V. */
DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
/** Maximum ASID allowed. */
struct
{
/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
bool fSupported;
/** Whether we're using SUPR0EnableVTx or not. */
bool fUsingSUPR0EnableVTx;
/** Host CR4 value (set by ring-0 VMX init) */
/** Host EFER value (set by ring-0 VMX init) */
/** VMX MSR values */
struct
{
} msr;
/* Last instruction error */
} vmx;
struct
{
/* HWCR msr (for diagnostics) */
/** SVM revision. */
/** SVM feature bits from cpuid 0x8000000a */
/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
bool fSupported;
} svm;
/** Saved error from detection */
struct
{
} cpuid;
bool fGlobalInit;
volatile bool fSuspended;
/**
* Does global Ring-0 HWACCM initialization.
*
* @returns VBox status code.
*/
VMMR0DECL(int) HWACCMR0Init(void)
{
int rc;
bool fAMDVPresent = false;
/* Fill in all callbacks with placeholders. */
HWACCMR0Globals.fGlobalInit = true;
/*
* Check for VT-x and AMD-V capabilities
*/
if (ASMHasCpuId())
{
/* Query AMD features. */
ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
)
{
/*
*/
if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
)
{
int aRc[RTCPUSET_MAX_CPUS];
/*
* First try use native kernel API for controlling VT-x.
* (This is only supported by some Mac OS X kernels atm.)
*/
if (rc != VERR_NOT_SUPPORTED)
{
AssertMsg(rc == VINF_SUCCESS || rc == VERR_VMX_IN_VMX_ROOT_MODE || rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
if (RT_SUCCESS(rc))
{
}
}
else
{
/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
/* Check the return code of all invocations. */
}
{
/* Reread in case we've changed it. */
if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK))
{
void *pvScatchPage;
/* VPID 16 bits ASID. */
if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
{
if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
}
{
if (RT_FAILURE(rc))
return rc;
/* Set revision dword at the beginning of the structure. */
*(uint32_t *)pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
/* Make sure we don't get rescheduled to another cpu during this probe. */
/*
* Check CR4.VMXE
*/
{
/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
* try to execute the VMX instructions...
*/
}
/* Enter VMX Root Mode */
if (RT_FAILURE(rc))
{
/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
*
* They should fix their code, but until they do we simply refuse to run.
*/
}
else
{
VMXDisable();
}
/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
RTR0MemObjFree(pScatchMemObj, false);
return HWACCMR0Globals.lLastError;
}
}
else
{
AssertFailed(); /* can't hit this case anymore */
}
}
#ifdef LOG_ENABLED
else
#endif
}
else
}
else
if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
)
{
/*
*/
)
{
int aRc[RTCPUSET_MAX_CPUS];
fAMDVPresent = true;
/* Query AMD features. */
ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
/* Check the return code of all invocations. */
if (RT_SUCCESS(rc))
#ifndef DEBUG_bird
AssertMsg(rc == VINF_SUCCESS || rc == VERR_SVM_IN_USE, ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
#endif
if (RT_SUCCESS(rc))
{
/* Read the HWCR msr for diagnostics. */
}
else
}
else
}
else
}
else
{
}
else
if (fAMDVPresent)
{
}
{
}
return VINF_SUCCESS;
}
/**
* Checks the error code array filled in for each cpu in the system.
*
* @returns VBox status code.
* @param paRc Error code array
* @param cErrorCodes Array size
* @param pidCpu Value of the first cpu that set an error (out)
*/
{
int rc = VINF_SUCCESS;
for (unsigned i=0;i<cErrorCodes;i++)
{
if (RTMpIsCpuOnline(i))
{
if (RT_FAILURE(paRc[i]))
{
*pidCpu = i;
break;
}
}
}
return rc;
}
/**
* Does global Ring-0 HWACCM termination.
*
* @returns VBox status code.
*/
VMMR0DECL(int) HWACCMR0Term(void)
{
int rc;
{
{
}
}
else
{
{
}
else
rc = VINF_SUCCESS;
{
int aRc[RTCPUSET_MAX_CPUS];
#ifdef VBOX_STRICT
#endif
}
/* Free the per-cpu pages used for VT-x and AMD-V */
{
{
}
}
}
return rc;
}
/**
* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
* is to be called on the target cpus.
*
* @param idCpu The identifier for the CPU the function is called on.
* @param pvUser1 The 1st user argument.
* @param pvUser2 The 2nd user argument.
*/
{
#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
#endif
Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
{
/*
* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
* Once the lock bit is set, this MSR can no longer be modified.
*/
|| ((val & (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK)) == MSR_IA32_FEATURE_CONTROL_VMXON) /* Some BIOSes forget to set the locked bit. */
)
{
/* MSR is not yet locked; we can change it ourselves here */
ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl | MSR_IA32_FEATURE_CONTROL_VMXON | MSR_IA32_FEATURE_CONTROL_LOCK);
}
else
}
else
if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
{
/* Check if SVM is disabled */
if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
{
/* Turn on SVM in the EFER MSR. */
if (val & MSR_K6_EFER_SVME)
{
}
else
{
/* Paranoia. */
if (val & MSR_K6_EFER_SVME)
{
/* Restore previous value. */
}
else
}
}
else
}
else
AssertFailed(); /* can't happen */
return;
}
/**
* Sets up HWACCM on all cpus.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*
*/
{
/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
return VERR_HWACCM_SUSPEND_PENDING;
if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, HWACCMSTATE_ENABLED, HWACCMSTATE_UNINITIALIZED))
{
int rc;
{
if (RT_SUCCESS(rc))
{
{
}
/* If the host provides a VT-x init API, then we'll rely on that for global init. */
}
else
}
else
{
int aRc[RTCPUSET_MAX_CPUS];
/* Allocate one page per cpu for the global vt-x and amd-v pages */
{
/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
if (RTMpIsCpuOnline(i))
{
rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
if (RT_FAILURE(rc))
return rc;
#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
#endif
}
}
{
/* Check the return code of all invocations. */
if (RT_SUCCESS(rc))
}
else
rc = VINF_SUCCESS;
}
return rc;
}
return VINF_SUCCESS;
}
/**
* Disable VT-x or AMD-V on the current CPU
*
* @returns VBox status code.
* @param pVM VM handle (can be 0!)
* @param idCpu The identifier for the CPU the function is called on.
*/
{
void *pvPageCpu;
Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
/* Make sure we start with a clean TLB. */
pCpu->cTLBFlushes = 0;
/* Should never happen */
{
AssertFailed();
return VERR_INTERNAL_ERROR;
}
if (RT_SUCCESS(rc))
pCpu->fConfigured = true;
return rc;
}
/**
* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
* is to be called on the target cpus.
*
* @param idCpu The identifier for the CPU the function is called on.
* @param pvUser1 The 1st user argument.
* @param pvUser2 The 2nd user argument.
*/
{
if (!HWACCMR0Globals.fGlobalInit)
{
AssertFailed();
return;
}
}
/**
* Disable VT-x or AMD-V on the current CPU
*
* @returns VBox status code.
* @param idCpu The identifier for the CPU the function is called on.
*/
{
void *pvPageCpu;
int rc;
Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
if (pCpu->fConfigured)
{
pCpu->fConfigured = false;
}
else
pCpu->uCurrentASID = 0;
return rc;
}
/**
* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
* is to be called on the target cpus.
*
* @param idCpu The identifier for the CPU the function is called on.
* @param pvUser1 The 1st user argument.
* @param pvUser2 The 2nd user argument.
*/
{
if (!HWACCMR0Globals.fGlobalInit)
{
AssertFailed();
return;
}
}
/**
* Called whenever a system power state change occurs.
*
* @param enmEvent Power event
* @param pvUser User argument
*/
{
#ifdef LOG_ENABLED
if (enmEvent == RTPOWEREVENT_SUSPEND)
SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
else
SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
#endif
if (enmEvent == RTPOWEREVENT_SUSPEND)
{
int aRc[RTCPUSET_MAX_CPUS];
int rc;
if (enmEvent == RTPOWEREVENT_SUSPEND)
{
{
/* Turn off VT-x or AMD-V on all CPUs. */
}
/* else nothing to do here for the local init case */
}
else
{
/* Reinit the CPUs from scratch as the suspend state might have messed with the MSRs. (lousy BIOSes as usual) */
rc = RTMpOnAll(HWACCMR0InitCPU, (void *)((HWACCMR0Globals.vmx.fSupported) ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX), aRc);
if (RT_SUCCESS(rc))
#ifdef LOG_ENABLED
if (RT_FAILURE(rc))
#endif
{
/* Turn VT-x or AMD-V back on on all CPUs. */
}
/* else nothing to do here for the local init case */
}
}
if (enmEvent == RTPOWEREVENT_RESUME)
}
/**
* Does Ring-0 per VM HWACCM initialization.
*
* This is mainly to check that the Host CPU mode is compatible
* with VMX.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
int rc;
#ifdef LOG_ENABLED
#endif
/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
return VERR_HWACCM_SUSPEND_PENDING;
{
#endif
}
{
/* Invalidate the last cpu we were running on. */
/* we'll aways increment this the first time (host uses ASID 0) */
}
/* Note: Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
/* Init a VT-x or AMD-V VM. */
return rc;
}
/**
* Does Ring-0 per VM HWACCM termination.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
int rc;
#ifdef LOG_ENABLED
#endif
/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
/* Terminate a VT-x or AMD-V VM. */
return rc;
}
/**
* Sets up a VT-x or AMD-V session
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
int rc;
/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
#ifdef LOG_ENABLED
#endif
{
/* On first entry we'll sync everything. */
}
/* Enable VT-x or AMD-V if local init is required. */
if (!HWACCMR0Globals.fGlobalInit)
{
}
/* Setup VT-x or AMD-V. */
/* Disable VT-x or AMD-V if local init was done before. */
if (!HWACCMR0Globals.fGlobalInit)
{
}
return rc;
}
/**
* Enters the VT-x or AMD-V session
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu VMCPUD id.
*/
{
int rc;
/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
/* Always load the guest's debug state on-demand. */
/* Always reload the host context and the guest's CR0 register. (!!!!) */
/* Setup the register and mask according to the current execution mode. */
else
/* Enable VT-x or AMD-V if local init is required. */
if (!HWACCMR0Globals.fGlobalInit)
{
}
/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
if (RT_SUCCESS(rc))
{
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
#endif
}
else
return rc;
}
/**
* Leaves the VT-x or AMD-V session
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu VMCPUD id.
*/
{
int rc;
/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
* or trash somebody else's FPU state.
*/
/* Save the guest FPU and XMM state if necessary. */
{
Log2(("CPUMR0SaveGuestFPU\n"));
}
/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
#ifdef RT_STRICT
&& RT_FAILURE(rc)))
{
}
#endif
/* Disable VT-x or AMD-V if local init was done before. */
if (!HWACCMR0Globals.fGlobalInit)
{
/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
}
return rc;
}
/**
* Runs guest code in a hardware accelerated VM.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
* @param pVCpu VMCPUD id.
*/
{
int rc;
#ifdef VBOX_STRICT
#endif
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
#endif
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
#endif
return rc;
}
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
/**
*
* @returns VBox status code.
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
* @param pCtx CPU context
*/
{
}
/**
* Save guest debug state (64 bits guest mode & 32 bits host only)
*
* @returns VBox status code.
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
* @param pCtx CPU context
*/
{
}
/**
* Test the 32->64 bits switcher
*
* @returns VBox status code.
* @param pVM VM handle.
*/
{
int rc;
else
return rc;
}
#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
/**
* Returns suspend status of the host
*
* @returns Suspend pending or not
*/
VMMR0DECL(bool) HWACCMR0SuspendPending()
{
}
/**
* Returns the cpu structure for the current cpu.
* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
*
* @returns cpu structure pointer
*/
{
}
/**
* Returns the cpu structure for the current cpu.
* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
*
* @returns cpu structure pointer
* @param idCpu id of the VCPU
*/
{
}
/**
* Returns the VMCPU of the current EMT thread.
*
* @param pVM The VM to operate on.
*/
{
/* RTMpCpuId had better be cheap. */
/** @todo optimize for large number of VCPUs when that becomes more common. */
{
return pVCpu;
}
return NULL;
}
/**
* Returns the VMCPU id of the current EMT thread.
*
* @param pVM The VM to operate on.
*/
{
if (pVCpu)
return 0;
}
/**
* Save a pending IO read.
*
* @param pVCpu The VMCPU to operate on.
* @param GCPtrRip Address of IO instruction
* @param GCPtrRipNext Address of the next instruction
* @param uPort Port address
* @param uAndVal And mask for saving the result in eax
* @param cbSize Read size
*/
VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
{
return;
}
/**
* Save a pending IO write.
*
* @param pVCpu The VMCPU to operate on.
* @param GCPtrRIP Address of IO instruction
* @param uPort Port address
* @param uAndVal And mask for fetching the result from eax
* @param cbSize Read size
*/
VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
{
return;
}
/**
* Disable VT-x if it's active *and* the current switcher turns off paging
*
* @returns VBox status code.
* @param pVM VM handle.
* @param pfVTxDisabled VT-x was disabled or not (out)
*/
{
*pfVTxDisabled = false;
|| !HWACCMR0Globals.fGlobalInit /* Local init implies the CPU is currently not in VMX root mode. */)
return VINF_SUCCESS; /* nothing to do */
switch(VMMGetSwitcher(pVM))
{
case VMMSWITCHER_32_TO_32:
case VMMSWITCHER_PAE_TO_PAE:
return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
case VMMSWITCHER_32_TO_PAE:
case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
case VMMSWITCHER_AMD64_TO_32:
case VMMSWITCHER_AMD64_TO_PAE:
break; /* unsafe switchers */
default:
AssertFailed();
return VERR_INTERNAL_ERROR;
}
void *pvPageCpu;
*pfVTxDisabled = true;
}
/**
* Reeable VT-x if was active *and* the current switcher turned off paging
*
* @returns VBox status code.
* @param pVM VM handle.
* @param fVTxDisabled VT-x was disabled or not
*/
{
if (!fVTxDisabled)
return VINF_SUCCESS; /* nothing to do */
void *pvPageCpu;
}
#ifdef VBOX_STRICT
/**
* Dumps a descriptor.
*
* @param pDesc Descriptor to dump.
* @param Sel Selector number.
* @param pszMsg Message to prepend the log entry with.
*/
{
/*
* Make variable description string.
*/
static struct
{
unsigned cch;
const char *psz;
} const s_aTypes[32] =
{
/* system */
# if HC_ARCH_BITS == 64
# else
# endif
/* non system */
};
char szMsg[128];
else
# if HC_ARCH_BITS == 64
else
# else
else
# endif
*psz = '\0';
/*
* Limit and Base and format the output.
*/
# if HC_ARCH_BITS == 64
# else
# endif
}
/**
* Formats a full register dump.
*
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
* @param pCtx The context to format.
*/
{
/*
* Format the flags.
*/
static struct
{
} aFlags[] =
{
};
char szEFlags[80];
for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
{
if (pszAdd)
{
*psz++ = ' ';
}
}
/*
* Format the registers.
*/
{
Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
"r14=%016RX64 r15=%016RX64\n"
"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
,
}
else
Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
,
(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
Log(("FPU:\n"
"FCW=%04x FSW=%04x FTW=%02x\n"
"FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
,
Log(("MSR:\n"
"EFER =%016RX64\n"
"PAT =%016RX64\n"
"STAR =%016RX64\n"
"CSTAR =%016RX64\n"
"LSTAR =%016RX64\n"
"SFMASK =%016RX64\n"
"KERNELGSBASE =%016RX64\n",
pCtx->msrKERNELGSBASE));
}
#endif /* VBOX_STRICT */
/* Dummy callback handlers. */
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
{
return VINF_SUCCESS;
}
VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}