HMSVMR0.cpp revision 9aadad141f2d4a7e0a56d4e8e46c6da52576dbb0
6a67d144095c31bbafed93cec1619590157335eajvergara * HM SVM (AMD-V) - Host Context Ring-0.
6a67d144095c31bbafed93cec1619590157335eajvergara * Copyright (C) 2013 Oracle Corporation
8cf870d281dc8c242f083d14dfef05f24aa5fceeJnRouvignac * This file is part of VirtualBox Open Source Edition (OSE), as
8cf870d281dc8c242f083d14dfef05f24aa5fceeJnRouvignac * available from http://www.virtualbox.org. This file is free software;
6a67d144095c31bbafed93cec1619590157335eajvergara * you can redistribute it and/or modify it under the terms of the GNU
6a67d144095c31bbafed93cec1619590157335eajvergara * General Public License (GPL) as published by the Free Software
6a67d144095c31bbafed93cec1619590157335eajvergara * Foundation, in version 2 as it comes in the "COPYING" file of the
6a67d144095c31bbafed93cec1619590157335eajvergara * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
8cf870d281dc8c242f083d14dfef05f24aa5fceeJnRouvignac * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
8cf870d281dc8c242f083d14dfef05f24aa5fceeJnRouvignac/*******************************************************************************
6a67d144095c31bbafed93cec1619590157335eajvergara* Header Files *
6a67d144095c31bbafed93cec1619590157335eajvergara*******************************************************************************/
6a67d144095c31bbafed93cec1619590157335eajvergara/*******************************************************************************
0877596da3b90efc5fd39171cef80a2fb8ec395ekenneth_suter* Defined Constants And Macros *
6a67d144095c31bbafed93cec1619590157335eajvergara*******************************************************************************/
6a67d144095c31bbafed93cec1619590157335eajvergara# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
53247d28ba99538f841a13ea2cde01c3faa3ef36kenneth_suter STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
6a67d144095c31bbafed93cec1619590157335eajvergara } while (0)
6a67d144095c31bbafed93cec1619590157335eajvergara# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
6a67d144095c31bbafed93cec1619590157335eajvergara/** If we decide to use a function table approach this can be useful to
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter * switch to a "static DECLCALLBACK(int)". */
6a67d144095c31bbafed93cec1619590157335eajvergara#define HMSVM_EXIT_DECL static int
6a67d144095c31bbafed93cec1619590157335eajvergara/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
7b6b125d52edabd5b1c9134feef7aeae0e69499ekenneth_suter * The CPU format of the segment attribute is described in X86DESCATTRBITS
7b6b125d52edabd5b1c9134feef7aeae0e69499ekenneth_suter * which is 16-bits (i.e. includes 4 bits of the segment limit).
6a67d144095c31bbafed93cec1619590157335eajvergara * The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
6a67d144095c31bbafed93cec1619590157335eajvergara * only the attribute bits and nothing else). Upper 4-bits are unused.
6a67d144095c31bbafed93cec1619590157335eajvergara#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0xf000) >> 4) )
6a67d144095c31bbafed93cec1619590157335eajvergara#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0x0f00) << 4) )
6a67d144095c31bbafed93cec1619590157335eajvergara/** @name Macros for loading, storing segment registers to/from the VMCB.
6a67d144095c31bbafed93cec1619590157335eajvergara Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
857225469c51bedb8c0566aa7757800cfaac4075kenneth_suter pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
0142bbb7ccb5d0efb942c20f5d27e5ddfb4344fdkenneth_suter pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
6a67d144095c31bbafed93cec1619590157335eajvergara pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
857225469c51bedb8c0566aa7757800cfaac4075kenneth_suter pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter/** Macro for checking and returning from the using function for
6a67d144095c31bbafed93cec1619590157335eajvergara * \#VMEXIT intercepts that maybe caused during delivering of another
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter * event in the guest. */
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
6a67d144095c31bbafed93cec1619590157335eajvergara int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT)) \
6a67d144095c31bbafed93cec1619590157335eajvergara } while (0)
c6c8254710feb80354037c2afb8d1cdae930a27akenneth_suter/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
6a67d144095c31bbafed93cec1619590157335eajvergara * instruction that exited. */
6a67d144095c31bbafed93cec1619590157335eajvergara if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
6a67d144095c31bbafed93cec1619590157335eajvergara } while (0)
6a67d144095c31bbafed93cec1619590157335eajvergara/** Assert that preemption is disabled or covered by thread-context hooks. */
6a67d144095c31bbafed93cec1619590157335eajvergara#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
a7d59bf59f3b588e70b86d920e0ab271496f4f06kenneth_suter/** Assert that we haven't migrated CPUs when thread-context hooks are not
6a67d144095c31bbafed93cec1619590157335eajvergara#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
6a67d144095c31bbafed93cec1619590157335eajvergara ("Illegal migration! Entered on CPU %u Current %u\n", \
6a67d144095c31bbafed93cec1619590157335eajvergara/** Exception bitmap mask for all contributory exceptions.
2401d3c2af505789c7c3b860a43e973f27731243jvergara * Page fault is deliberately excluded here as it's conditional as to whether
2401d3c2af505789c7c3b860a43e973f27731243jvergara * it's contributory or benign. Page faults are handled separately.
2401d3c2af505789c7c3b860a43e973f27731243jvergara#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_TS) \
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter/** @name VMCB Clean Bits.
2401d3c2af505789c7c3b860a43e973f27731243jvergara * These flags are used for VMCB-state caching. A set VMCB Clean Bit indicates
2401d3c2af505789c7c3b860a43e973f27731243jvergara * AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
2401d3c2af505789c7c3b860a43e973f27731243jvergara/** All intercepts vectors, TSC offset, PAUSE filter counter. */
6a67d144095c31bbafed93cec1619590157335eajvergara/** I/O permission bitmap, MSR permission bitmap. */
0877596da3b90efc5fd39171cef80a2fb8ec395ekenneth_suter/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
6a67d144095c31bbafed93cec1619590157335eajvergaraV_INTR_VECTOR. */
3e6ff045d382a718a951d6305c8910ffc268f893kenneth_suter/** Nested Paging: Nested CR3 (nCR3), PAT. */
6a67d144095c31bbafed93cec1619590157335eajvergara/** Control registers (CR0, CR3, CR4, EFER). */
0142bbb7ccb5d0efb942c20f5d27e5ddfb4344fdkenneth_suter/** Debug registers (DR6, DR7). */
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter/** GDT, IDT limit and base. */
6a67d144095c31bbafed93cec1619590157335eajvergara/** Segment register: CS, SS, DS, ES limit and base. */
6a67d144095c31bbafed93cec1619590157335eajvergara/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
6a67d144095c31bbafed93cec1619590157335eajvergara/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
6a67d144095c31bbafed93cec1619590157335eajvergaraPHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
6a67d144095c31bbafed93cec1619590157335eajvergara/** Mask of all valid VMCB Clean bits. */
6a67d144095c31bbafed93cec1619590157335eajvergara#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
6a67d144095c31bbafed93cec1619590157335eajvergara/** @name SVM transient.
6a67d144095c31bbafed93cec1619590157335eajvergara * A state structure for holding miscellaneous information across AMD-V
6a67d144095c31bbafed93cec1619590157335eajvergara * VMRUN/#VMEXIT operation, restored after the transition.
6a67d144095c31bbafed93cec1619590157335eajvergaratypedef struct SVMTRANSIENT
53247d28ba99538f841a13ea2cde01c3faa3ef36kenneth_suter /** The host's rflags/eflags. */
6a67d144095c31bbafed93cec1619590157335eajvergara /** The #VMEXIT exit code (the EXITCODE field in the VMCB). */
6a67d144095c31bbafed93cec1619590157335eajvergara /** The guest's TPR value used for TPR shadowing. */
6a67d144095c31bbafed93cec1619590157335eajvergara /** Alignment. */
6a67d144095c31bbafed93cec1619590157335eajvergara /** Whether the TSC_AUX MSR needs restoring on #VMEXIT. */
53247d28ba99538f841a13ea2cde01c3faa3ef36kenneth_suter /** Whether the #VMEXIT was caused by a page-fault during delivery of a
6a67d144095c31bbafed93cec1619590157335eajvergara * contributary exception or a page-fault. */
6a67d144095c31bbafed93cec1619590157335eajvergara /** Whether the TSC offset mode needs to be updated. */
6a67d144095c31bbafed93cec1619590157335eajvergaraAssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
6a67d144095c31bbafed93cec1619590157335eajvergaraAssertCompileMemberAlignment(SVMTRANSIENT, fRestoreTscAuxMsr, sizeof(uint64_t));
6a67d144095c31bbafed93cec1619590157335eajvergara * MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
6a67d144095c31bbafed93cec1619590157335eajvergara /** Reading this MSR causes a VM-exit. */
6a67d144095c31bbafed93cec1619590157335eajvergara /** Reading this MSR does not cause a VM-exit. */
6a67d144095c31bbafed93cec1619590157335eajvergara * MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
6a67d144095c31bbafed93cec1619590157335eajvergara /** Writing to this MSR causes a VM-exit. */
6a67d144095c31bbafed93cec1619590157335eajvergara /** Writing to this MSR does not cause a VM-exit. */
6a67d144095c31bbafed93cec1619590157335eajvergara/*******************************************************************************
2401d3c2af505789c7c3b860a43e973f27731243jvergara* Internal Functions *
2401d3c2af505789c7c3b860a43e973f27731243jvergara*******************************************************************************/
2401d3c2af505789c7c3b860a43e973f27731243jvergarastatic void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
2401d3c2af505789c7c3b860a43e973f27731243jvergarastatic void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
6a67d144095c31bbafed93cec1619590157335eajvergarastatic void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
7056ae8910decb0d96b430451ac58b99526eb0d9jvergaraHMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
c9d984b0d2c0fda320e79eb3868dd6fbeb1ffa34jvergaraHMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraHMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergaraDECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
6a67d144095c31bbafed93cec1619590157335eajvergara/*******************************************************************************
6a67d144095c31bbafed93cec1619590157335eajvergara* Global Variables *
6a67d144095c31bbafed93cec1619590157335eajvergara*******************************************************************************/
6a67d144095c31bbafed93cec1619590157335eajvergara/** Ring-0 memory object for the IO bitmap. */
6a67d144095c31bbafed93cec1619590157335eajvergara/** Physical address of the IO bitmap. */
6a67d144095c31bbafed93cec1619590157335eajvergara/** Virtual address of the IO bitmap. */
6a67d144095c31bbafed93cec1619590157335eajvergara * Sets up and activates AMD-V on the current CPU.
6a67d144095c31bbafed93cec1619590157335eajvergara * @returns VBox status code.
6a67d144095c31bbafed93cec1619590157335eajvergara * @param pCpu Pointer to the CPU info struct.
6a67d144095c31bbafed93cec1619590157335eajvergara * @param pVM Pointer to the VM (can be NULL after a resume!).
6a67d144095c31bbafed93cec1619590157335eajvergara * @param pvCpuPage Pointer to the global CPU page.
6a67d144095c31bbafed93cec1619590157335eajvergara * @param HCPhysCpuPage Physical address of the global CPU page.
6a67d144095c31bbafed93cec1619590157335eajvergaraVMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
6a67d144095c31bbafed93cec1619590157335eajvergara AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
6a67d144095c31bbafed93cec1619590157335eajvergara && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
6a67d144095c31bbafed93cec1619590157335eajvergara * We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
6a67d144095c31bbafed93cec1619590157335eajvergara /* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
c9d984b0d2c0fda320e79eb3868dd6fbeb1ffa34jvergara /* Turn on AMD-V in the EFER MSR. */
c9d984b0d2c0fda320e79eb3868dd6fbeb1ffa34jvergara ASMWrMsr(MSR_K6_EFER, u64HostEfer | MSR_K6_EFER_SVME);
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter /* Write the physical page address where the CPU will store the host state while executing the VM. */
6a67d144095c31bbafed93cec1619590157335eajvergara * Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
6a67d144095c31bbafed93cec1619590157335eajvergara * when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
6a67d144095c31bbafed93cec1619590157335eajvergara * upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
6a67d144095c31bbafed93cec1619590157335eajvergara * to flush the TLB with before using a new ASID.
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter * Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter * Deactivates AMD-V on the current CPU.
6a67d144095c31bbafed93cec1619590157335eajvergara * @returns VBox status code.
6a67d144095c31bbafed93cec1619590157335eajvergara * @param pCpu Pointer to the CPU info struct.
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter * @param pvCpuPage Pointer to the global CPU page.
0142bbb7ccb5d0efb942c20f5d27e5ddfb4344fdkenneth_suter * @param HCPhysCpuPage Physical address of the global CPU page.
6a67d144095c31bbafed93cec1619590157335eajvergaraVMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
6a67d144095c31bbafed93cec1619590157335eajvergara && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter /* Turn off AMD-V in the EFER MSR. */
6a67d144095c31bbafed93cec1619590157335eajvergara ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
0142bbb7ccb5d0efb942c20f5d27e5ddfb4344fdkenneth_suter /* Invalidate host state physical address. */
6a67d144095c31bbafed93cec1619590157335eajvergara * Does global AMD-V initialization (called during module initialization).
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter * @returns VBox status code.
0142bbb7ccb5d0efb942c20f5d27e5ddfb4344fdkenneth_suter * Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
6a67d144095c31bbafed93cec1619590157335eajvergara * once globally here instead of per-VM.
6a67d144095c31bbafed93cec1619590157335eajvergara int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
6a67d144095c31bbafed93cec1619590157335eajvergara g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
6a67d144095c31bbafed93cec1619590157335eajvergara g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
6a67d144095c31bbafed93cec1619590157335eajvergara /* Set all bits to intercept all IO accesses. */
6a67d144095c31bbafed93cec1619590157335eajvergara ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
2401d3c2af505789c7c3b860a43e973f27731243jvergara * Does global AMD-V termination (called during module termination).
6a67d144095c31bbafed93cec1619590157335eajvergara RTR0MemObjFree(g_hMemObjIOBitmap, false /* fFreeMappings */);
6a67d144095c31bbafed93cec1619590157335eajvergara * Frees any allocated per-VCPU structures for a VM.
6a67d144095c31bbafed93cec1619590157335eajvergara * @param pVM Pointer to the VM.
7b6b125d52edabd5b1c9134feef7aeae0e69499ekenneth_suter if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
6a67d144095c31bbafed93cec1619590157335eajvergara RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
6a67d144095c31bbafed93cec1619590157335eajvergara RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
6a67d144095c31bbafed93cec1619590157335eajvergara if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
6a67d144095c31bbafed93cec1619590157335eajvergara RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
6a67d144095c31bbafed93cec1619590157335eajvergara * Does per-VM AMD-V initialization.
6a67d144095c31bbafed93cec1619590157335eajvergara * @returns VBox status code.
6a67d144095c31bbafed93cec1619590157335eajvergara * @param pVM Pointer to the VM.
6a67d144095c31bbafed93cec1619590157335eajvergara * Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
6a67d144095c31bbafed93cec1619590157335eajvergara if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
6a67d144095c31bbafed93cec1619590157335eajvergara Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
6a67d144095c31bbafed93cec1619590157335eajvergara * Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
7b6b125d52edabd5b1c9134feef7aeae0e69499ekenneth_suter pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
6a67d144095c31bbafed93cec1619590157335eajvergara * Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
5b3741e0620fd2baaa974cecc2c2d953bb7d4fbbkenneth_suter * FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
6a67d144095c31bbafed93cec1619590157335eajvergara rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
6a67d144095c31bbafed93cec1619590157335eajvergara pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
6a67d144095c31bbafed93cec1619590157335eajvergara pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
7056ae8910decb0d96b430451ac58b99526eb0d9jvergara * Allocate one page for the guest-state VMCB.
goto failure_cleanup;
* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
goto failure_cleanup;
pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
return VINF_SUCCESS;
return rc;
return VINF_SUCCESS;
static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
unsigned ulBit;
AssertFailed();
#ifdef HMSVM_ALWAYS_TRAP_PF
#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
/* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
return rc;
bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
if (!fFlushPending)
/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
return VINF_SUCCESS;
* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
bool fNewAsid = false;
fNewAsid = true;
if (fNewAsid)
bool fHitASIDLimit = false;
fHitASIDLimit = true;
if ( !fHitASIDLimit
("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
#ifdef VBOX_WITH_STATISTICS
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
return rc;
#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
u64GuestCR0 |= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
bool fInterceptNM = false;
bool fInterceptMF = false;
u64GuestCR0 |= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
fInterceptMF = true;
if (fInterceptNM)
if (fInterceptMF)
case PGMMODE_REAL:
AssertFailed();
#ifdef VBOX_ENABLE_64_BITS_GUESTS
AssertFailed();
AssertFailed();
return VINF_SUCCESS;
/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
Assert((pCtx->dr[6] & X86_DR6_RA1_MASK) == X86_DR6_RA1_MASK); Assert((pCtx->dr[6] & X86_DR6_RAZ_MASK) == 0);
Assert((pCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); Assert((pCtx->dr[7] & X86_DR7_RAZ_MASK) == 0);
bool fInterceptDB = false;
bool fInterceptMovDRx = false;
if (fStepping)
fInterceptDB = true;
fInterceptDB = true;
fInterceptMovDRx = true;
fInterceptMovDRx = true;
if (fInterceptDB)
if (fInterceptMovDRx)
return VINF_SUCCESS;
bool fPendingIntr;
/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
if (fPendingIntr)
/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
if (fPendingIntr)
return rc;
#ifndef VBOX_ENABLE_64_BITS_GUESTS
return VINF_SUCCESS;
return VINF_SUCCESS;
return VINF_SUCCESS;
switch (enmEvent)
case RTTHREADCTXEVENT_RESUMED:
Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
return VINF_SUCCESS;
AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
/* hmR0SvmLoadGuestDebugRegs() must be called -after- updating guest RFLAGS as the RFLAGS may need to be changed. */
AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
/* All the guest state bits should be loaded except maybe the host context and shared host/guest bits. */
|| !(pVCpu->hm.s.fContextUseFlags & ~(HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE)),
Log4(("Load: CS:RIP=%04x:%RX64 EFL=%#x SS:RSP=%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->ss, pCtx->rsp));
return rc;
* Avoid reloading the guest state on longjmp reentrants and do it lazily just before executing the guest.
* This only helps when we get rescheduled more than once to a different host CPU on a longjmp trip before
return VINF_SUCCESS;
* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
#ifdef VBOX_STRICT
* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
#ifdef VBOX_STRICT
/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
* (longjmp/exit-to-r3) in VT-x which is not efficient. */
/* VMMRZCallRing3() already makes sure we never get called as a result of an longjmp due to an assertion, */
/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
Event.u = 0;
switch (uVector)
case X86_XCPT_PF:
case X86_XCPT_DF:
case X86_XCPT_TS:
case X86_XCPT_NP:
case X86_XCPT_SS:
case X86_XCPT_GP:
case X86_XCPT_AC:
Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo */, NULL /* pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
switch (uVectorType)
case SVM_EVENT_EXTERNAL_IRQ:
case SVM_EVENT_NMI:
case SVM_EVENT_SOFTWARE_INT:
case SVM_EVENT_EXCEPTION:
* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
return uIntrState;
pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
Event.u = 0;
if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
if (!fIntShadow)
* Check if the guest can receive external interrupts (PIC/APIC). Once we do PDMGetInterrupt() we -must- deliver
* the interrupt ASAP. We must not execute any guest code until we inject the interrupt which is why it is
if ( !fBlockInt
&& !fIntShadow)
Event.u = 0;
#ifdef VBOX_STRICT
#ifdef VBOX_WITH_STATISTICS
#ifdef VBOX_STRICT
int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
return rc;
int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
return rc;
return VINF_EM_PENDING_REQUEST;
return VINF_PGM_POOL_FLUSH_PENDING;
return VINF_EM_RAW_TO_R3;
return VINF_SUCCESS;
* clearing the common-state (TRPM/forceflags), we must undo those changes so
DECLINLINE(int) hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
return rc;
* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
return VINF_EM_RAW_TO_R3;
return VINF_EM_RAW_INTERRUPT;
/* Indicate the start of guest execution. No more longjmps or returns to ring-3 from this point!!! */
return VINF_SUCCESS;
DECLINLINE(void) hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
* Re-enable nested paging (automatically disabled on every VM-exit). See AMD spec. 15.25.3 "Enabling Nested Paging".
* We avoid changing the corresponding VMCB Clean Bit as we're not changing it to a different value since the previous run.
#ifdef HMSVM_SYNC_FULL_GUEST_STATE
pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT; /* Preemption might set this, nothing to do on AMD-V. */
AssertMsg(!pVCpu->hm.s.fContextUseFlags, ("fContextUseFlags =%#x\n", pVCpu->hm.s.fContextUseFlags));
/* If VMCB Clean Bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB-shootdowns, set this across the world switch. */
* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
#ifdef VBOX_WITH_KERNEL_USING_XMM
return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
DECLINLINE(void) hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB-shootdowns. */
ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for TLB-shootdowns. */
pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
for (;; cLoops++)
/* Preparatory work for running guest code, this may return to ring-3 for some last minute updates. */
* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
|| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
return rc;
return rc;
* The ordering of the case labels is based on most-frequently-occurring VM-exits for most guests under
case SVM_EXIT_NPF:
case SVM_EXIT_IOIO:
case SVM_EXIT_RDTSC:
case SVM_EXIT_RDTSCP:
case SVM_EXIT_CPUID:
case SVM_EXIT_MONITOR:
case SVM_EXIT_MWAIT:
case SVM_EXIT_HLT:
case SVM_EXIT_READ_CR0:
case SVM_EXIT_READ_CR3:
case SVM_EXIT_READ_CR4:
case SVM_EXIT_WRITE_CR0:
case SVM_EXIT_WRITE_CR3:
case SVM_EXIT_WRITE_CR4:
case SVM_EXIT_WRITE_CR8:
case SVM_EXIT_VINTR:
case SVM_EXIT_INTR:
case SVM_EXIT_FERR_FREEZE:
case SVM_EXIT_NMI:
case SVM_EXIT_MSR:
case SVM_EXIT_INVLPG:
case SVM_EXIT_WBINVD:
case SVM_EXIT_INVD:
case SVM_EXIT_RDPMC:
case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
case SVM_EXIT_TASK_SWITCH:
case SVM_EXIT_VMMCALL:
case SVM_EXIT_SHUTDOWN:
case SVM_EXIT_SMI:
case SVM_EXIT_INIT:
* We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
return VERR_SVM_UNEXPECTED_EXIT;
case SVM_EXIT_INVLPGA:
case SVM_EXIT_RSM:
case SVM_EXIT_VMRUN:
case SVM_EXIT_VMLOAD:
case SVM_EXIT_VMSAVE:
case SVM_EXIT_STGI:
case SVM_EXIT_CLGI:
case SVM_EXIT_SKINIT:
#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
Event.u = 0;
case X86_XCPT_DE:
case X86_XCPT_BP:
case X86_XCPT_UD:
case X86_XCPT_NP:
case X86_XCPT_SS:
case X86_XCPT_GP:
AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
return VERR_SVM_UNEXPECTED_XCPT_EXIT;
Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
return VINF_SUCCESS;
return VERR_SVM_UNKNOWN_EXIT;
#ifdef DEBUG
# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
# define HMSVM_ASSERT_PREEMPT_CPUID() \
RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { } while(0)
return VERR_EM_INTERPRETER;
return VERR_EM_INTERPRETER;
return rc;
return rc;
Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
return VERR_EM_INTERPRETER;
Event.u = 0;
Event.u = 0;
DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
Event.u = 0;
Event.u = 0;
Event.u = 0;
Event.u = 0;
bool fPending;
if (!pPatch)
case HMTPRINSTR_READ:
case HMTPRINSTR_WRITE_REG:
case HMTPRINSTR_WRITE_IMM:
return VERR_SVM_UNEXPECTED_PATCH_TYPE;
return VINF_SUCCESS;
switch (uVector)
case X86_XCPT_GP:
case X86_XCPT_SS:
case X86_XCPT_NP:
case X86_XCPT_TS:
case X86_XCPT_DE:
static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
#ifdef VBOX_STRICT
Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
switch (enmReflect)
case SVMREFLECTXCPT_XCPT:
/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
case SVMREFLECTXCPT_DF:
case SVMREFLECTXCPT_TF:
return rc;
/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
return VINF_EM_RAW_INTERRUPT;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
return rc;
AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
return rc;
return VINF_EM_RESET;
AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3,
return rc;
AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x CRx=%#RX64\n",
return rc;
HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
return VINF_SUCCESS;
int rc;
return rc;
AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
/* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
return rc;
return VINF_SUCCESS;
/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
return rc;
static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
return VERR_EM_INTERPRETER;
HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
#ifdef VBOX_STRICT
/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
#ifdef VBOX_HM_WITH_GUEST_PATCHING
|| (u32ErrCode & (X86_TRAP_PF_P | X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P | X86_TRAP_PF_RSVD)) /* MMIO page. */
if (!pPatch)
return VINF_EM_HM_PATCH_TPR_INSTR;
int rc;
VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
return rc;
rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
return rc;
pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one before reentry. */
/* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
/* Deliver the pending interrupt via hmR0SvmPreRunGuest()->hmR0SvmInjectEventVmcb() and resume guest execution. */
return VINF_SUCCESS;
#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery. Kept pending u8Vector=%#x\n", Event.n.u8Vector));
return VERR_EM_INTERPRETER;
return VINF_SUCCESS;
Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
return VINF_SUCCESS;
#ifdef VBOX_HM_WITH_GUEST_PATCHING
if (!pPatch)
return VINF_EM_HM_PATCH_TPR_INSTR;
Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
return rc;
return VINF_SUCCESS;
return rc;
#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
return VINF_SUCCESS;
return VINF_SUCCESS;
return VERR_EM_INTERPRETER;
return VINF_SUCCESS;
/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
return rc;