HMR0Mixed.mac revision b4973420a07afec39ececea9026a746b44685170
; Included by HMR0A.asm with RT_ARCH_AMD64 defined or undefined.
; available from http://www.virtualbox.org. This file is free software;
; you can redistribute it and/or modify it under the terms of the GNU
; Darwin (Mavericks) uses IDTR limit to store the CPUID so we need to restore it always. See @bugref{6875}.
mov [ss:xDI + CPUMCTX.eax], eax
mov [ss:xDI + CPUMCTX.ebx], ebx
mov [ss:xDI + CPUMCTX.ecx], ecx
mov [ss:xDI + CPUMCTX.edx], edx
mov [ss:xDI + CPUMCTX.esi], esi
mov [ss:xDI + CPUMCTX.ebp], ebp
mov [ss:xDI + CPUMCTX.cr2], xAX
mov dword [ss:xDI + CPUMCTX.edi], eax
pop dword [ss:xDI + CPUMCTX.edi] ; The guest edi we pushed above.
add xAX, [xSP + 2] ; eax <- GDTR.address + descriptor offset.
; vmread's will fail (only eflags.cf=1 will be set) but that shouldn't cause any
mov ecx, [ss:xDX + VMCSCACHE.Read.cValidEntries]
mov eax, [ss:xDX + VMCSCACHE.Read.aField + xCX * 4]
vmread [ss:xDX + VMCSCACHE.Read.aFieldVal + xCX * 8], xAX
; * Prepares for and executes VMLAUNCH/VMRESUME (32 bits guest mode)
; * @param fResume x86:[ebp+8], msc:rcx,gcc:rdi vmlauch/vmresume
mov ecx, [xBX + VMCSCACHE.Write.cValidEntries]
mov eax, [xBX + VMCSCACHE.Write.aField + xCX * 4]
vmwrite xAX, [xBX + VMCSCACHE.Write.aFieldVal + xCX * 8]
mov dword [xBX + VMCSCACHE.Write.cValidEntries], 0
; VT-x only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
mov xBX, [xSI + CPUMCTX.cr2]
mov eax, [xSI + CPUMCTX.eax]
mov ebx, [xSI + CPUMCTX.ebx]
mov ecx, [xSI + CPUMCTX.ecx]
mov edx, [xSI + CPUMCTX.edx]
mov ebp, [xSI + CPUMCTX.ebp]
mov edi, [xSI + CPUMCTX.edi]
mov esi, [xSI + CPUMCTX.esi]
mov edi, [xSI + CPUMCTX.edi]
mov esi, [xSI + CPUMCTX.esi]
mov qword [xDI + CPUMCTX.eax], rax
mov qword [xDI + CPUMCTX.ebx], rbx
mov qword [xDI + CPUMCTX.ecx], rcx
mov qword [xDI + CPUMCTX.edx], rdx
mov qword [xDI + CPUMCTX.esi], rsi
mov qword [xDI + CPUMCTX.ebp], rbp
mov qword [xDI + CPUMCTX.r8], r8
mov qword [xDI + CPUMCTX.r9], r9
mov qword [xDI + CPUMCTX.r10], r10
mov qword [xDI + CPUMCTX.r11], r11
mov qword [xDI + CPUMCTX.r12], r12
mov qword [xDI + CPUMCTX.r13], r13
mov qword [xDI + CPUMCTX.r14], r14
mov qword [xDI + CPUMCTX.r15], r15
mov qword [xDI + CPUMCTX.cr2], rax
mov qword [xDI + CPUMCTX.edi], rax
add xAX, [xSP + 2] ; eax <- GDTR.address + descriptor offset.
LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
LOADHOSTMSREX MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
LOADHOSTMSREX MSR_K6_STAR, CPUMCTX.msrSTAR
LOADHOSTMSREX MSR_K8_LSTAR, CPUMCTX.msrLSTAR
; vmread's will fail (only eflags.cf=1 will be set) but that shouldn't cause any
mov ecx, [xDX + VMCSCACHE.Read.cValidEntries]
mov eax, [xDX + VMCSCACHE.Read.aField + xCX * 4]
vmread [xDX + VMCSCACHE.Read.aFieldVal + xCX * 8], xAX
; * Prepares for and executes VMLAUNCH/VMRESUME (64 bits guest mode)
; * @param fResume msc:rcx, gcc:rdi vmlauch/vmresume
mov ecx, [xBX + VMCSCACHE.Write.cValidEntries]
mov eax, [xBX + VMCSCACHE.Write.aField + xCX * 4]
vmwrite xAX, [xBX + VMCSCACHE.Write.aFieldVal + xCX * 8]
mov dword [xBX + VMCSCACHE.Write.cValidEntries], 0
LOADGUESTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR
LOADGUESTMSR MSR_K6_STAR, CPUMCTX.msrSTAR
LOADGUESTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
LOADGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
; VT-x only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
mov rbx, qword [xSI + CPUMCTX.cr2]
mov rax, qword [xSI + CPUMCTX.eax]
mov rbx, qword [xSI + CPUMCTX.ebx]
mov rcx, qword [xSI + CPUMCTX.ecx]
mov rdx, qword [xSI + CPUMCTX.edx]
mov rbp, qword [xSI + CPUMCTX.ebp]
mov r8, qword [xSI + CPUMCTX.r8]
mov r9, qword [xSI + CPUMCTX.r9]
mov r10, qword [xSI + CPUMCTX.r10]
mov r11, qword [xSI + CPUMCTX.r11]
mov r12, qword [xSI + CPUMCTX.r12]
mov r13, qword [xSI + CPUMCTX.r13]
mov r14, qword [xSI + CPUMCTX.r14]
mov r15, qword [xSI + CPUMCTX.r15]
mov rdi, qword [xSI + CPUMCTX.edi]
mov rsi, qword [xSI + CPUMCTX.esi]
mov rdi, qword [xSI + CPUMCTX.edi]
mov rsi, qword [xSI + CPUMCTX.esi]
mov ebx, [xSI + CPUMCTX.ebx]
mov ecx, [xSI + CPUMCTX.ecx]
mov edx, [xSI + CPUMCTX.edx]
mov edi, [xSI + CPUMCTX.edi]
mov ebp, [xSI + CPUMCTX.ebp]
mov esi, [xSI + CPUMCTX.esi]
; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch.
mov [ss:xAX + CPUMCTX.ebx], ebx
mov [ss:xAX + CPUMCTX.ecx], ecx
mov [ss:xAX + CPUMCTX.edx], edx
mov [ss:xAX + CPUMCTX.esi], esi
mov [ss:xAX + CPUMCTX.edi], edi
mov [ss:xAX + CPUMCTX.ebp], ebp
mov rbx, qword [xSI + CPUMCTX.ebx]
mov rcx, qword [xSI + CPUMCTX.ecx]
mov rdx, qword [xSI + CPUMCTX.edx]
mov rdi, qword [xSI + CPUMCTX.edi]
mov rbp, qword [xSI + CPUMCTX.ebp]
mov r8, qword [xSI + CPUMCTX.r8]
mov r9, qword [xSI + CPUMCTX.r9]
mov r10, qword [xSI + CPUMCTX.r10]
mov r11, qword [xSI + CPUMCTX.r11]
mov r12, qword [xSI + CPUMCTX.r12]
mov r13, qword [xSI + CPUMCTX.r13]
mov r14, qword [xSI + CPUMCTX.r14]
mov r15, qword [xSI + CPUMCTX.r15]
mov rsi, qword [xSI + CPUMCTX.esi]
; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch.
mov qword [rax + CPUMCTX.ebx], rbx
mov qword [rax + CPUMCTX.ecx], rcx
mov qword [rax + CPUMCTX.edx], rdx
mov qword [rax + CPUMCTX.esi], rsi
mov qword [rax + CPUMCTX.edi], rdi
mov qword [rax + CPUMCTX.ebp], rbp
mov qword [rax + CPUMCTX.r8], r8
mov qword [rax + CPUMCTX.r9], r9
mov qword [rax + CPUMCTX.r10], r10
mov qword [rax + CPUMCTX.r11], r11
mov qword [rax + CPUMCTX.r12], r12
mov qword [rax + CPUMCTX.r13], r13
mov qword [rax + CPUMCTX.r14], r14
mov qword [rax + CPUMCTX.r15], r15