HMR0.cpp revision 1bc500a8f68a50c718620e24d730ac17b56d4d26
/* $Id$ */
/** @file
* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
*/
/*
* Copyright (C) 2006-2013 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_HM
#include "HMInternal.h"
#include <iprt/asm-amd64-x86.h>
#include "HWVMXR0.h"
#include "HWSVMR0.h"
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
/*******************************************************************************
* Structures and Typedefs *
*******************************************************************************/
/**
* This is used to manage the status code of a RTMpOnAll in HM.
*/
typedef struct HMR0FIRSTRC
{
/** The status code. */
/** The ID of the CPU reporting the first failure. */
} HMR0FIRSTRC;
/** Pointer to a first return code structure. */
typedef HMR0FIRSTRC *PHMR0FIRSTRC;
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/**
* Global data.
*/
static struct
{
/** Per CPU globals. */
/** @name Ring-0 method table for AMD-V and VT-x specific operations.
* @{ */
DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
bool fEnabledByHost));
DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
/** @} */
/** Maximum ASID allowed. */
/** VT-x data. */
struct
{
/** Set to by us to indicate VMX is supported by the CPU. */
bool fSupported;
/** Whether we're using SUPR0EnableVTx or not. */
bool fUsingSUPR0EnableVTx;
/** Whether we're using the preemption timer or not. */
bool fUsePreemptTimer;
/** The shift mask employed by the VMX-Preemption timer. */
/** Host CR4 value (set by ring-0 VMX init) */
/** Host EFER value (set by ring-0 VMX init) */
/** VMX MSR values */
struct
{
} msr;
/* Last instruction error */
} vmx;
/** AMD-V information. */
struct
{
/* HWCR MSR (for diagnostics) */
/** SVM revision. */
/** SVM feature bits from cpuid 0x8000000a */
/** Set by us to indicate SVM is supported by the CPU. */
bool fSupported;
} svm;
/** Saved error from detection */
struct
{
} cpuid;
* enabled and disabled each time it's used to execute guest code. */
bool fGlobalInit;
/** Indicates whether the host is suspending or not. We'll refuse a few
* actions when the host is being suspended to speed up the suspending and
* avoid trouble. */
volatile bool fSuspended;
/** Whether we've already initialized all CPUs.
* @remarks We could check the EnableAllCpusOnce state, but this is
* simpler and hopefully easier to understand. */
bool fEnabled;
/** Serialize initialization in HMR0EnableAllCpus. */
} g_HvmR0;
/**
* Initializes a first return code structure.
*
* @param pFirstRc The structure to init.
*/
{
}
/**
* Try set the status code (success ignored).
*
* @param pFirstRc The first return code structure.
* @param rc The status code.
*/
{
if ( RT_FAILURE(rc)
}
/**
* Get the status code of a first return code structure.
*
* @returns The status code; VINF_SUCCESS or error status, no informational or
* warning errors.
* @param pFirstRc The first return code structure.
*/
{
}
#ifdef VBOX_STRICT
/**
* Get the CPU ID on which the failure status code was reported.
*
* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
* @param pFirstRc The first return code structure.
*/
{
}
#endif /* VBOX_STRICT */
/** @name Dummy callback handlers.
* @{ */
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
bool fEnabledBySystem)
{
return VINF_SUCCESS;
}
static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
/** @} */
/**
* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
* Down at the Rate Specified" erratum.
*
* Errata names and related steppings:
* - BA86 - D0.
* - AAX65 - C2.
* - AAU65 - C2, K0.
* - AAO95 - B1.
* - AAT59 - C2.
* - AAK139 - D0.
* - AAM126 - C0, C1, D0.
* - AAN92 - B1.
* - AAJ124 - C0, D0.
*
* - AAP86 - B1.
*
* Steppings: B1, C0, C1, C2, D0, K0.
*
* @returns true if subject to it, false if not.
*/
static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
{
u &= ~(RT_BIT_32(14) | RT_BIT_32(15) | RT_BIT_32(28) | RT_BIT_32(29) | RT_BIT_32(30) | RT_BIT_32(31));
|| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
|| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
|| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
|| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
|| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
|| u == UINT32_C(0x000106A0) /*?321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
|| u == UINT32_C(0x000106A1) /*?321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
|| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
|| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
|| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
|| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
)
return true;
return false;
}
/**
* Intel specific initialization code.
*
* @returns VBox status code (will only fail if out of memory).
*/
{
/*
* Check that all the required VT-x features are present.
*/
if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
)
{
/** @todo move this into a separate function. */
/*
* First try use native kernel API for controlling VT-x.
* (This is only supported by some Mac OS X kernels atm.)
*/
{
AssertLogRelMsg(rc == VINF_SUCCESS || rc == VERR_VMX_IN_VMX_ROOT_MODE || rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
if (RT_SUCCESS(rc))
{
}
}
else
{
/* We need to check if VT-x has been properly initialized on all
CPUs. Some BIOSes do a lousy job. */
}
{
/* Reread in case we've changed it. */
if ( (g_HvmR0.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON | MSR_IA32_FEATURE_CONTROL_LOCK))
{
/*
* Read all relevant MSR.
*/
/* VPID 16 bits ASID. */
{
{
}
}
{
/*
* Enter root mode
*/
if (RT_FAILURE(rc))
{
return rc;
}
/* Set revision dword at the beginning of the structure. */
/* Make sure we don't get rescheduled to another cpu during this probe. */
/*
* Check CR4.VMXE
*/
{
/* In theory this bit could be cleared behind our back. Which would cause
#UD faults when we try to execute the VMX instructions... */
}
/* Enter VMX Root Mode */
if (RT_SUCCESS(rc))
{
VMXDisable();
}
else
{
/*
* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
* it will crash the host when we enter raw mode, because:
*
* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
* this bit), and
* (b) turning off paging causes a #GP (unavoidable when switching
* from long to 32 bits mode or 32 bits to PAE).
*
* They should fix their code, but until they do we simply refuse to run.
*/
}
/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
if it wasn't so before (some software could incorrectly
think it's in VMX mode). */
RTR0MemObjFree(hScatchMemObj, false);
}
}
else
{
AssertFailed(); /* can't hit this case anymore */
}
{
/* Call the global VT-x initialization routine. */
rc = VMXR0GlobalInit();
if (RT_FAILURE(rc))
/*
* Install the VT-x methods.
*/
/*
* Check for the VMX-Preemption Timer and adjust for the * "VMX-Preemption
* Timer Does Not Count Down at the Rate Specified" erratum.
*/
{
}
}
}
#ifdef LOG_ENABLED
else
#endif
}
else
return VINF_SUCCESS;
}
/**
* AMD-specific initialization code.
*/
{
/*
*/
&& uMaxExtLeaf >= 0x8000000a
)
{
/* Query AMD features. */
/*
* We need to check if AMD-V has been properly initialized on all CPUs.
* Some BIOSes might do a poor job.
*/
if (RT_SUCCESS(rc))
#ifndef DEBUG_bird
#endif
if (RT_SUCCESS(rc))
{
/* Read the HWCR MSR for diagnostics. */
}
else
}
else
}
/**
* Does global Ring-0 HM initialization (at module init).
*
* @returns VBox status code.
*/
VMMR0_INT_DECL(int) HMR0Init(void)
{
/*
* Initialize the globals.
*/
/* Fill in all callbacks with placeholders. */
g_HvmR0.fGlobalInit = true;
/*
* Make sure aCpuInfo is big enough for all the CPUs on this system.
*/
{
LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
return VERR_TOO_MANY_CPUS;
}
/*
* Check for VT-x and AMD-V capabilities.
*/
int rc;
if (ASMHasCpuId())
{
/* Standard features. */
if (ASMIsValidStdRange(uMaxLeaf))
{
/* Query AMD features. */
else
/* Go to CPU specific initialization code. */
{
if (RT_FAILURE(rc))
return rc;
}
else
}
else
}
else
/*
* when brought offline/online or suspending/resuming.
*/
{
}
/* We return success here because module init shall not fail if HM
fails to initialize. */
return VINF_SUCCESS;
}
/**
* Does global Ring-0 HM termination (at module termination).
*
* @returns VBox status code.
*/
VMMR0_INT_DECL(int) HMR0Term(void)
{
int rc;
{
/*
* Simple if the host OS manages VT-x.
*/
{
}
}
else
{
{
/* Doesn't really matter if this fails. */
}
else
rc = VINF_SUCCESS;
/*
*/
if (g_HvmR0.fGlobalInit)
{
if (RT_SUCCESS(rc))
{
}
}
/*
* Free the per-cpu pages used for VT-x and AMD-V.
*/
{
{
}
}
}
/** @todo This needs cleaning up. There's no matching hmR0TermIntel() and all
* modules. */
return rc;
}
/**
* Worker function used by hmR0PowerCallback and HMR0Init to initalize
* VT-x on a CPU.
*
* @param idCpu The identifier for the CPU the function is called on.
* @param pvUser1 Pointer to the first RC structure.
* @param pvUser2 Ignored.
*/
{
Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
/*
* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
* Once the lock bit is set, this MSR can no longer be modified.
*/
== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
)
{
/* MSR is not yet locked; we can change it ourselves here. */
}
int rc;
rc = VINF_SUCCESS;
else
}
/**
* Worker function used by hmR0PowerCallback and HMR0Init to initalize
* VT-x / AMD-V on a CPU.
*
* @param idCpu The identifier for the CPU the function is called on.
* @param pvUser1 Pointer to the first RC structure.
* @param pvUser2 Ignored.
*/
{
Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
/* Check if SVM is disabled. */
int rc;
if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
{
/* Turn on SVM in the EFER MSR. */
if (fEfer & MSR_K6_EFER_SVME)
else
{
/* Paranoia. */
if (fEfer & MSR_K6_EFER_SVME)
{
/* Restore previous value. */
rc = VINF_SUCCESS;
}
else
}
}
else
}
/**
* Enable VT-x or AMD-V on the current CPU
*
* @returns VBox status code.
* @param pVM Pointer to the VM (can be 0).
* @param idCpu The identifier for the CPU the function is called on.
*/
{
Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
int rc;
else
{
AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
}
if (RT_SUCCESS(rc))
pCpu->fConfigured = true;
return rc;
}
/**
* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
* is to be called on the target cpus.
*
* @param idCpu The identifier for the CPU the function is called on.
* @param pvUser1 The 1st user argument.
* @param pvUser2 The 2nd user argument.
*/
{
}
/**
* RTOnce callback employed by HMR0EnableAllCpus.
*
* @returns VBox status code.
* @param pvUser Pointer to the VM.
* @param pvUserIgnore NULL, ignored.
*/
{
/*
* Indicate that we've initialized.
*
* Note! There is a potential race between this function and the suspend
* notification. Kind of unlikely though, so ignored for now.
*/
/*
* The global init variable is set by the first VM.
*/
{
}
int rc;
{
/*
* Global VT-x initialization API (only darwin for now).
*/
if (RT_SUCCESS(rc))
/* If the host provides a VT-x init API, then we'll rely on that for global init. */
else
}
else
{
/*
* We're doing the job ourselves.
*/
/* Allocate one page per cpu for the global vt-x and amd-v pages */
{
if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
{
rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
}
}
rc = VINF_SUCCESS;
}
{
if (RT_SUCCESS(rc))
AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
}
return rc;
}
/**
* Sets up HM on all cpus.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
/* Make sure we don't touch hm after we've disabled hm in
preparation of a suspend. */
return VERR_HM_SUSPEND_PENDING;
}
/**
* Disable VT-x or AMD-V on the current CPU.
*
* @returns VBox status code.
* @param idCpu The identifier for the CPU the function is called on.
*/
{
Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
int rc;
if (pCpu->fConfigured)
{
{
}
else
{
pCpu->fIgnoreAMDVInUseError = true;
rc = VINF_SUCCESS;
}
pCpu->fConfigured = false;
}
else
pCpu->uCurrentAsid = 0;
return rc;
}
/**
* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
* is to be called on the target cpus.
*
* @param idCpu The identifier for the CPU the function is called on.
* @param pvUser1 The 1st user argument.
* @param pvUser2 The 2nd user argument.
*/
{
}
/**
* Callback function invoked when a cpu goes online or offline.
*
* @param enmEvent The Mp event.
* @param idCpu The identifier for the CPU the function is called on.
* @param pvData Opaque data (PVM pointer).
*/
{
/*
* We only care about uninitializing a CPU that is going offline. When a
* CPU comes online, the initialization is done lazily in HMR0Enter().
*/
switch (enmEvent)
{
case RTMPEVENT_OFFLINE:
{
break;
}
default:
break;
}
}
/**
* Called whenever a system power state change occurs.
*
* @param enmEvent The Power event.
* @param pvUser User argument.
*/
{
#ifdef LOG_ENABLED
if (enmEvent == RTPOWEREVENT_SUSPEND)
SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
else
SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
#endif
if (enmEvent == RTPOWEREVENT_SUSPEND)
{
int rc;
if (enmEvent == RTPOWEREVENT_SUSPEND)
{
if (g_HvmR0.fGlobalInit)
{
/* Turn off VT-x or AMD-V on all CPUs. */
}
/* else nothing to do here for the local init case */
}
else
{
/* Reinit the CPUs from scratch as the suspend state might have
messed with the MSRs. (lousy BIOSes as usual) */
else
if (RT_SUCCESS(rc))
#ifdef LOG_ENABLED
if (RT_FAILURE(rc))
#endif
if (g_HvmR0.fGlobalInit)
{
/* Turn VT-x or AMD-V back on on all CPUs. */
}
/* else nothing to do here for the local init case */
}
}
if (enmEvent == RTPOWEREVENT_RESUME)
}
/**
* Does Ring-0 per VM HM initialization.
*
* This will copy HM global into the VM structure and call the CPU specific
* init routine which will allocate resources for each virtual CPU and such.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
#ifdef LOG_ENABLED
#endif
/* Make sure we don't touch hm after we've disabled hm in preparation of a suspend. */
return VERR_HM_SUSPEND_PENDING;
/*
* Copy globals to the VM structure.
*/
{
#endif
}
/*
* Initialize some per CPU fields.
*/
{
/* Invalidate the last cpu we were running on. */
/* We'll aways increment this the first time (host uses ASID 0) */
}
/*
* Call the hardware specific initialization method.
*
* Note! The fInUse handling here isn't correct as we can we can be
* rescheduled to a different cpu, but the fInUse case is mostly for
* debugging... Disabling preemption isn't an option when allocating
* memory, so we'll let it slip for now.
*/
return rc;
}
/**
* Does Ring-0 per VM HM termination.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
/* Make sure we don't touch hm after we've disabled hm in preparation
of a suspend. */
/** @todo r=bird: This cannot be right, the termination functions are
* ==> memory leak. */
/*
* Call the hardware specific method.
*
* Note! Not correct as we can be rescheduled to a different cpu, but the
* fInUse case is mostly for debugging.
*/
return rc;
}
/**
* Sets up a VT-x or AMD-V session.
*
* This is mostly about setting up the hardware VM state.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
/* Make sure we don't touch hm after we've disabled hm in
preparation of a suspend. */
/*
* Call the hardware specific setup VM method. This requires the CPU to be
*/
/* On first entry we'll sync everything. */
/* Enable VT-x or AMD-V if local init is required. */
int rc;
if (!g_HvmR0.fGlobalInit)
{
}
/* Setup VT-x or AMD-V. */
/* Disable VT-x or AMD-V if local init was done before. */
if (!g_HvmR0.fGlobalInit)
{
}
return rc;
}
/**
* Enters the VT-x or AMD-V session.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
*
* @remarks This is called with preemption disabled.
*/
{
/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
#ifdef VBOX_WITH_OLD_VTX_CODE
/* Always load the guest's debug state on-demand. */
#else
#endif
/* Always reload the host context and the guest's CR0 register (for the FPU bits). */
/* Setup the register and mask according to the current execution mode. */
else
/* Enable VT-x or AMD-V if local init is required, or enable if it's a
freshly onlined CPU. */
int rc;
if ( !pCpu->fConfigured
|| !g_HvmR0.fGlobalInit)
{
}
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
#endif
/* We must save the host context here (VT-x) as we might be rescheduled on
a different cpu after a long jump back to ring 3. */
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
if (fStartedSet)
#endif
/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
and ring-3 calls. */
if (RT_FAILURE(rc))
return rc;
}
/**
* Leaves the VT-x or AMD-V session.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
*
* @remarks Called with preemption disabled just like HMR0Enter, our
* counterpart.
*/
{
int rc;
/** @todo r=bird: This can't be entirely right? */
/* The new code does FPU restoration in the VMX R0 code. */
#ifdef VBOX_WITH_OLD_VTX_CODE
/*
* Save the guest FPU and XMM state if necessary.
*
* Note! It's rather tricky with longjmps done by e.g. Log statements or
* the page fault handler. We must restore the host FPU here to make
* absolutely sure we don't leave the guest FPU state active or trash
* somebody else's FPU state.
*/
{
Log2(("CPUMR0SaveGuestFPU\n"));
pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0; /** @todo r=bird: Why HM_CHANGED_GUEST_CR0?? */
}
#endif
/* We don't pass on invlpg information to the recompiler for nested paging
guests, so we must make sure the recompiler flushes its TLB the next
time it executes code. */
#ifdef VBOX_WITH_OLD_VTX_CODE
#else
#endif
)
{
}
/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
and ring-3 calls. */
|| RT_FAILURE_NP(rc),
/*
* Disable VT-x or AMD-V if local init was done before.
*/
if (!g_HvmR0.fGlobalInit)
{
/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
}
return rc;
}
/**
* Runs guest code in a hardware accelerated VM.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
*
* @remarks Called with preemption disabled and after first having called
* HMR0Enter.
*/
{
#ifdef VBOX_STRICT
#endif
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
#endif
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
#endif
return rc;
}
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
/**
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest CPU context.
*/
{
}
/**
* Save guest debug state (64 bits guest mode & 32 bits host only)
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest CPU context.
*/
{
}
/**
* Test the 32->64 bits switcher.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
*/
{
int rc;
else
return rc;
}
#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
/**
* Returns suspend status of the host.
*
* @returns Suspend pending or not.
*/
VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
{
}
/**
* Returns the cpu structure for the current cpu.
* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
*
* @returns The cpu structure pointer.
*/
{
}
/**
* Returns the cpu structure for the current cpu.
* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
*
* @returns The cpu structure pointer.
* @param idCpu id of the VCPU.
*/
{
}
/**
* Save a pending IO read.
*
* @param pVCpu Pointer to the VMCPU.
* @param GCPtrRip Address of IO instruction.
* @param GCPtrRipNext Address of the next instruction.
* @param uPort Port address.
* @param uAndVal AND mask for saving the result in eax.
* @param cbSize Read size.
*/
VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
{
return;
}
/**
* Save a pending IO write.
*
* @param pVCpu Pointer to the VMCPU.
* @param GCPtrRIP Address of IO instruction.
* @param uPort Port address.
* @param uAndVal AND mask for fetching the result from eax.
* @param cbSize Read size.
*/
VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
{
return;
}
/**
* Raw-mode switcher hook - disable VT-x if it's active *and* the current
* switcher turns off paging.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param enmSwitcher The switcher we're about to use.
* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
*/
{
*pfVTxDisabled = false;
/* No such issues with AMD-V */
return VINF_SUCCESS;
/* Check if the swithcing we're up to is safe. */
switch (enmSwitcher)
{
case VMMSWITCHER_32_TO_32:
case VMMSWITCHER_PAE_TO_PAE:
return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
case VMMSWITCHER_32_TO_PAE:
case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
case VMMSWITCHER_AMD64_TO_32:
case VMMSWITCHER_AMD64_TO_PAE:
break; /* unsafe switchers */
default:
}
/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
regardless of whether we're currently using VT-x or not. */
{
return VINF_SUCCESS;
}
/** @todo Check if this code is presumtive wrt other VT-x users on the
* system... */
/* Nothing to do if we haven't enabled VT-x. */
return VINF_SUCCESS;
/* Local init implies the CPU is currently not in VMX root mode. */
if (!g_HvmR0.fGlobalInit)
return VINF_SUCCESS;
/* Ok, disable VT-x. */
*pfVTxDisabled = true;
}
/**
* Raw-mode switcher hook - re-enable VT-x if was active *and* the current
* switcher turned off paging.
*
* @param pVM Pointer to the VM.
* @param fVTxDisabled Whether VT-x was disabled or not.
*/
{
if (!fVTxDisabled)
return; /* nothing to do */
else
{
}
}
#ifdef VBOX_STRICT
/**
* Dumps a descriptor.
*
* @param pDesc Descriptor to dump.
* @param Sel Selector number.
* @param pszMsg Message to prepend the log entry with.
*/
{
/*
* Make variable description string.
*/
static struct
{
unsigned cch;
const char *psz;
} const s_aTypes[32] =
{
/* system */
# if HC_ARCH_BITS == 64
# else
# endif
/* non system */
};
char szMsg[128];
else
# if HC_ARCH_BITS == 64
else
# else
else
# endif
*psz = '\0';
/*
* Limit and Base and format the output.
*/
# if HC_ARCH_BITS == 64
# else
# endif
}
/**
* Formats a full register dump.
*
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the CPU context.
*/
{
/*
* Format the flags.
*/
static struct
{
} const s_aFlags[] =
{
};
char szEFlags[80];
for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
{
if (pszAdd)
{
*psz++ = ' ';
}
}
/*
* Format the registers.
*/
if (CPUMIsGuestIn64BitCode(pVCpu))
{
Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
"r14=%016RX64 r15=%016RX64\n"
"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
,
}
else
Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
,
Log(("FPU:\n"
"FCW=%04x FSW=%04x FTW=%02x\n"
"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
,
Log(("MSR:\n"
"EFER =%016RX64\n"
"PAT =%016RX64\n"
"STAR =%016RX64\n"
"CSTAR =%016RX64\n"
"LSTAR =%016RX64\n"
"SFMASK =%016RX64\n"
"KERNELGSBASE =%016RX64\n",
pCtx->msrKERNELGSBASE));
}
#endif /* VBOX_STRICT */