CPUMR0A.asm revision c3ad07071523338d76960d8da7678860aea8b03d
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync; CPUM - Guest Context Assembly Routines.
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync; Copyright (C) 2006-2013 Oracle Corporation
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync; This file is part of VirtualBox Open Source Edition (OSE), as
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync; available from http://www.virtualbox.org. This file is free software;
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync; you can redistribute it and/or modify it under the terms of the GNU
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync; General Public License (GPL) as published by the Free Software
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync; Foundation, in version 2 as it comes in the "COPYING" file of the
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync;*******************************************************************************
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync;* Header Files *
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync;*******************************************************************************
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync%ifdef IN_RING3
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync %error "The jump table doesn't link on leopard."
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync;*******************************************************************************
67b414aa650cb27688d387c2184f8488d801cd72vboxsync;* Defined Constants And Macros *
67b414aa650cb27688d387c2184f8488d801cd72vboxsync;*******************************************************************************
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync;; The offset of the XMM registers in X86FXSTATE.
67b414aa650cb27688d387c2184f8488d801cd72vboxsync; Use define because I'm too lazy to convert the struct.
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync%define XMM_OFF_IN_X86FXSTATE 160
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync;*******************************************************************************
84d5d5272edbc1f41f963221b74a7eda71d0e2a2vboxsync;* External Symbols *
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync;*******************************************************************************
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsyncextern NAME(SUPR0AbsIs64bit)
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsyncextern NAME(SUPR0Abs64bitKernelCS)
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsyncextern NAME(SUPR0Abs64bitKernelSS)
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsyncextern NAME(SUPR0Abs64bitKernelDS)
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsyncextern NAME(SUPR0AbsKernelCS)
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync;*******************************************************************************
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync;* Global Variables *
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync;*******************************************************************************
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync; Store the SUPR0AbsIs64bit absolute value here so we can cmp/test without
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync; needing to clobber a register. (This trick doesn't quite work for PE btw.
84d5d5272edbc1f41f963221b74a7eda71d0e2a2vboxsync; but that's not relevant atm.)
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsyncGLOBALNAME g_fCPUMIs64bitHost
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync dd NAME(SUPR0AbsIs64bit)
84d5d5272edbc1f41f963221b74a7eda71d0e2a2vboxsync;; Macro for FXSAVE/FXRSTOR leaky behaviour on AMD CPUs, see cpumR3CheckLeakyFpu().
84d5d5272edbc1f41f963221b74a7eda71d0e2a2vboxsync; Cleans the FPU state, if necessary, before restoring the FPU.
84d5d5272edbc1f41f963221b74a7eda71d0e2a2vboxsync; This macro ASSUMES CR0.TS is not set!
0edd5583e49bb46471ed27200f0fe2fdf00f5ecavboxsync; @remarks Trashes xAX!!
84d5d5272edbc1f41f963221b74a7eda71d0e2a2vboxsync; Changes here should also be reflected in CPUMAllA.asm's copy!
e06cbb510db6f327856cabc016398e4fda505809vboxsync%macro CLEANFPU 0
e06cbb510db6f327856cabc016398e4fda505809vboxsync test dword [xDX + CPUMCPU.fUseFlags], CPUM_USE_FFXSR_LEAKY
e06cbb510db6f327856cabc016398e4fda505809vboxsync jz .nothing_to_clean
10f224d85cd1135f0ca4ee1c1c1a7e15988bed58vboxsync xor eax, eax
43b9d660479e358a9b61827b8037ea65268345e9vboxsync fnstsw ax ; Get FSW
ad1c538f298dad2073517c8773fca41b5243201cvboxsync test eax, RT_BIT(7) ; If FSW.ES (bit 7) is set, clear it to not cause FPU exceptions
10f224d85cd1135f0ca4ee1c1c1a7e15988bed58vboxsync ; while clearing & loading the FPU bits in 'clean_fpu'
10f224d85cd1135f0ca4ee1c1c1a7e15988bed58vboxsync jz .clean_fpu
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync ffree st7 ; Clear FPU stack register(7)'s tag entry to prevent overflow if a wraparound occurs
84d5d5272edbc1f41f963221b74a7eda71d0e2a2vboxsync ; for the upcoming push (load)
48eca14ff165b52c459d7c3090f1f5dba0d1fedbvboxsync fild dword [xDX + CPUMCPU.Guest.fpu] ; Explicit FPU load to overwrite FIP, FOP, FDP registers in the FPU.
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync.nothing_to_clean:
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync;; Macro to save and modify CR0 (if necessary) before touching the FPU state
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync; so as to not cause any FPU exceptions.
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync; @remarks Uses xCX for backing-up CR0 (if CR0 needs to be modified) otherwise clears xCX.
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync; @remarks Trashes xAX.
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync%macro SAVE_CR0_CLEAR_FPU_TRAPS 0
67b414aa650cb27688d387c2184f8488d801cd72vboxsync xor ecx, ecx
67b414aa650cb27688d387c2184f8488d801cd72vboxsync mov xAX, cr0
67b414aa650cb27688d387c2184f8488d801cd72vboxsync test eax, X86_CR0_TS | X86_CR0_EM ; Make sure its safe to access the FPU state.
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync jz %%skip_cr0_write
67b414aa650cb27688d387c2184f8488d801cd72vboxsync mov xCX, xAX ; Save old CR0
67b414aa650cb27688d387c2184f8488d801cd72vboxsync and xAX, ~(X86_CR0_TS | X86_CR0_EM)
67b414aa650cb27688d387c2184f8488d801cd72vboxsync mov cr0, xAX
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync%%skip_cr0_write:
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync;; Macro to restore CR0 from xCX if necessary.
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync; @remarks xCX should contain the CR0 value to restore or 0 if no restoration is needed.
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync%macro RESTORE_CR0 0
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync je %%skip_cr0_restore
22cf3a5eb5a3cc2ea58e4fe974914e6a32514614vboxsync mov cr0, xCX
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync%%skip_cr0_restore:
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync; Saves the host FPU/XMM state and restores the guest state.
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync; @returns 0
10f224d85cd1135f0ca4ee1c1c1a7e15988bed58vboxsync; @param pCPUMCPU x86:[esp+4] GCC:rdi MSC:rcx CPUMCPU pointer
607049337dcf359292c82c9372a2c19d9c4cdd2fvboxsyncBEGINPROC cpumR0SaveHostRestoreGuestFPUState
607049337dcf359292c82c9372a2c19d9c4cdd2fvboxsync%ifdef RT_ARCH_AMD64
607049337dcf359292c82c9372a2c19d9c4cdd2fvboxsync %ifdef RT_OS_WINDOWS
607049337dcf359292c82c9372a2c19d9c4cdd2fvboxsync mov xDX, rcx
10f224d85cd1135f0ca4ee1c1c1a7e15988bed58vboxsync mov xDX, rdi
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync mov xDX, dword [esp + 4]
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync pushf ; The darwin kernel can get upset or upset things if an
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync cli ; interrupt occurs while we're doing fxsave/fxrstor/cr0.
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync ; Switch the state.
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync or dword [xDX + CPUMCPU.fUseFlags], (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM)
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync ; Clear CR0 FPU bits to not cause exceptions, uses xCX
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync SAVE_CR0_CLEAR_FPU_TRAPS
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync ; Do NOT use xCX from this point!
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync cmp byte [NAME(g_fCPUMIs64bitHost)], 0
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync jz .legacy_mode
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync db 0xea ; jmp far .sixtyfourbit_mode
9e201d78ac6efdd08550263f2e146cdb76e9d49bvboxsync dd .sixtyfourbit_mode, NAME(SUPR0Abs64bitKernelCS)
o64 fxsave [xDX + CPUMCPU.Host.fpu] ; ASSUMES that all VT-x/AMD-V boxes sports fxsave/fxrstor (safe assumption)
o64 fxrstor [xDX + CPUMCPU.Guest.fpu]
fxsave [xDX + CPUMCPU.Host.fpu] ; ASSUMES that all VT-x/AMD-V boxes sports fxsave/fxrstor (safe assumption)
fxrstor [xDX + CPUMCPU.Guest.fpu]
lea r11, [xDX + CPUMCPU.Host.fpu + XMM_OFF_IN_X86FXSTATE]
o64 fxsave [rdx + CPUMCPU.Host.fpu]
o64 fxrstor [rdx + CPUMCPU.Guest.fpu]
; Saves the host FPU/XMM state
cli ; interrupt occurs while we're doing fxsave/fxrstor/cr0.
or dword [xDX + CPUMCPU.fUseFlags], (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM)
fxsave [xDX + CPUMCPU.Host.fpu] ; ASSUMES that all VT-x/AMD-V boxes support fxsave/fxrstor (safe assumption)
; Saves the guest FPU/XMM state and restores the host state.
test dword [xDX + CPUMCPU.fUseFlags], CPUM_USED_FPU
cli ; interrupt occurs while we're doing fxsave/fxrstor/cr0.
o64 fxsave [xDX + CPUMCPU.Guest.fpu] ; ASSUMES that all VT-x/AMD-V boxes support fxsave/fxrstor (safe assumption)
o64 fxrstor [xDX + CPUMCPU.Host.fpu]
fxsave [xDX + CPUMCPU.Guest.fpu] ; ASSUMES that all VT-x/AMD-V boxes support fxsave/fxrstor (safe assumption)
fxrstor [xDX + CPUMCPU.Host.fpu]
and dword [xDX + CPUMCPU.fUseFlags], ~CPUM_USED_FPU
o64 fxsave [rdx + CPUMCPU.Guest.fpu]
o64 fxrstor [rdx + CPUMCPU.Host.fpu]
; Sets the host's FPU/XMM state
test dword [xDX + CPUMCPU.fUseFlags], CPUM_USED_FPU
cli ; interrupt occurs while we're doing fxsave/fxrstor/cr0.
o64 fxrstor [xDX + CPUMCPU.Host.fpu]
fxrstor [xDX + CPUMCPU.Host.fpu]
and dword [xDX + CPUMCPU.fUseFlags], ~CPUM_USED_FPU
o64 fxrstor [rdx + CPUMCPU.Host.fpu]