CPUMR0A.asm revision 2a5babc3ace611a3a900b61ff0659923994840bf
f5d30e2864e048a42c4dc1134993ae7efdb5d6c3Mark Andrews; CPUM - Guest Context Assembly Routines.
f5d30e2864e048a42c4dc1134993ae7efdb5d6c3Mark Andrews; Copyright (C) 2006-2013 Oracle Corporation
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; This file is part of VirtualBox Open Source Edition (OSE), as
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; available from http://www.virtualbox.org. This file is free software;
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; you can redistribute it and/or modify it under the terms of the GNU
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; General Public License (GPL) as published by the Free Software
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; Foundation, in version 2 as it comes in the "COPYING" file of the
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein;*******************************************************************************
14a656f94b1fd0ababd84a772228dfa52276ba15Evan Hunt;* Header Files *
14a656f94b1fd0ababd84a772228dfa52276ba15Evan Hunt;*******************************************************************************
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein%ifdef IN_RING3
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein %error "The jump table doesn't link on leopard."
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein;*******************************************************************************
14a656f94b1fd0ababd84a772228dfa52276ba15Evan Hunt;* Defined Constants And Macros *
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein;*******************************************************************************
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein;; The offset of the XMM registers in X86FXSTATE.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; Use define because I'm too lazy to convert the struct.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein%define XMM_OFF_IN_X86FXSTATE 160
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein;*******************************************************************************
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein;* External Symbols *
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein;*******************************************************************************
e0f518c964d69b07a52949c80c12d8fe4adb7398Rob Austein%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austeinextern NAME(SUPR0AbsIs64bit)
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austeinextern NAME(SUPR0Abs64bitKernelCS)
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austeinextern NAME(SUPR0Abs64bitKernelSS)
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austeinextern NAME(SUPR0Abs64bitKernelDS)
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austeinextern NAME(SUPR0AbsKernelCS)
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein;*******************************************************************************
f9672c2f8645f25055467b926e3442374be7376fRob Austein;* Global Variables *
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein;*******************************************************************************
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; Store the SUPR0AbsIs64bit absolute value here so we can cmp/test without
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; needing to clobber a register. (This trick doesn't quite work for PE btw.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; but that's not relevant atm.)
268a4475065fe6a8cd7cc707820982cf5e98f430Rob AusteinGLOBALNAME g_fCPUMIs64bitHost
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein dd NAME(SUPR0AbsIs64bit)
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein;; Macro for FXSAVE/FXRSTOR leaky behaviour on AMD CPUs, see cpumR3CheckLeakyFpu().
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; Cleans the FPU state, if necessary, before restoring the FPU.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; This macro ASSUMES CR0.TS is not set!
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; @remarks Trashes xAX!!
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; Changes here should also be reflected in CPUMRCA.asm's copy!
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein%macro CLEANFPU 0
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein test dword [xDX + CPUMCPU.fUseFlags], CPUM_USE_FFXSR_LEAKY
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein jz .nothing_to_clean
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein xor eax, eax
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein fnstsw ax ; Get FSW
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein test eax, RT_BIT(7) ; If FSW.ES (bit 7) is set, clear it to not cause FPU exceptions
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein ; while clearing & loading the FPU bits in 'clean_fpu'
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein jz .clean_fpu
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein ffree st7 ; Clear FPU stack register(7)'s tag entry to prevent overflow if a wraparound occurs
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein ; for the upcoming push (load)
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein fild dword [xDX + CPUMCPU.Guest.fpu] ; Explicit FPU load to overwrite FIP, FOP, FDP registers in the FPU.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein.nothing_to_clean:
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein;; Macro to save and modify CR0 (if necessary) before touching the FPU state
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; so as to not cause any FPU exceptions.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; @remarks Uses xCX for backing-up CR0 (if CR0 needs to be modified) otherwise clears xCX.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; @remarks Trashes xAX.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein%macro SAVE_CR0_CLEAR_FPU_TRAPS 0
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein xor ecx, ecx
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein mov xAX, cr0
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein test eax, X86_CR0_TS | X86_CR0_EM ; Make sure its safe to access the FPU state.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein jz %%skip_cr0_write
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein mov xCX, xAX ; Save old CR0
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein and xAX, ~(X86_CR0_TS | X86_CR0_EM)
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein mov cr0, xAX
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein%%skip_cr0_write:
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein;; Macro to restore CR0 from xCX if necessary.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; @remarks xCX should contain the CR0 value to restore or 0 if no restoration is needed.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein%macro RESTORE_CR0 0
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein je %%skip_cr0_restore
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein mov cr0, xCX
81059f7c19ef4d1835e3ce87bdb7ea1a46569eaeRob Austein%%skip_cr0_restore:
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; Saves the host FPU/XMM state and restores the guest state.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein; @param pCPUMCPU x86:[esp+4] GCC:rdi MSC:rcx CPUMCPU pointer
268a4475065fe6a8cd7cc707820982cf5e98f430Rob AusteinBEGINPROC cpumR0SaveHostRestoreGuestFPUState
49732e4d6008d7d99dfce596a17e17aa13425502Mark Andrews%ifdef RT_ARCH_AMD64
49732e4d6008d7d99dfce596a17e17aa13425502Mark Andrews %ifdef RT_OS_WINDOWS
49732e4d6008d7d99dfce596a17e17aa13425502Mark Andrews mov xDX, rcx
49732e4d6008d7d99dfce596a17e17aa13425502Mark Andrews mov xDX, rdi
49732e4d6008d7d99dfce596a17e17aa13425502Mark Andrews mov xDX, dword [esp + 4]
49732e4d6008d7d99dfce596a17e17aa13425502Mark Andrews pushf ; The darwin kernel can get upset or upset things if an
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein cli ; interrupt occurs while we're doing fxsave/fxrstor/cr0.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein ; Switch the state.
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein or dword [xDX + CPUMCPU.fUseFlags], (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM)
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein ; Clear CR0 FPU bits to not cause exceptions, uses xCX
268a4475065fe6a8cd7cc707820982cf5e98f430Rob Austein SAVE_CR0_CLEAR_FPU_TRAPS
o64 fxsave [xDX + CPUMCPU.Host.fpu] ; ASSUMES that all VT-x/AMD-V boxes sports fxsave/fxrstor (safe assumption)
o64 fxrstor [xDX + CPUMCPU.Guest.fpu]
fxsave [xDX + CPUMCPU.Host.fpu] ; ASSUMES that all VT-x/AMD-V boxes sports fxsave/fxrstor (safe assumption)
fxrstor [xDX + CPUMCPU.Guest.fpu]
lea r11, [xDX + CPUMCPU.Host.fpu + XMM_OFF_IN_X86FXSTATE]
o64 fxsave [rdx + CPUMCPU.Host.fpu]
o64 fxrstor [rdx + CPUMCPU.Guest.fpu]
; Saves the host FPU/XMM state
cli ; interrupt occurs while we're doing fxsave/fxrstor/cr0.
or dword [xDX + CPUMCPU.fUseFlags], (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM)
fxsave [xDX + CPUMCPU.Host.fpu] ; ASSUMES that all VT-x/AMD-V boxes support fxsave/fxrstor (safe assumption)
; Saves the guest FPU/XMM state and restores the host state.
test dword [xDX + CPUMCPU.fUseFlags], CPUM_USED_FPU
cli ; interrupt occurs while we're doing fxsave/fxrstor/cr0.
o64 fxsave [xDX + CPUMCPU.Guest.fpu] ; ASSUMES that all VT-x/AMD-V boxes support fxsave/fxrstor (safe assumption)
o64 fxrstor [xDX + CPUMCPU.Host.fpu]
fxsave [xDX + CPUMCPU.Guest.fpu] ; ASSUMES that all VT-x/AMD-V boxes support fxsave/fxrstor (safe assumption)
fxrstor [xDX + CPUMCPU.Host.fpu]
and dword [xDX + CPUMCPU.fUseFlags], ~CPUM_USED_FPU
o64 fxsave [rdx + CPUMCPU.Guest.fpu]
o64 fxrstor [rdx + CPUMCPU.Host.fpu]
; Sets the host's FPU/XMM state
test dword [xDX + CPUMCPU.fUseFlags], CPUM_USED_FPU
cli ; interrupt occurs while we're doing fxsave/fxrstor/cr0.
o64 fxrstor [xDX + CPUMCPU.Host.fpu]
fxrstor [xDX + CPUMCPU.Host.fpu]
and dword [xDX + CPUMCPU.fUseFlags], ~CPUM_USED_FPU
o64 fxrstor [rdx + CPUMCPU.Host.fpu]