447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; CPUM - Ring-0 Assembly Routines (supporting HM and IEM).
aae8a6a38fd27661046ab1d06cb2cb5c096c40edvboxsync; Copyright (C) 2006-2015 Oracle Corporation
52676b598e9afd834db7f3e62a983044038e92bevboxsync; This file is part of VirtualBox Open Source Edition (OSE), as
52676b598e9afd834db7f3e62a983044038e92bevboxsync; available from http://www.virtualbox.org. This file is free software;
52676b598e9afd834db7f3e62a983044038e92bevboxsync; you can redistribute it and/or modify it under the terms of the GNU
52676b598e9afd834db7f3e62a983044038e92bevboxsync; General Public License (GPL) as published by the Free Software
52676b598e9afd834db7f3e62a983044038e92bevboxsync; Foundation, in version 2 as it comes in the "COPYING" file of the
52676b598e9afd834db7f3e62a983044038e92bevboxsync; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
52676b598e9afd834db7f3e62a983044038e92bevboxsync; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
52676b598e9afd834db7f3e62a983044038e92bevboxsync;*******************************************************************************
52676b598e9afd834db7f3e62a983044038e92bevboxsync;* Header Files *
52676b598e9afd834db7f3e62a983044038e92bevboxsync;*******************************************************************************
52676b598e9afd834db7f3e62a983044038e92bevboxsync%ifdef IN_RING3
52676b598e9afd834db7f3e62a983044038e92bevboxsync %error "The jump table doesn't link on leopard."
bb33bc2ad72088bbb39737f7145a6cfbe1f65780vboxsync;*******************************************************************************
bb33bc2ad72088bbb39737f7145a6cfbe1f65780vboxsync;* Defined Constants And Macros *
bb33bc2ad72088bbb39737f7145a6cfbe1f65780vboxsync;*******************************************************************************
bb33bc2ad72088bbb39737f7145a6cfbe1f65780vboxsync;; The offset of the XMM registers in X86FXSTATE.
bb33bc2ad72088bbb39737f7145a6cfbe1f65780vboxsync; Use define because I'm too lazy to convert the struct.
bb33bc2ad72088bbb39737f7145a6cfbe1f65780vboxsync%define XMM_OFF_IN_X86FXSTATE 160
d239ea80a55b621f0f0e0710e8a1b4762ddd6d0avboxsync%define IP_OFF_IN_X86FXSTATE 08h
d239ea80a55b621f0f0e0710e8a1b4762ddd6d0avboxsync%define CS_OFF_IN_X86FXSTATE 0ch
d239ea80a55b621f0f0e0710e8a1b4762ddd6d0avboxsync%define DS_OFF_IN_X86FXSTATE 14h
ff308c5c63cf562048295f83638429a925415a10vboxsync;; For numeric expressions
ff308c5c63cf562048295f83638429a925415a10vboxsync%ifdef RT_ARCH_AMD64
ff308c5c63cf562048295f83638429a925415a10vboxsync %define CPUMR0_IS_AMD64 1
ff308c5c63cf562048295f83638429a925415a10vboxsync %define CPUMR0_IS_AMD64 0
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsync;*******************************************************************************
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsync;* External Symbols *
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsync;*******************************************************************************
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsyncextern NAME(SUPR0AbsIs64bit)
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsyncextern NAME(SUPR0Abs64bitKernelCS)
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsyncextern NAME(SUPR0Abs64bitKernelSS)
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsyncextern NAME(SUPR0Abs64bitKernelDS)
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsyncextern NAME(SUPR0AbsKernelCS)
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsync;*******************************************************************************
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsync;* Global Variables *
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsync;*******************************************************************************
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%if 0 ; Currently not used.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsyncg_r32_Zero: dd 0.0
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsync; Store the SUPR0AbsIs64bit absolute value here so we can cmp/test without
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsync; needing to clobber a register. (This trick doesn't quite work for PE btw.
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsync; but that's not relevant atm.)
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsyncGLOBALNAME g_fCPUMIs64bitHost
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsync dd NAME(SUPR0AbsIs64bit)
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%if 0 ; Currently not used anywhere.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; Macro for FXSAVE/FXRSTOR leaky behaviour on AMD CPUs, see cpumR3CheckLeakyFpu().
c3ad07071523338d76960d8da7678860aea8b03dvboxsync; Cleans the FPU state, if necessary, before restoring the FPU.
c3ad07071523338d76960d8da7678860aea8b03dvboxsync; This macro ASSUMES CR0.TS is not set!
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; @param xDX Pointer to CPUMCPU.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; @uses xAX, EFLAGS
2a5babc3ace611a3a900b61ff0659923994840bfvboxsync; Changes here should also be reflected in CPUMRCA.asm's copy!
c3ad07071523338d76960d8da7678860aea8b03dvboxsync%macro CLEANFPU 0
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync test dword [xDX + CPUMCPU.fUseFlags], CPUM_USE_FFXSR_LEAKY
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync jz .nothing_to_clean
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync xor eax, eax
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync fnstsw ax ; FSW -> AX.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync test eax, RT_BIT(7) ; If FSW.ES (bit 7) is set, clear it to not cause FPU exceptions
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync ; while clearing & loading the FPU bits in 'clean_fpu' below.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync jz .clean_fpu
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync ffree st7 ; Clear FPU stack register(7)'s tag entry to prevent overflow if a wraparound occurs.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync ; for the upcoming push (load)
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync fild dword [g_r32_Zero xWrtRIP] ; Explicit FPU load to overwrite FIP, FOP, FDP registers in the FPU.
c3ad07071523338d76960d8da7678860aea8b03dvboxsync.nothing_to_clean:
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%endif ; Unused.
ff308c5c63cf562048295f83638429a925415a10vboxsync; Clears CR0.TS and CR0.EM if necessary, saving the previous result.
ff308c5c63cf562048295f83638429a925415a10vboxsync; This is used to avoid FPU exceptions when touching the FPU state.
ff308c5c63cf562048295f83638429a925415a10vboxsync; @param %1 Register to save the old CR0 in (pass to RESTORE_CR0).
ff308c5c63cf562048295f83638429a925415a10vboxsync; @param %2 Temporary scratch register.
ff308c5c63cf562048295f83638429a925415a10vboxsync; @uses EFLAGS, CR0
ff308c5c63cf562048295f83638429a925415a10vboxsync%macro SAVE_CR0_CLEAR_FPU_TRAPS 2
ff308c5c63cf562048295f83638429a925415a10vboxsync mov %2, cr0
ff308c5c63cf562048295f83638429a925415a10vboxsync test %2, X86_CR0_TS | X86_CR0_EM ; Make sure its safe to access the FPU state.
ff308c5c63cf562048295f83638429a925415a10vboxsync jz %%skip_cr0_write
ff308c5c63cf562048295f83638429a925415a10vboxsync mov %1, %2 ; Save old CR0
ff308c5c63cf562048295f83638429a925415a10vboxsync and %2, ~(X86_CR0_TS | X86_CR0_EM)
ff308c5c63cf562048295f83638429a925415a10vboxsync mov cr0, %2
ff308c5c63cf562048295f83638429a925415a10vboxsync%%skip_cr0_write:
ff308c5c63cf562048295f83638429a925415a10vboxsync; Restore CR0.TS and CR0.EM state if SAVE_CR0_CLEAR_FPU_TRAPS change it.
ff308c5c63cf562048295f83638429a925415a10vboxsync; @param %1 The register that SAVE_CR0_CLEAR_FPU_TRAPS saved the old CR0 in.
ff308c5c63cf562048295f83638429a925415a10vboxsync%macro RESTORE_CR0 1
ff308c5c63cf562048295f83638429a925415a10vboxsync je %%skip_cr0_restore
ff308c5c63cf562048295f83638429a925415a10vboxsync mov cr0, %1
ff308c5c63cf562048295f83638429a925415a10vboxsync%%skip_cr0_restore:
ff308c5c63cf562048295f83638429a925415a10vboxsync; Saves the host state.
ff308c5c63cf562048295f83638429a925415a10vboxsync; @uses rax, rdx
ff308c5c63cf562048295f83638429a925415a10vboxsync; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
ff308c5c63cf562048295f83638429a925415a10vboxsync; @param pXState Define for the regsiter containing the extended state pointer.
ff308c5c63cf562048295f83638429a925415a10vboxsync%macro CPUMR0_SAVE_HOST 0
ff308c5c63cf562048295f83638429a925415a10vboxsync ; Load a couple of registers we'll use later in all branches.
ff308c5c63cf562048295f83638429a925415a10vboxsync mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
ff308c5c63cf562048295f83638429a925415a10vboxsync mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
ff308c5c63cf562048295f83638429a925415a10vboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
ff308c5c63cf562048295f83638429a925415a10vboxsync ; The joy of 32-bit darwin kernels that runs the CPU in 64-bit mode.
ff308c5c63cf562048295f83638429a925415a10vboxsync cmp byte [NAME(g_fCPUMIs64bitHost)], 0
ff308c5c63cf562048295f83638429a925415a10vboxsync jz %%host_legacy_mode
ff308c5c63cf562048295f83638429a925415a10vboxsync db 0xea ; jmp far .sixtyfourbit_mode
ff308c5c63cf562048295f83638429a925415a10vboxsync dd %%host_sixtyfourbit_mode, NAME(SUPR0Abs64bitKernelCS)
ff308c5c63cf562048295f83638429a925415a10vboxsync%%host_sixtyfourbit_mode:
ff308c5c63cf562048295f83638429a925415a10vboxsync or eax, eax
ff308c5c63cf562048295f83638429a925415a10vboxsync jz %%host_sixtyfourbit_fxsave
ff308c5c63cf562048295f83638429a925415a10vboxsync mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
ff308c5c63cf562048295f83638429a925415a10vboxsync o64 xsave [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync jmp %%host_sixtyfourbit_done
ff308c5c63cf562048295f83638429a925415a10vboxsync%%host_sixtyfourbit_fxsave:
ff308c5c63cf562048295f83638429a925415a10vboxsync o64 fxsave [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync%%host_sixtyfourbit_done:
ff308c5c63cf562048295f83638429a925415a10vboxsync jmp far [%%host_fpret wrt rip]
ff308c5c63cf562048295f83638429a925415a10vboxsync%%host_fpret: ; 16:32 Pointer to %%host_done.
ff308c5c63cf562048295f83638429a925415a10vboxsync dd %%host_done, NAME(SUPR0AbsKernelCS)
ff308c5c63cf562048295f83638429a925415a10vboxsync%%host_legacy_mode:
ff308c5c63cf562048295f83638429a925415a10vboxsync ; XSAVE or FXSAVE?
ff308c5c63cf562048295f83638429a925415a10vboxsync or eax, eax
ff308c5c63cf562048295f83638429a925415a10vboxsync jz %%host_fxsave
ff308c5c63cf562048295f83638429a925415a10vboxsync mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
ff308c5c63cf562048295f83638429a925415a10vboxsync%ifdef RT_ARCH_AMD64
ff308c5c63cf562048295f83638429a925415a10vboxsync o64 xsave [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync xsave [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync jmp %%host_done
ff308c5c63cf562048295f83638429a925415a10vboxsync%%host_fxsave:
ff308c5c63cf562048295f83638429a925415a10vboxsync%ifdef RT_ARCH_AMD64
ff308c5c63cf562048295f83638429a925415a10vboxsync o64 fxsave [pXState] ; Use explicit REX prefix. See @bugref{6398}.
ff308c5c63cf562048295f83638429a925415a10vboxsync fxsave [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync%%host_done:
ff308c5c63cf562048295f83638429a925415a10vboxsync%endmacro ; CPUMR0_SAVE_HOST
ff308c5c63cf562048295f83638429a925415a10vboxsync; Loads the host state.
ff308c5c63cf562048295f83638429a925415a10vboxsync; @uses rax, rdx
ff308c5c63cf562048295f83638429a925415a10vboxsync; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
ff308c5c63cf562048295f83638429a925415a10vboxsync; @param pXState Define for the regsiter containing the extended state pointer.
ff308c5c63cf562048295f83638429a925415a10vboxsync%macro CPUMR0_LOAD_HOST 0
ff308c5c63cf562048295f83638429a925415a10vboxsync ; Load a couple of registers we'll use later in all branches.
ff308c5c63cf562048295f83638429a925415a10vboxsync mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
ff308c5c63cf562048295f83638429a925415a10vboxsync mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
ff308c5c63cf562048295f83638429a925415a10vboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
ff308c5c63cf562048295f83638429a925415a10vboxsync ; The joy of 32-bit darwin kernels that runs the CPU in 64-bit mode.
ff308c5c63cf562048295f83638429a925415a10vboxsync cmp byte [NAME(g_fCPUMIs64bitHost)], 0
ff308c5c63cf562048295f83638429a925415a10vboxsync jz %%host_legacy_mode
ff308c5c63cf562048295f83638429a925415a10vboxsync db 0xea ; jmp far .sixtyfourbit_mode
ff308c5c63cf562048295f83638429a925415a10vboxsync dd %%host_sixtyfourbit_mode, NAME(SUPR0Abs64bitKernelCS)
ff308c5c63cf562048295f83638429a925415a10vboxsync%%host_sixtyfourbit_mode:
ff308c5c63cf562048295f83638429a925415a10vboxsync or eax, eax
ff308c5c63cf562048295f83638429a925415a10vboxsync jz %%host_sixtyfourbit_fxrstor
ff308c5c63cf562048295f83638429a925415a10vboxsync mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
ff308c5c63cf562048295f83638429a925415a10vboxsync o64 xrstor [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync jmp %%host_sixtyfourbit_done
ff308c5c63cf562048295f83638429a925415a10vboxsync%%host_sixtyfourbit_fxrstor:
ff308c5c63cf562048295f83638429a925415a10vboxsync o64 fxrstor [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync%%host_sixtyfourbit_done:
ff308c5c63cf562048295f83638429a925415a10vboxsync jmp far [%%host_fpret wrt rip]
ff308c5c63cf562048295f83638429a925415a10vboxsync%%host_fpret: ; 16:32 Pointer to %%host_done.
ff308c5c63cf562048295f83638429a925415a10vboxsync dd %%host_done, NAME(SUPR0AbsKernelCS)
ff308c5c63cf562048295f83638429a925415a10vboxsync%%host_legacy_mode:
ff308c5c63cf562048295f83638429a925415a10vboxsync ; XRSTOR or FXRSTOR?
ff308c5c63cf562048295f83638429a925415a10vboxsync or eax, eax
ff308c5c63cf562048295f83638429a925415a10vboxsync jz %%host_fxrstor
ff308c5c63cf562048295f83638429a925415a10vboxsync mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
ff308c5c63cf562048295f83638429a925415a10vboxsync%ifdef RT_ARCH_AMD64
ff308c5c63cf562048295f83638429a925415a10vboxsync o64 xrstor [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync xrstor [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync jmp %%host_done
ff308c5c63cf562048295f83638429a925415a10vboxsync%%host_fxrstor:
ff308c5c63cf562048295f83638429a925415a10vboxsync%ifdef RT_ARCH_AMD64
ff308c5c63cf562048295f83638429a925415a10vboxsync o64 fxrstor [pXState] ; Use explicit REX prefix. See @bugref{6398}.
ff308c5c63cf562048295f83638429a925415a10vboxsync fxrstor [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync%%host_done:
ff308c5c63cf562048295f83638429a925415a10vboxsync%endmacro ; CPUMR0_LOAD_HOST
d239ea80a55b621f0f0e0710e8a1b4762ddd6d0avboxsync;; Macro for FXSAVE for the guest FPU but tries to figure out whether to
d239ea80a55b621f0f0e0710e8a1b4762ddd6d0avboxsync; save the 32-bit FPU state or 64-bit FPU state.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; @param %1 Pointer to CPUMCPU.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; @param %2 Pointer to XState.
ff308c5c63cf562048295f83638429a925415a10vboxsync; @param %3 Force AMD64
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; @uses xAX, xDX, EFLAGS, 20h of stack.
ff308c5c63cf562048295f83638429a925415a10vboxsync%macro SAVE_32_OR_64_FPU 3
ff308c5c63cf562048295f83638429a925415a10vboxsync%if CPUMR0_IS_AMD64 || %3
ff308c5c63cf562048295f83638429a925415a10vboxsync ; Save the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
ff308c5c63cf562048295f83638429a925415a10vboxsync test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
ff308c5c63cf562048295f83638429a925415a10vboxsync jnz short %%save_long_mode_guest
ff308c5c63cf562048295f83638429a925415a10vboxsync fxsave [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync%if CPUMR0_IS_AMD64 || %3
ff308c5c63cf562048295f83638429a925415a10vboxsync jmp %%save_done_32bit_cs_ds
ff308c5c63cf562048295f83638429a925415a10vboxsync%%save_long_mode_guest:
ff308c5c63cf562048295f83638429a925415a10vboxsync o64 fxsave [pXState]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync xor edx, edx
ff308c5c63cf562048295f83638429a925415a10vboxsync cmp dword [pXState + CS_OFF_IN_X86FXSTATE], 0
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync jne short %%save_done
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync sub rsp, 20h ; Only need 1ch bytes but keep stack aligned otherwise we #GP(0).
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync fnstenv [rsp]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync movzx eax, word [rsp + 10h]
ff308c5c63cf562048295f83638429a925415a10vboxsync mov [pXState + CS_OFF_IN_X86FXSTATE], eax
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync movzx eax, word [rsp + 18h]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync add rsp, 20h
ff308c5c63cf562048295f83638429a925415a10vboxsync mov [pXState + DS_OFF_IN_X86FXSTATE], eax
ff308c5c63cf562048295f83638429a925415a10vboxsync%%save_done_32bit_cs_ds:
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync mov edx, X86_FXSTATE_RSVD_32BIT_MAGIC
d239ea80a55b621f0f0e0710e8a1b4762ddd6d0avboxsync%%save_done:
ff308c5c63cf562048295f83638429a925415a10vboxsync mov dword [pXState + X86_OFF_FXSTATE_RSVD], edx
ff308c5c63cf562048295f83638429a925415a10vboxsync%endmacro ; SAVE_32_OR_64_FPU
ff308c5c63cf562048295f83638429a925415a10vboxsync; Save the guest state.
ff308c5c63cf562048295f83638429a925415a10vboxsync; @uses rax, rdx
ff308c5c63cf562048295f83638429a925415a10vboxsync; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
ff308c5c63cf562048295f83638429a925415a10vboxsync; @param pXState Define for the regsiter containing the extended state pointer.
ff308c5c63cf562048295f83638429a925415a10vboxsync%macro CPUMR0_SAVE_GUEST 0
ff308c5c63cf562048295f83638429a925415a10vboxsync ; Load a couple of registers we'll use later in all branches.
ff308c5c63cf562048295f83638429a925415a10vboxsync mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
ff308c5c63cf562048295f83638429a925415a10vboxsync mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
ff308c5c63cf562048295f83638429a925415a10vboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
ff308c5c63cf562048295f83638429a925415a10vboxsync ; The joy of 32-bit darwin kernels that runs the CPU in 64-bit mode.
ff308c5c63cf562048295f83638429a925415a10vboxsync cmp byte [NAME(g_fCPUMIs64bitHost)], 0
ff308c5c63cf562048295f83638429a925415a10vboxsync jz %%guest_legacy_mode
ff308c5c63cf562048295f83638429a925415a10vboxsync db 0xea ; jmp far .sixtyfourbit_mode
ff308c5c63cf562048295f83638429a925415a10vboxsync dd %%guest_sixtyfourbit_mode, NAME(SUPR0Abs64bitKernelCS)
ff308c5c63cf562048295f83638429a925415a10vboxsync%%guest_sixtyfourbit_mode:
ff308c5c63cf562048295f83638429a925415a10vboxsync or eax, eax
ff308c5c63cf562048295f83638429a925415a10vboxsync jz %%guest_sixtyfourbit_fxsave
ff308c5c63cf562048295f83638429a925415a10vboxsync mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
ff308c5c63cf562048295f83638429a925415a10vboxsync o64 xsave [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync jmp %%guest_sixtyfourbit_done
ff308c5c63cf562048295f83638429a925415a10vboxsync%%guest_sixtyfourbit_fxsave:
ff308c5c63cf562048295f83638429a925415a10vboxsync SAVE_32_OR_64_FPU pCpumCpu, pXState, 1
ff308c5c63cf562048295f83638429a925415a10vboxsync%%guest_sixtyfourbit_done:
ff308c5c63cf562048295f83638429a925415a10vboxsync jmp far [%%guest_fpret wrt rip]
ff308c5c63cf562048295f83638429a925415a10vboxsync%%guest_fpret: ; 16:32 Pointer to %%guest_done.
ff308c5c63cf562048295f83638429a925415a10vboxsync dd %%guest_done, NAME(SUPR0AbsKernelCS)
ff308c5c63cf562048295f83638429a925415a10vboxsync%%guest_legacy_mode:
ff308c5c63cf562048295f83638429a925415a10vboxsync ; XSAVE or FXSAVE?
ff308c5c63cf562048295f83638429a925415a10vboxsync or eax, eax
ff308c5c63cf562048295f83638429a925415a10vboxsync jz %%guest_fxsave
ff308c5c63cf562048295f83638429a925415a10vboxsync mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
ff308c5c63cf562048295f83638429a925415a10vboxsync%ifdef RT_ARCH_AMD64
ff308c5c63cf562048295f83638429a925415a10vboxsync o64 xsave [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync xsave [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync jmp %%guest_done
ff308c5c63cf562048295f83638429a925415a10vboxsync%%guest_fxsave:
ff308c5c63cf562048295f83638429a925415a10vboxsync SAVE_32_OR_64_FPU pCpumCpu, pXState, 0
ff308c5c63cf562048295f83638429a925415a10vboxsync%%guest_done:
ff308c5c63cf562048295f83638429a925415a10vboxsync%endmacro ; CPUMR0_SAVE_GUEST
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; Wrapper for selecting 32-bit or 64-bit FXRSTOR according to what SAVE_32_OR_64_FPU did.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; @param %1 Pointer to CPUMCPU.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; @param %2 Pointer to XState.
ff308c5c63cf562048295f83638429a925415a10vboxsync; @param %3 Force AMD64.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; @uses xAX, xDX, EFLAGS
ff308c5c63cf562048295f83638429a925415a10vboxsync%macro RESTORE_32_OR_64_FPU 3
ff308c5c63cf562048295f83638429a925415a10vboxsync%if CPUMR0_IS_AMD64 || %3
ff308c5c63cf562048295f83638429a925415a10vboxsync ; Restore the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
ff308c5c63cf562048295f83638429a925415a10vboxsync test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
ff308c5c63cf562048295f83638429a925415a10vboxsync jz %%restore_32bit_fpu
ff308c5c63cf562048295f83638429a925415a10vboxsync cmp dword [pXState + X86_OFF_FXSTATE_RSVD], X86_FXSTATE_RSVD_32BIT_MAGIC
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync jne short %%restore_64bit_fpu
ff308c5c63cf562048295f83638429a925415a10vboxsync%%restore_32bit_fpu:
ff308c5c63cf562048295f83638429a925415a10vboxsync fxrstor [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync%if CPUMR0_IS_AMD64 || %3
ff308c5c63cf562048295f83638429a925415a10vboxsync ; TODO: Restore XMM8-XMM15!
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync jmp short %%restore_fpu_done
d239ea80a55b621f0f0e0710e8a1b4762ddd6d0avboxsync%%restore_64bit_fpu:
ff308c5c63cf562048295f83638429a925415a10vboxsync o64 fxrstor [pXState]
d239ea80a55b621f0f0e0710e8a1b4762ddd6d0avboxsync%%restore_fpu_done:
ff308c5c63cf562048295f83638429a925415a10vboxsync%endmacro ; RESTORE_32_OR_64_FPU
ff308c5c63cf562048295f83638429a925415a10vboxsync; Loads the guest state.
ff308c5c63cf562048295f83638429a925415a10vboxsync; @uses rax, rdx
ff308c5c63cf562048295f83638429a925415a10vboxsync; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
ff308c5c63cf562048295f83638429a925415a10vboxsync; @param pXState Define for the regsiter containing the extended state pointer.
ff308c5c63cf562048295f83638429a925415a10vboxsync%macro CPUMR0_LOAD_GUEST 0
ff308c5c63cf562048295f83638429a925415a10vboxsync ; Load a couple of registers we'll use later in all branches.
ff308c5c63cf562048295f83638429a925415a10vboxsync mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
ff308c5c63cf562048295f83638429a925415a10vboxsync mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
ff308c5c63cf562048295f83638429a925415a10vboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
ff308c5c63cf562048295f83638429a925415a10vboxsync ; The joy of 32-bit darwin kernels that runs the CPU in 64-bit mode.
ff308c5c63cf562048295f83638429a925415a10vboxsync cmp byte [NAME(g_fCPUMIs64bitHost)], 0
ff308c5c63cf562048295f83638429a925415a10vboxsync jz %%guest_legacy_mode
ff308c5c63cf562048295f83638429a925415a10vboxsync db 0xea ; jmp far .sixtyfourbit_mode
ff308c5c63cf562048295f83638429a925415a10vboxsync dd %%guest_sixtyfourbit_mode, NAME(SUPR0Abs64bitKernelCS)
ff308c5c63cf562048295f83638429a925415a10vboxsync%%guest_sixtyfourbit_mode:
ff308c5c63cf562048295f83638429a925415a10vboxsync or eax, eax
ff308c5c63cf562048295f83638429a925415a10vboxsync jz %%guest_sixtyfourbit_fxrstor
ff308c5c63cf562048295f83638429a925415a10vboxsync mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
ff308c5c63cf562048295f83638429a925415a10vboxsync o64 xrstor [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync jmp %%guest_sixtyfourbit_done
ff308c5c63cf562048295f83638429a925415a10vboxsync%%guest_sixtyfourbit_fxrstor:
ff308c5c63cf562048295f83638429a925415a10vboxsync RESTORE_32_OR_64_FPU pCpumCpu, pXState, 1
ff308c5c63cf562048295f83638429a925415a10vboxsync%%guest_sixtyfourbit_done:
ff308c5c63cf562048295f83638429a925415a10vboxsync jmp far [%%guest_fpret wrt rip]
ff308c5c63cf562048295f83638429a925415a10vboxsync%%guest_fpret: ; 16:32 Pointer to %%guest_done.
ff308c5c63cf562048295f83638429a925415a10vboxsync dd %%guest_done, NAME(SUPR0AbsKernelCS)
ff308c5c63cf562048295f83638429a925415a10vboxsync%%guest_legacy_mode:
ff308c5c63cf562048295f83638429a925415a10vboxsync ; XRSTOR or FXRSTOR?
ff308c5c63cf562048295f83638429a925415a10vboxsync or eax, eax
ff308c5c63cf562048295f83638429a925415a10vboxsync jz %%guest_fxrstor
ff308c5c63cf562048295f83638429a925415a10vboxsync mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
ff308c5c63cf562048295f83638429a925415a10vboxsync%ifdef RT_ARCH_AMD64
ff308c5c63cf562048295f83638429a925415a10vboxsync o64 xrstor [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync xrstor [pXState]
ff308c5c63cf562048295f83638429a925415a10vboxsync jmp %%guest_done
ff308c5c63cf562048295f83638429a925415a10vboxsync%%guest_fxrstor:
ff308c5c63cf562048295f83638429a925415a10vboxsync RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0
ff308c5c63cf562048295f83638429a925415a10vboxsync%%guest_done:
ff308c5c63cf562048295f83638429a925415a10vboxsync%endmacro ; CPUMR0_LOAD_GUEST
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; Saves the host FPU/SSE/AVX state and restores the guest FPU/SSE/AVX state.
90f2027a781d66b7498ed1e5684e087e4d9d3b1bvboxsync; @returns 0
2bc1e783ef90b85482496df5a124421431650546vboxsync; @param pCpumCpu x86:[ebp+8] gcc:rdi msc:rcx CPUMCPU pointer
90f2027a781d66b7498ed1e5684e087e4d9d3b1bvboxsyncBEGINPROC cpumR0SaveHostRestoreGuestFPUState
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync ; Prologue - xAX+xDX must be free for XSAVE/XRSTOR input.
90f2027a781d66b7498ed1e5684e087e4d9d3b1bvboxsync%ifdef RT_ARCH_AMD64
90f2027a781d66b7498ed1e5684e087e4d9d3b1bvboxsync %ifdef RT_OS_WINDOWS
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync mov r11, rcx
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync mov r11, rdi
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pCpumCpu r11
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pXState r10
2bc1e783ef90b85482496df5a124421431650546vboxsync mov ebp, esp
2bc1e783ef90b85482496df5a124421431650546vboxsync mov ebx, dword [ebp + 8]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pCpumCpu ebx
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pXState esi
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync pushf ; The darwin kernel can get upset or upset things if an
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync cli ; interrupt occurs while we're doing fxsave/fxrstor/cr0.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync SAVE_CR0_CLEAR_FPU_TRAPS xCX, xAX ; xCX is now old CR0 value, don't use!
ff308c5c63cf562048295f83638429a925415a10vboxsync CPUMR0_SAVE_HOST
ff308c5c63cf562048295f83638429a925415a10vboxsync CPUMR0_LOAD_GUEST
bb33bc2ad72088bbb39737f7145a6cfbe1f65780vboxsync%ifdef VBOX_WITH_KERNEL_USING_XMM
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync ; Restore the non-volatile xmm registers. ASSUMING 64-bit host.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync movdqa xmm6, [pXState + XMM_OFF_IN_X86FXSTATE + 060h]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync movdqa xmm7, [pXState + XMM_OFF_IN_X86FXSTATE + 070h]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync movdqa xmm8, [pXState + XMM_OFF_IN_X86FXSTATE + 080h]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync movdqa xmm9, [pXState + XMM_OFF_IN_X86FXSTATE + 090h]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync movdqa xmm10, [pXState + XMM_OFF_IN_X86FXSTATE + 0a0h]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync movdqa xmm11, [pXState + XMM_OFF_IN_X86FXSTATE + 0b0h]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync movdqa xmm12, [pXState + XMM_OFF_IN_X86FXSTATE + 0c0h]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync movdqa xmm13, [pXState + XMM_OFF_IN_X86FXSTATE + 0d0h]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync movdqa xmm14, [pXState + XMM_OFF_IN_X86FXSTATE + 0e0h]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync movdqa xmm15, [pXState + XMM_OFF_IN_X86FXSTATE + 0f0h]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync RESTORE_CR0 xCX
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync or dword [pCpumCpu + CPUMCPU.fUseFlags], (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM)
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%ifdef RT_ARCH_X86
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync xor eax, eax
90f2027a781d66b7498ed1e5684e087e4d9d3b1bvboxsyncENDPROC cpumR0SaveHostRestoreGuestFPUState
3bf5a39c9314b43d8fe91e4ed18b977e2f87659dvboxsync%ifndef RT_ARCH_AMD64
3bf5a39c9314b43d8fe91e4ed18b977e2f87659dvboxsync%ifdef VBOX_WITH_64_BITS_GUESTS
3bf5a39c9314b43d8fe91e4ed18b977e2f87659dvboxsync%ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; Saves the host FPU/SSE/AVX state.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; @returns VINF_SUCCESS (0) in EAX
2bc1e783ef90b85482496df5a124421431650546vboxsync; @param pCpumCpu x86:[ebp+8] gcc:rdi msc:rcx CPUMCPU pointer
3bf5a39c9314b43d8fe91e4ed18b977e2f87659dvboxsyncBEGINPROC cpumR0SaveHostFPUState
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync ; Prologue - xAX+xDX must be free for XSAVE/XRSTOR input.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%ifdef RT_ARCH_AMD64
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %ifdef RT_OS_WINDOWS
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync mov r11, rcx
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync mov r11, rdi
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pCpumCpu r11
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pXState r10
2bc1e783ef90b85482496df5a124421431650546vboxsync mov ebp, esp
2bc1e783ef90b85482496df5a124421431650546vboxsync mov ebx, dword [ebp + 8]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pCpumCpu ebx
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pXState esi
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync pushf ; The darwin kernel can get upset or upset things if an
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync cli ; interrupt occurs while we're doing fxsave/fxrstor/cr0.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync SAVE_CR0_CLEAR_FPU_TRAPS xCX, xAX ; xCX is now old CR0 value, don't use!
ff308c5c63cf562048295f83638429a925415a10vboxsync CPUMR0_SAVE_HOST
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync RESTORE_CR0 xCX
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync or dword [pCpumCpu + CPUMCPU.fUseFlags], (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM)
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%ifdef RT_ARCH_X86
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync xor eax, eax
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsyncALIGNCODE(16)
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync.sixtyfourbit_mode:
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync ; Save the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync o64 fxsave [pXstate]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync jmp far [.fpret wrt rip]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync.fpret: ; 16:32 Pointer to .the_end.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync dd .done, NAME(SUPR0AbsKernelCS)
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%undef pCpumCpu
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%undef pXState
3bf5a39c9314b43d8fe91e4ed18b977e2f87659dvboxsyncENDPROC cpumR0SaveHostFPUState
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; Saves the guest FPU/SSE/AVX state and restores the host FPU/SSE/AVX state.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; @returns VINF_SUCCESS (0) in eax.
2bc1e783ef90b85482496df5a124421431650546vboxsync; @param pCpumCpu x86:[ebp+8] gcc:rdi msc:rcx CPUMCPU pointer
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsyncBEGINPROC cpumR0SaveGuestRestoreHostFPUState
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync ; Prologue - xAX+xDX must be free for XSAVE/XRSTOR input.
52676b598e9afd834db7f3e62a983044038e92bevboxsync%ifdef RT_ARCH_AMD64
52676b598e9afd834db7f3e62a983044038e92bevboxsync %ifdef RT_OS_WINDOWS
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync mov r11, rcx
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync mov r11, rdi
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pCpumCpu r11
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pXState r10
2bc1e783ef90b85482496df5a124421431650546vboxsync mov ebp, esp
2bc1e783ef90b85482496df5a124421431650546vboxsync mov ebx, dword [ebp + 8]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pCpumCpu ebx
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pXState esi
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync ; Only restore FPU if guest has used it.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USED_FPU
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync jz .fpu_not_used
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync pushf ; The darwin kernel can get upset or upset things if an
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync cli ; interrupt occurs while we're doing fxsave/fxrstor/cr0.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync SAVE_CR0_CLEAR_FPU_TRAPS xCX, xAX ; xCX is now old CR0 value, don't use!
ff308c5c63cf562048295f83638429a925415a10vboxsync CPUMR0_SAVE_GUEST
ff308c5c63cf562048295f83638429a925415a10vboxsync CPUMR0_LOAD_HOST
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync RESTORE_CR0 xCX
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync and dword [pCpumCpu + CPUMCPU.fUseFlags], ~CPUM_USED_FPU
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsync.fpu_not_used:
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%ifdef RT_ARCH_X86
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync xor eax, eax
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%undef pCpumCpu
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%undef pXState
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsyncENDPROC cpumR0SaveGuestRestoreHostFPUState
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync; Restores the host's FPU/SSE/AVX state from pCpumCpu->Host.
52676b598e9afd834db7f3e62a983044038e92bevboxsync; @returns 0
2bc1e783ef90b85482496df5a124421431650546vboxsync; @param pCpumCpu x86:[ebp+8] gcc:rdi msc:rcx CPUMCPU pointer
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsyncBEGINPROC cpumR0RestoreHostFPUState
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync ; Prologue - xAX+xDX must be free for XSAVE/XRSTOR input.
52676b598e9afd834db7f3e62a983044038e92bevboxsync%ifdef RT_ARCH_AMD64
52676b598e9afd834db7f3e62a983044038e92bevboxsync %ifdef RT_OS_WINDOWS
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync mov r11, rcx
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync mov r11, rdi
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pCpumCpu r11
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pXState r10
2bc1e783ef90b85482496df5a124421431650546vboxsync mov ebp, esp
2bc1e783ef90b85482496df5a124421431650546vboxsync mov ebx, dword [ebp + 8]
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pCpumCpu ebx
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync %define pXState esi
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync ; Restore FPU if guest has used it.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USED_FPU
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync jz short .fpu_not_used
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync pushf ; The darwin kernel can get upset or upset things if an
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync cli ; interrupt occurs while we're doing fxsave/fxrstor/cr0.
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync SAVE_CR0_CLEAR_FPU_TRAPS xCX, xAX ; xCX is now old CR0 value, don't use!
ff308c5c63cf562048295f83638429a925415a10vboxsync CPUMR0_LOAD_HOST
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync RESTORE_CR0 xCX
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync and dword [pCpumCpu + CPUMCPU.fUseFlags], ~CPUM_USED_FPU
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsync.fpu_not_used:
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%ifdef RT_ARCH_X86
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync xor eax, eax
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%undef pCpumCPu
447d6c76d88201b58c0bd7b0c8621088cf428951vboxsync%undef pXState
a41a001e5a4dd3f39faab90b412243ced6d59394vboxsyncENDPROC cpumR0RestoreHostFPUState
409950536f73e7c9a387f7d548122ae6bffae950vboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
409950536f73e7c9a387f7d548122ae6bffae950vboxsync; DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
409950536f73e7c9a387f7d548122ae6bffae950vboxsyncALIGNCODE(16)
409950536f73e7c9a387f7d548122ae6bffae950vboxsyncBEGINPROC cpumR0SaveDRx
409950536f73e7c9a387f7d548122ae6bffae950vboxsync%ifdef RT_ARCH_AMD64
409950536f73e7c9a387f7d548122ae6bffae950vboxsync %ifdef ASM_CALL64_GCC
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov xCX, rdi
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov xCX, dword [esp + 4]
c5a332cfb15a444b40d1564a0c1e73899c1a3b2bvboxsync pushf ; Just to be on the safe side.
409950536f73e7c9a387f7d548122ae6bffae950vboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
409950536f73e7c9a387f7d548122ae6bffae950vboxsync cmp byte [NAME(g_fCPUMIs64bitHost)], 0
409950536f73e7c9a387f7d548122ae6bffae950vboxsync jz .legacy_mode
409950536f73e7c9a387f7d548122ae6bffae950vboxsync db 0xea ; jmp far .sixtyfourbit_mode
409950536f73e7c9a387f7d548122ae6bffae950vboxsync dd .sixtyfourbit_mode, NAME(SUPR0Abs64bitKernelCS)
409950536f73e7c9a387f7d548122ae6bffae950vboxsync.legacy_mode:
409950536f73e7c9a387f7d548122ae6bffae950vboxsync%endif ; VBOX_WITH_HYBRID_32BIT_KERNEL
409950536f73e7c9a387f7d548122ae6bffae950vboxsync ; Do the job.
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov xAX, dr0
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov xDX, dr1
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov [xCX], xAX
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov [xCX + 8 * 1], xDX
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov xAX, dr2
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov xDX, dr3
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov [xCX + 8 * 2], xAX
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov [xCX + 8 * 3], xDX
409950536f73e7c9a387f7d548122ae6bffae950vboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
409950536f73e7c9a387f7d548122ae6bffae950vboxsyncALIGNCODE(16)
409950536f73e7c9a387f7d548122ae6bffae950vboxsync.sixtyfourbit_mode:
409950536f73e7c9a387f7d548122ae6bffae950vboxsync and ecx, 0ffffffffh
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov rax, dr0
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov rdx, dr1
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov r8, dr2
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov r9, dr3
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov [rcx], rax
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov [rcx + 8 * 1], rdx
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov [rcx + 8 * 2], r8
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov [rcx + 8 * 3], r9
409950536f73e7c9a387f7d548122ae6bffae950vboxsync jmp far [.fpret wrt rip]
409950536f73e7c9a387f7d548122ae6bffae950vboxsync.fpret: ; 16:32 Pointer to .the_end.
409950536f73e7c9a387f7d548122ae6bffae950vboxsync dd .done, NAME(SUPR0AbsKernelCS)
409950536f73e7c9a387f7d548122ae6bffae950vboxsyncENDPROC cpumR0SaveDRx
409950536f73e7c9a387f7d548122ae6bffae950vboxsync; DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
409950536f73e7c9a387f7d548122ae6bffae950vboxsyncALIGNCODE(16)
409950536f73e7c9a387f7d548122ae6bffae950vboxsyncBEGINPROC cpumR0LoadDRx
409950536f73e7c9a387f7d548122ae6bffae950vboxsync%ifdef RT_ARCH_AMD64
409950536f73e7c9a387f7d548122ae6bffae950vboxsync %ifdef ASM_CALL64_GCC
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov xCX, rdi
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov xCX, dword [esp + 4]
c5a332cfb15a444b40d1564a0c1e73899c1a3b2bvboxsync pushf ; Just to be on the safe side.
409950536f73e7c9a387f7d548122ae6bffae950vboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
409950536f73e7c9a387f7d548122ae6bffae950vboxsync cmp byte [NAME(g_fCPUMIs64bitHost)], 0
409950536f73e7c9a387f7d548122ae6bffae950vboxsync jz .legacy_mode
409950536f73e7c9a387f7d548122ae6bffae950vboxsync db 0xea ; jmp far .sixtyfourbit_mode
409950536f73e7c9a387f7d548122ae6bffae950vboxsync dd .sixtyfourbit_mode, NAME(SUPR0Abs64bitKernelCS)
409950536f73e7c9a387f7d548122ae6bffae950vboxsync.legacy_mode:
409950536f73e7c9a387f7d548122ae6bffae950vboxsync%endif ; VBOX_WITH_HYBRID_32BIT_KERNEL
409950536f73e7c9a387f7d548122ae6bffae950vboxsync ; Do the job.
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov xAX, [xCX]
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov xDX, [xCX + 8 * 1]
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov dr0, xAX
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov dr1, xDX
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov xAX, [xCX + 8 * 2]
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov xDX, [xCX + 8 * 3]
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov dr2, xAX
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov dr3, xDX
409950536f73e7c9a387f7d548122ae6bffae950vboxsync%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
409950536f73e7c9a387f7d548122ae6bffae950vboxsyncALIGNCODE(16)
409950536f73e7c9a387f7d548122ae6bffae950vboxsync.sixtyfourbit_mode:
409950536f73e7c9a387f7d548122ae6bffae950vboxsync and ecx, 0ffffffffh
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov rax, [rcx]
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov rdx, [rcx + 8 * 1]
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov r8, [rcx + 8 * 2]
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov r9, [rcx + 8 * 3]
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov dr0, rax
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov dr1, rdx
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov dr2, r8
409950536f73e7c9a387f7d548122ae6bffae950vboxsync mov dr3, r9
409950536f73e7c9a387f7d548122ae6bffae950vboxsync jmp far [.fpret wrt rip]
409950536f73e7c9a387f7d548122ae6bffae950vboxsync.fpret: ; 16:32 Pointer to .the_end.
409950536f73e7c9a387f7d548122ae6bffae950vboxsync dd .done, NAME(SUPR0AbsKernelCS)
409950536f73e7c9a387f7d548122ae6bffae950vboxsyncENDPROC cpumR0LoadDRx
409950536f73e7c9a387f7d548122ae6bffae950vboxsync%endif ; VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0