VMM/VMMR0/CPUMR0.cpp

	CPUMR0.cpp revision d8a23af9e839b76190777c3be93a8517751d4c0c
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync/* $Id$ */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync/** @file
0f70ed40798198e1d9099c6ae3bdb239d2b8cf0dvboxsync * CPUM - Host Context Ring 0.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync */
0f70ed40798198e1d9099c6ae3bdb239d2b8cf0dvboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync/*
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync * Copyright (C) 2006-2011 Oracle Corporation
a9749534ba173982f6c3bafe8d51ccd22960e493vboxsync *
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
82bcaaf8077ba892f39afb721dca149353c63d2cvboxsync * available from http://www.virtualbox.org. This file is free software;
82bcaaf8077ba892f39afb721dca149353c63d2cvboxsync * you can redistribute it and/or modify it under the terms of the GNU
82bcaaf8077ba892f39afb721dca149353c63d2cvboxsync * General Public License (GPL) as published by the Free Software
82bcaaf8077ba892f39afb721dca149353c63d2cvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
82bcaaf8077ba892f39afb721dca149353c63d2cvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
82bcaaf8077ba892f39afb721dca149353c63d2cvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
82bcaaf8077ba892f39afb721dca149353c63d2cvboxsync */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync/*******************************************************************************
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync*   Header Files                                                               *
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync*******************************************************************************/
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#define LOG_GROUP LOG_GROUP_CPUM
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#include <VBox/vmm/cpum.h>
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync#include "CPUMInternal.h"
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync#include <VBox/vmm/vm.h>
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync#include <VBox/err.h>
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync#include <VBox/log.h>
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync#include <VBox/vmm/hwaccm.h>
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync#include <iprt/assert.h>
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync#include <iprt/asm-amd64-x86.h>
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync# include <iprt/mem.h>
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync# include <iprt/memobj.h>
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync# include <VBox/apic.h>
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#endif
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#include <iprt/x86.h>
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync/*******************************************************************************
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync*   Structures and Typedefs                                                    *
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync*******************************************************************************/
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync/**
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync * Local APIC mappings.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync */
e2843ed205192b88e54eef60ad541d00bbbc932avboxsynctypedef struct CPUMHOSTLAPIC
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync{
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    /** Indicates that the entry is in use and have valid data. */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    bool        fEnabled;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    /** Has APIC_REG_LVT_THMR. Not used. */
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync    uint32_t    fHasThermal;
500aaaf3dc1d98456808e7618db3fb2e7c8fb8e0vboxsync    /** The physical address of the APIC registers. */
8ffcab9595cc0d56977968cd496363502fd814aevboxsync    RTHCPHYS    PhysBase;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    /** The memory object entering the physical address. */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    RTR0MEMOBJ  hMemObj;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    /** The mapping object for hMemObj. */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    RTR0MEMOBJ  hMapObj;
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync    /** The mapping address APIC registers.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     * @remarks Different CPUs may use the same physical address to map their
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *          APICs, so this pointer is only valid when on the CPU owning the
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *          APIC. */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    void       *pv;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync} CPUMHOSTLAPIC;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#endif
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync/*******************************************************************************
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync*   Global Variables                                                           *
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync*******************************************************************************/
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsyncstatic CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#endif
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync/*******************************************************************************
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync*   Internal Functions                                                         *
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync*******************************************************************************/
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
e2843ed205192b88e54eef60ad541d00bbbc932avboxsyncstatic int  cpumR0MapLocalApics(void);
e2843ed205192b88e54eef60ad541d00bbbc932avboxsyncstatic void cpumR0UnmapLocalApics(void);
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync#endif
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync/**
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync * Does the Ring-0 CPU initialization once during module load.
77da7a074c86956d36759983037056c00cb87535vboxsync * XXX Host-CPU hot-plugging?
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync */
e2843ed205192b88e54eef60ad541d00bbbc932avboxsyncVMMR0DECL(int) CPUMR0ModuleInit(void)
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync{
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync    int rc = VINF_SUCCESS;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    rc = cpumR0MapLocalApics();
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync#endif
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync    return rc;
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync}
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync/**
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync * Terminate the module.
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync */
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsyncVMMR0DECL(int) CPUMR0ModuleTerm(void)
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync{
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
d5b5f09d8841828e647de9da5003fda55ca4cd5evboxsync    cpumR0UnmapLocalApics();
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync#endif
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync    return VINF_SUCCESS;
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync}
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync/**
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync * Does Ring-0 CPUM initialization.
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync *
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync * This is mainly to check that the Host CPU mode is compatible
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync * with VBox.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync *
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync * @returns VBox status code.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync * @param   pVM         The VM to operate on.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsyncVMMR0DECL(int) CPUMR0Init(PVM pVM)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync{
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    LogFlow(("CPUMR0Init: %p\n", pVM));
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    /*
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     * Check CR0 & CR4 flags.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    uint32_t u32CR0 = ASMGetCR0();
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    if ((u32CR0 & (X86_CR0_PE | X86_CR0_PG)) != (X86_CR0_PE | X86_CR0_PG)) /* a bit paranoid perhaps.. */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    {
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        return VERR_UNSUPPORTED_CPU_MODE;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    }
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    /*
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     * Check for sysenter and syscall usage.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     */
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync    if (ASMHasCpuId())
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    {
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync        /*
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync         * SYSENTER/SYSEXIT
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync         *
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync         * Intel docs claim you should test both the flag and family, model &
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync         * stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync         * but don't support it.  AMD CPUs may support this feature in legacy
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync         * mode, they've banned it from long mode.  Since we switch to 32-bit
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync         * mode when entering raw-mode context the feature would become
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         * accessible again on AMD CPUs, so we have to check regardless of
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         * host bitness.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        uint32_t u32CpuVersion;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        uint32_t u32Dummy;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        uint32_t fFeatures;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        uint32_t u32Family   = u32CpuVersion >> 8;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        uint32_t u32Model    = (u32CpuVersion >> 4) & 0xF;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        uint32_t u32Stepping = u32CpuVersion & 0xF;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        if (    (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            &&  (   u32Family   != 6    /* (> pentium pro) */
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync                 || u32Model    >= 3
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync                 || u32Stepping >= 3
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                 || !ASMIsIntelCpu())
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync           )
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync        {
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync            /*
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync             * Read the MSR and see if it's in use or not.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync             */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            if (u32)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            {
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                pVM->cpum.s.fHostUseFlags |= CPUM_USE_SYSENTER;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            }
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        }
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        /*
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         * SYSCALL/SYSRET
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         *
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         * This feature is indicated by the SEP bit returned in EDX by CPUID
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         * function 0x80000001.  Intel CPUs only supports this feature in
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         * long mode.  Since we're not running 64-bit guests in raw-mode there
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         * are no issues with 32-bit intel hosts.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        uint32_t cExt = 0;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        if (    cExt >= 0x80000001
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            &&  cExt <= 0x8000ffff)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        {
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_SEP)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            {
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#ifdef RT_ARCH_X86
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync# else
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                if (!ASMIsIntelCpu())
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync# endif
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#endif
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                {
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                    uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                    if (fEfer & MSR_K6_EFER_SCE)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                    {
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                        pVM->cpum.s.fHostUseFlags |= CPUM_USE_SYSCALL;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                        Log(("CPUMR0Init: host uses syscall\n"));
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                    }
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                }
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            }
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        }
77da7a074c86956d36759983037056c00cb87535vboxsync    }
77da7a074c86956d36759983037056c00cb87535vboxsync
77da7a074c86956d36759983037056c00cb87535vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    /*
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     * Check if debug registers are armed.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     * This ASSUMES that DR7.GD is not set, or that it's handled transparently!
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    uint32_t u32DR7 = ASMGetDR7();
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    if (u32DR7 & X86_DR7_ENABLED_MASK)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    {
8ffcab9595cc0d56977968cd496363502fd814aevboxsync        for (VMCPUID i = 0; i < pVM->cCpus; i++)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
7f67048412d241d45c0835b9c403a5bb1c879030vboxsync    }
8ffcab9595cc0d56977968cd496363502fd814aevboxsync
8ffcab9595cc0d56977968cd496363502fd814aevboxsync    return VINF_SUCCESS;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync}
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync/**
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync * Lazily sync in the FPU/XMM state
7f67048412d241d45c0835b9c403a5bb1c879030vboxsync *
7f67048412d241d45c0835b9c403a5bb1c879030vboxsync * @returns VBox status code.
7f67048412d241d45c0835b9c403a5bb1c879030vboxsync * @param   pVM         VM handle.
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync * @param   pVCpu       VMCPU handle.
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync * @param   pCtx        CPU context
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsyncVMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync{
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync    Assert(ASMGetCR4() & X86_CR4_OSFSXR);
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync    /* If the FPU state has already been loaded, then it's a guest trap. */
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync    if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU)
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync    {
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync        Assert(    ((pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync               ||  ((pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)));
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        return VINF_EM_RAW_GUEST_TRAP;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    }
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync    /*
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     * There are two basic actions:
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *   1. Save host fpu and restore guest fpu.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *   2. Generate guest trap.
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync     *
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     * When entering the hypervisor we'll always enable MP (for proper wait
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     * trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     * is taken from the guest OS in order to get proper SSE handling.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     * Actions taken depending on the guest CR0 flags:
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *   3    2    1
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *  TS | EM | MP | FPUInstr | WAIT :: VMM Action
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     * ------------------------------------------------------------------------
8a8d7629deae8875b70c6899e8b0f683b2a543e1vboxsync     *   0 |  0 |  0 | Exec     | Exec :: Clear TS & MP, Save HC, Load GC.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *   0 |  0 |  1 | Exec     | Exec :: Clear TS, Save HC, Load GC.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *   0 |  1 |  0 | #NM      | Exec :: Clear TS & MP, Save HC, Load GC.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *   0 |  1 |  1 | #NM      | Exec :: Clear TS, Save HC, Load GC.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *   1 |  0 |  0 | #NM      | Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *   1 |  0 |  1 | #NM      | #NM  :: Go to guest taking trap there.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *   1 |  1 |  0 | #NM      | Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync     *   1 |  1 |  1 | #NM      | #NM  :: Go to guest taking trap there.
8a8d7629deae8875b70c6899e8b0f683b2a543e1vboxsync     */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    switch (pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    {
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        case X86_CR0_MP | X86_CR0_TS:
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        case X86_CR0_MP | X86_CR0_EM | X86_CR0_TS:
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            return VINF_EM_RAW_GUEST_TRAP;
8a8d7629deae8875b70c6899e8b0f683b2a543e1vboxsync        default:
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            break;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    }
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    if (CPUMIsGuestInLongModeEx(pCtx))
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    {
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        /* Save the host state and record the fact (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM). */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        cpumR0SaveHostFPUState(&pVCpu->cpum.s);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        /* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        pVCpu->cpum.s.fUseFlags |= CPUM_SYNC_FPU_STATE;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    }
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    else
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#endif
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    {
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync# if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) || defined(VBOX_WITH_KERNEL_USING_XMM) /** @todo remove the #else here and move cpumHandleLazyFPUAsm back to VMMGC after branching out 3.0!!. */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE));
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        /** @todo Move the FFXR handling down into
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         *        cpumR0SaveHostRestoreguestFPUState to optimize the
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         *        VBOX_WITH_KERNEL_USING_XMM handling. */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        uint64_t SavedEFER = 0;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        {
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            SavedEFER = ASMRdMsr(MSR_K6_EFER);
8a8d7629deae8875b70c6899e8b0f683b2a543e1vboxsync            if (SavedEFER & MSR_K6_EFER_FFXSR)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            {
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                ASMWrMsr(MSR_K6_EFER, SavedEFER & ~MSR_K6_EFER_FFXSR);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                pVCpu->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            }
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        }
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        /* Do the job and record that we've switched FPU state. */
150e55a1de2d8702b09de9dd08e488cc9da197d9vboxsync        cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
9a12ad9a1028187595f21d9264898220c1ea565fvboxsync
9a12ad9a1028187595f21d9264898220c1ea565fvboxsync        /* Restore EFER. */
9a12ad9a1028187595f21d9264898220c1ea565fvboxsync        if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
9a12ad9a1028187595f21d9264898220c1ea565fvboxsync            ASMWrMsr(MSR_K6_EFER, SavedEFER);
9a12ad9a1028187595f21d9264898220c1ea565fvboxsync
b4feef6ee36ff3c271b06e7e52e22580cc66174bvboxsync# else
9a12ad9a1028187595f21d9264898220c1ea565fvboxsync        uint64_t oldMsrEFERHost = 0;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        uint32_t oldCR0 = ASMGetCR0();
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
9a12ad9a1028187595f21d9264898220c1ea565fvboxsync        /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
8a8d7629deae8875b70c6899e8b0f683b2a543e1vboxsync        if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        {
9a12ad9a1028187595f21d9264898220c1ea565fvboxsync            /** @todo Do we really need to read this every time?? The host could change this on the fly though.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync             *  bird: what about starting by skipping the ASMWrMsr below if we didn't
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync             *        change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            {
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync                pVCpu->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            }
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        }
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        int rc = CPUMHandleLazyFPU(pVCpu);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        AssertRC(rc);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        Assert(CPUMIsGuestFPUStateActive(pVCpu));
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        /* Restore EFER MSR */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        /* CPUMHandleLazyFPU could have changed CR0; restore it. */
f581f3e365dbaec7822752c865314476d86c7e16vboxsync        ASMSetCR0(oldCR0);
8a8d7629deae8875b70c6899e8b0f683b2a543e1vboxsync# endif
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#else  /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        /*
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         * Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         */
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync        pVCpu->cpum.s.Host.fpu.FCW = CPUMGetFCW();
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync        if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync            pVCpu->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync        cpumR0LoadFPU(pCtx);
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync        /*
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync         * The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync         *
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync         * MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync         */
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync        if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync        {
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync            /** @todo Do we really need to read this every time?? The host could change this on the fly though. */
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync            uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync            if (msrEFERHost & MSR_K6_EFER_FFXSR)
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync            {
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync                /* fxrstor doesn't restore the XMM state! */
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync                cpumR0LoadXMM(pCtx);
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync                pVCpu->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync            }
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync        }
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync    }
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync    Assert((pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM)) == (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM));
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync    return VINF_SUCCESS;
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync}
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync
77da7a074c86956d36759983037056c00cb87535vboxsync
77da7a074c86956d36759983037056c00cb87535vboxsync/**
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync * Save guest FPU/XMM state
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync *
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync * @returns VBox status code.
d5b5f09d8841828e647de9da5003fda55ca4cd5evboxsync * @param   pVM         VM handle.
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync * @param   pVCpu       VMCPU handle.
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync * @param   pCtx        CPU context
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync */
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsyncVMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync{
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync    Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync    Assert(ASMGetCR4() & X86_CR4_OSFSXR);
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync    AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync    if (CPUMIsGuestInLongModeEx(pCtx))
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync    {
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync        if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE))
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync        {
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync            HWACCMR0SaveFPUState(pVM, pVCpu, pCtx);
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync            cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync        }
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync        /* else nothing to do; we didn't perform a world switch */
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync    }
2622c26c6b4105d944a29c5e2c77b6ef26e10101vboxsync    else
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#endif
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync    {
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync# ifdef VBOX_WITH_KERNEL_USING_XMM
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        /*
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync         * We've already saved the XMM registers in the assembly wrapper, so
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         * we have to save them before saving the entire FPU state and put them
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         * back afterwards.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        /** @todo This could be skipped if MSR_K6_EFER_FFXSR is set, but
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         *        I'm not able to test such an optimization tonight.
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync         *        We could just all this in assembly. */
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        uint128_t aGuestXmmRegs[16];
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        memcpy(&aGuestXmmRegs[0], &pVCpu->cpum.s.Guest.fpu.aXMM[0], sizeof(aGuestXmmRegs));
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync# endif
d5b5f09d8841828e647de9da5003fda55ca4cd5evboxsync
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync        /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync        uint64_t oldMsrEFERHost = 0;
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync        if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync        {
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync            ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        }
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync        cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
d1a00c93378091ef28db9d959b2d692cc8143a07vboxsync
2e2dec6e64c09dd7e3fe4ad0ee8bb5cf7d63762evboxsync        /* Restore EFER MSR */
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync        if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync            ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost | MSR_K6_EFER_FFXSR);
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync# ifdef VBOX_WITH_KERNEL_USING_XMM
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync        memcpy(&pVCpu->cpum.s.Guest.fpu.aXMM[0], &aGuestXmmRegs[0], sizeof(aGuestXmmRegs));
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync# endif
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync#else  /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync# ifdef VBOX_WITH_KERNEL_USING_XMM
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync#  error "Fix all the NM_TRAPS_IN_KERNEL_MODE code path. I'm not going to fix unused code now."
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync# endif
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync        cpumR0SaveFPU(pCtx);
e2843ed205192b88e54eef60ad541d00bbbc932avboxsync        if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
        {
            /* fxsave doesn't save the XMM state! */
            cpumR0SaveXMM(pCtx);
        }

        /*
         * Restore the original FPU control word and MXCSR.
         * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
         */
        cpumR0SetFCW(pVCpu->cpum.s.Host.fpu.FCW);
        if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
            cpumR0SetMXCSR(pVCpu->cpum.s.Host.fpu.MXCSR);
#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
    }

    pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU | CPUM_SYNC_FPU_STATE | CPUM_MANUAL_XMM_RESTORE);
    return VINF_SUCCESS;
}


/**
 * Save guest debug state
 *
 * @returns VBox status code.
 * @param   pVM         VM handle.
 * @param   pVCpu       VMCPU handle.
 * @param   pCtx        CPU context
 * @param   fDR6        Include DR6 or not
 */
VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
{
    Assert(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS);

    /* Save the guest's debug state. The caller is responsible for DR7. */
#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
    if (CPUMIsGuestInLongModeEx(pCtx))
    {
        if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_STATE))
        {
            uint64_t dr6 = pCtx->dr[6];

            HWACCMR0SaveDebugState(pVM, pVCpu, pCtx);
            if (!fDR6) /* dr6 was already up-to-date */
                pCtx->dr[6] = dr6;
        }
    }
    else
#endif
    {
#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
        cpumR0SaveDRx(&pCtx->dr[0]);
#else
        pCtx->dr[0] = ASMGetDR0();
        pCtx->dr[1] = ASMGetDR1();
        pCtx->dr[2] = ASMGetDR2();
        pCtx->dr[3] = ASMGetDR3();
#endif
        if (fDR6)
            pCtx->dr[6] = ASMGetDR6();
    }

    /*
     * Restore the host's debug state. DR0-3, DR6 and only then DR7!
     * DR7 contains 0x400 right now.
     */
    CPUMR0LoadHostDebugState(pVM, pVCpu);
    Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS));
    return VINF_SUCCESS;
}


/**
 * Lazily sync in the debug state
 *
 * @returns VBox status code.
 * @param   pVM         VM handle.
 * @param   pVCpu       VMCPU handle.
 * @param   pCtx        CPU context
 * @param   fDR6        Include DR6 or not
 */
VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
{
    /* Save the host state. */
    CPUMR0SaveHostDebugState(pVM, pVCpu);
    Assert(ASMGetDR7() == X86_DR7_INIT_VAL);

    /* Activate the guest state DR0-3; DR7 is left to the caller. */
#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
    if (CPUMIsGuestInLongModeEx(pCtx))
    {
        /* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
        pVCpu->cpum.s.fUseFlags |= CPUM_SYNC_DEBUG_STATE;
    }
    else
#endif
    {
#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
        cpumR0LoadDRx(&pCtx->dr[0]);
#else
        ASMSetDR0(pCtx->dr[0]);
        ASMSetDR1(pCtx->dr[1]);
        ASMSetDR2(pCtx->dr[2]);
        ASMSetDR3(pCtx->dr[3]);
#endif
        if (fDR6)
            ASMSetDR6(pCtx->dr[6]);
    }

    pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
    return VINF_SUCCESS;
}

/**
 * Save the host debug state
 *
 * @returns VBox status code.
 * @param   pVM         VM handle.
 * @param   pVCpu       VMCPU handle.
 */
VMMR0DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu)
{
    /* Save the host state. */
#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
    AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
    cpumR0SaveDRx(&pVCpu->cpum.s.Host.dr0);
#else
    pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
    pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
    pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
    pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
#endif
    pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
    /** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
    pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
    /* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
    ASMSetDR7(X86_DR7_INIT_VAL);

    return VINF_SUCCESS;
}

/**
 * Load the host debug state
 *
 * @returns VBox status code.
 * @param   pVM         VM handle.
 * @param   pVCpu       VMCPU handle.
 */
VMMR0DECL(int) CPUMR0LoadHostDebugState(PVM pVM, PVMCPU pVCpu)
{
    Assert(pVCpu->cpum.s.fUseFlags & (CPUM_USE_DEBUG_REGS | CPUM_USE_DEBUG_REGS_HYPER));

    /*
     * Restore the host's debug state. DR0-3, DR6 and only then DR7!
     * DR7 contains 0x400 right now.
     */
#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
    AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
    cpumR0LoadDRx(&pVCpu->cpum.s.Host.dr0);
#else
    ASMSetDR0(pVCpu->cpum.s.Host.dr0);
    ASMSetDR1(pVCpu->cpum.s.Host.dr1);
    ASMSetDR2(pVCpu->cpum.s.Host.dr2);
    ASMSetDR3(pVCpu->cpum.s.Host.dr3);
#endif
    ASMSetDR6(pVCpu->cpum.s.Host.dr6);
    ASMSetDR7(pVCpu->cpum.s.Host.dr7);

    pVCpu->cpum.s.fUseFlags &= ~(CPUM_USE_DEBUG_REGS | CPUM_USE_DEBUG_REGS_HYPER);
    return VINF_SUCCESS;
}


/**
 * Lazily sync in the hypervisor debug state
 *
 * @returns VBox status code.
 * @param   pVM         VM handle.
 * @param   pVCpu       VMCPU handle.
 * @param   pCtx        CPU context
 * @param   fDR6        Include DR6 or not
 */
VMMR0DECL(int) CPUMR0LoadHyperDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
{
    /* Save the host state. */
    CPUMR0SaveHostDebugState(pVM, pVCpu);
    Assert(ASMGetDR7() == X86_DR7_INIT_VAL);

    /* Activate the guest state DR0-3; DR7 is left to the caller. */
#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
    if (CPUMIsGuestInLongModeEx(pCtx))
    {
        AssertFailed();
        return VERR_NOT_IMPLEMENTED;
    }
    else
#endif
    {
#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
        AssertFailed();
        return VERR_NOT_IMPLEMENTED;
#else
        ASMSetDR0(CPUMGetHyperDR0(pVCpu));
        ASMSetDR1(CPUMGetHyperDR1(pVCpu));
        ASMSetDR2(CPUMGetHyperDR2(pVCpu));
        ASMSetDR3(CPUMGetHyperDR3(pVCpu));
#endif
        if (fDR6)
            ASMSetDR6(CPUMGetHyperDR6(pVCpu));
    }

    pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
    return VINF_SUCCESS;
}

#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI

/**
 * Worker for cpumR0MapLocalApics. Check each CPU for a present Local APIC.
 * Play safe and treat each CPU separate.
 */
static void cpumR0MapLocalApicWorker(RTCPUID idCpu, void *pvUser1, void *pvUser2)
{
    int iCpu = RTMpCpuIdToSetIndex(idCpu);
    AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));

    uint32_t u32MaxIdx, u32EBX, u32ECX, u32EDX;
    ASMCpuId(0, &u32MaxIdx, &u32EBX, &u32ECX, &u32EDX);
    if (   (   (   u32EBX == X86_CPUID_VENDOR_INTEL_EBX
                && u32ECX == X86_CPUID_VENDOR_INTEL_ECX
                && u32EDX == X86_CPUID_VENDOR_INTEL_EDX)
           ||  (   u32EBX == X86_CPUID_VENDOR_AMD_EBX
                && u32ECX == X86_CPUID_VENDOR_AMD_ECX
                && u32EDX == X86_CPUID_VENDOR_AMD_EDX))
        && u32MaxIdx >= 1)
    {
        ASMCpuId(1, &u32MaxIdx, &u32EBX, &u32ECX, &u32EDX);
        if (    (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
            &&  (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
        {
            uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
            uint64_t u64Mask     = UINT64_C(0x0000000ffffff000);

            /* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
            uint32_t u32MaxExtIdx;
            ASMCpuId(0x80000000, &u32MaxExtIdx, &u32EBX, &u32ECX, &u32EDX);
            if (   u32MaxExtIdx >= UINT32_C(0x80000008)
                && u32MaxExtIdx <  UINT32_C(0x8000ffff))
            {
                uint32_t u32PhysBits;
                ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
                u32PhysBits &= 0xff;
                u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
            }

            uint64_t const u64PhysBase = u64ApicBase & u64Mask;
            g_aLApics[iCpu].PhysBase   = (RTHCPHYS)u64PhysBase;
            g_aLApics[iCpu].fEnabled   = g_aLApics[iCpu].PhysBase == u64PhysBase;
        }
    }
}


/**
 * Map the MMIO page of each local APIC in the system.
 */
static int cpumR0MapLocalApics(void)
{
    /*
     * Check that we'll always stay within the array bounds.
     */
    if (RTMpGetArraySize() > RT_ELEMENTS(g_aLApics))
    {
        LogRel(("CPUM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aLApics)));
        return VERR_TOO_MANY_CPUS;
    }

    /*
     * Create mappings for all online CPUs we think have APICs.
     */
    /** @todo r=bird: This code is not adequately handling CPUs that are
     *        offline or unplugged at init time and later bought into action. */
    int rc = RTMpOnAll(cpumR0MapLocalApicWorker, NULL, NULL);

    for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
    {
        if (g_aLApics[iCpu].fEnabled)
        {
            rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
                                     PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
            if (RT_SUCCESS(rc))
            {
                rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void *)-1,
                                         PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
                if (RT_SUCCESS(rc))
                {
                    void *pvApicBase = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);

                    /*
                     * 0x0X       82489 external APIC
                     * 0x1X       Local APIC
                     * 0x2X..0xFF reserved
                     */
                    /** @todo r=bird: The local APIC is usually at the same address for all CPUs,
                     *        and therefore inaccessible by the other CPUs. */
                    uint32_t ApicVersion = ApicRegRead(pvApicBase, APIC_REG_VERSION);
                    if ((APIC_REG_VERSION_GET_VER(ApicVersion) & 0xF0) == 0x10)
                    {
                        g_aLApics[iCpu].fHasThermal = APIC_REG_VERSION_GET_MAX_LVT(ApicVersion) >= 5;
                        g_aLApics[iCpu].pv          = pvApicBase;
                        Log(("CPUM: APIC %02u at %RGp (mapped at %p) - ver %#x, lint0=%#x lint1=%#x pc=%#x thmr=%#x\n",
                             iCpu, g_aLApics[iCpu].PhysBase, g_aLApics[iCpu].pv, ApicVersion,
                             ApicRegRead(pvApicBase, APIC_REG_LVT_LINT0),
                             ApicRegRead(pvApicBase, APIC_REG_LVT_LINT1),
                             ApicRegRead(pvApicBase, APIC_REG_LVT_PC),
                             ApicRegRead(pvApicBase, APIC_REG_LVT_THMR)
                             ));
                        continue;
                    }

                    RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
                }
                RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
            }
            g_aLApics[iCpu].fEnabled = false;
        }
    }
    if (RT_FAILURE(rc))
    {
        cpumR0UnmapLocalApics();
        return rc;
    }

    return VINF_SUCCESS;
}


/**
 * Unmap the Local APIC of all host CPUs.
 */
static void cpumR0UnmapLocalApics(void)
{
    for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
    {
        if (g_aLApics[iCpu].pv)
        {
            RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
            RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
            g_aLApics[iCpu].hMapObj  = NIL_RTR0MEMOBJ;
            g_aLApics[iCpu].hMemObj  = NIL_RTR0MEMOBJ;
            g_aLApics[iCpu].fEnabled = false;
            g_aLApics[iCpu].pv       = NULL;
        }
    }
}


/**
 * Write the Local APIC mapping address of the current host CPU to CPUM to be
 * able to access the APIC registers in the raw mode switcher for disabling/
 * re-enabling the NMI. Must be called with disabled preemption or disabled
 * interrupts!
 *
 * @param   pVM         VM handle.
 * @param   idHostCpu   The ID of the current host CPU.
 */
VMMR0DECL(void) CPUMR0SetLApic(PVM pVM, RTCPUID idHostCpu)
{
    pVM->cpum.s.pvApicBase = g_aLApics[RTMpCpuIdToSetIndex(idHostCpu)].pv;
}

#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */