CPUMR0.cpp revision a41a001e5a4dd3f39faab90b412243ced6d59394
/* $Id$ */
/** @file
* CPUM - Host Context Ring 0.
*/
/*
* Copyright (C) 2006-2007 Sun Microsystems, Inc.
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
* Clara, CA 95054 USA or visit http://www.sun.com if you need
* additional information or have any questions.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_CPUM
#include "CPUMInternal.h"
/**
* Does Ring-0 CPUM initialization.
*
* This is mainly to check that the Host CPU mode is compatible
* with VBox.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
/*
* Check CR0 & CR4 flags.
*/
if ((u32CR0 & (X86_CR0_PE | X86_CR0_PG)) != (X86_CR0_PE | X86_CR0_PG)) /* a bit paranoid perhaps.. */
{
return VERR_UNSUPPORTED_CPU_MODE;
}
/*
* Check for sysenter if it's used.
*/
if (ASMHasCpuId())
{
/*
* Intel docs claim you should test both the flag and family, model & stepping.
* Some Pentium Pro cpus have the SEP cpuid flag set, but don't support it.
*/
if ( (u32Features & X86_CPUID_FEATURE_EDX_SEP)
{
/*
* Read the MSR and see if it's in use or not.
*/
if (u32)
{
}
}
/** @todo check for AMD and syscall!!!!!! */
}
/*
* Check if debug registers are armed.
* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
*/
if (u32DR7 & X86_DR7_ENABLED_MASK)
{
}
return VINF_SUCCESS;
}
/**
*
* @returns VBox status code.
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
* @param pCtx CPU context
*/
{
/* If the FPU state has already been loaded, then it's a guest trap. */
{
Assert( ((pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
return VINF_EM_RAW_GUEST_TRAP;
}
/*
* There are two basic actions:
* 1. Save host fpu and restore guest fpu.
* 2. Generate guest trap.
*
* When entering the hypervisor we'll always enable MP (for proper wait
* is taken from the guest OS in order to get proper SSE handling.
*
*
* Actions taken depending on the guest CR0 flags:
*
* 3 2 1
* TS | EM | MP | FPUInstr | WAIT :: VMM Action
* ------------------------------------------------------------------------
* 0 | 0 | 0 | Exec | Exec :: Clear TS & MP, Save HC, Load GC.
* 0 | 0 | 1 | Exec | Exec :: Clear TS, Save HC, Load GC.
* 0 | 1 | 0 | #NM | Exec :: Clear TS & MP, Save HC, Load GC.
* 0 | 1 | 1 | #NM | Exec :: Clear TS, Save HC, Load GC.
* 1 | 0 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
* 1 | 0 | 1 | #NM | #NM :: Go to guest taking trap there.
* 1 | 1 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
* 1 | 1 | 1 | #NM | #NM :: Go to guest taking trap there.
*/
{
case X86_CR0_MP | X86_CR0_TS:
return VINF_EM_RAW_GUEST_TRAP;
default:
break;
}
#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
if (CPUMIsGuestInLongModeEx(pCtx))
{
/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
}
else
#endif
{
uint64_t oldMsrEFERHost = 0;
/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
{
/** @todo Do we really need to read this every time?? The host could change this on the fly though.
* bird: what about starting by skipping the ASMWrMsr below if we didn't
* change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
{
}
}
/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
/* Restore EFER MSR */
/* CPUMHandleLazyFPU could have changed CR0; restore it. */
#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
/*
* Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
*/
/*
* The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
*
* MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
*/
{
/** @todo Do we really need to read this every time?? The host could change this on the fly though. */
if (msrEFERHost & MSR_K6_EFER_FFXSR)
{
/* fxrstor doesn't restore the XMM state! */
}
}
#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
}
return VINF_SUCCESS;
}
/**
*
* @returns VBox status code.
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
* @param pCtx CPU context
*/
{
#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
if (CPUMIsGuestInLongModeEx(pCtx))
{
}
else
#endif
{
uint64_t oldMsrEFERHost = 0;
/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
{
}
/* Restore EFER MSR */
#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
{
/* fxsave doesn't save the XMM state! */
}
/*
* Restore the original FPU control word and MXCSR.
*/
#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
}
return VINF_SUCCESS;
}
/**
* Save guest debug state
*
* @returns VBox status code.
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
* @param pCtx CPU context
* @param fDR6 Include DR6 or not
*/
{
/* Save the guest's debug state. The caller is responsible for DR7. */
#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
if (CPUMIsGuestInLongModeEx(pCtx))
{
{
if (!fDR6) /* dr6 was already up-to-date */
}
}
else
#endif
{
/** @todo @bugref{3202}: Need to wrap these buggers! */
if (fDR6)
}
/*
* Restore the host's debug state. DR0-3, DR6 and only then DR7!
* DR7 contains 0x400 right now.
*/
/** @todo @bugref{3202}: And these! */
return VINF_SUCCESS;
}
/**
* Lazily sync in the debug state
*
* @returns VBox status code.
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
* @param pCtx CPU context
* @param fDR6 Include DR6 or not
*/
{
/* Save the host state. */
/** @todo @bugref{3202}: And these as well! */
/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
/* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
/* Activate the guest state DR0-3; DR7 is left to the caller. */
#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
if (CPUMIsGuestInLongModeEx(pCtx))
{
/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
}
else
#endif
{
/** @todo @bugref{3202}: This too! */
if (fDR6)
}
return VINF_SUCCESS;
}