PGMAllPool.cpp revision 1a5d2d9ef8cf8eeec5649664cf88c7fd55c968d2
/* $Id$ */
/** @file
* PGM Shadow Page Pool.
*/
/*
* Copyright (C) 2006-2010 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_PGM_POOL
#ifdef IN_RC
#endif
#include "PGMInternal.h"
#include "PGMInline.h"
#include <VBox/disopcode.h>
#include <iprt/asm-amd64-x86.h>
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
#ifndef IN_RING3
DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
#endif
#ifdef LOG_ENABLED
#endif
#if 0 /*defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT)*/
static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT);
#endif
/**
* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
*
* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
* @param enmKind The page kind.
*/
{
switch (enmKind)
{
return true;
default:
return false;
}
}
/**
* Flushes a chain of pages sharing the same access monitor.
*
* @returns VBox status code suitable for scheduling.
* @param pPool The pool.
* @param pPage A page in the chain.
* @todo VBOXSTRICTRC
*/
{
/*
* Find the list head.
*/
{
{
}
}
/*
* Iterate the list flushing each shadow page.
*/
int rc = VINF_SUCCESS;
for (;;)
{
{
}
/* next */
if (idx == NIL_PGMPOOL_IDX)
break;
}
return rc;
}
/**
* Wrapper for getting the current context pointer to the entry being modified.
*
* @returns VBox status code suitable for scheduling.
* @param pVM The VM handle.
* @param pvDst Destination address
* @param pvSrc Source guest virtual address.
* @param GCPhysSrc The source guest physical address.
* @param cb Size of data to read
*/
DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc,
{
#if defined(IN_RING3)
return VINF_SUCCESS;
#else
/* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
#endif
}
/**
* Process shadow entries before they are changed by the guest.
*
* For PT entries we will clear them. For PD entries, we'll simply check
* for mapping conflicts and set the SyncCR3 FF if found.
*
* @param pVCpu VMCPU handle
* @param pPool The pool.
* @param pPage The head page.
* @param GCPhysFault The guest physical fault address.
* @param uAddress In R0 and GC this is the guest context fault address (flat).
* In R3 this is the host context 'fault' address.
* @param cbWrite Write size; might be zero if the caller knows we're not crossing entry boundaries
*/
void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault,
{
AssertMsg(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX, ("%u (idx=%u)\n", pPage->iMonitoredPrev, pPage->idx));
LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp cbWrite=%d\n", (RTGCPTR)(CTXTYPE(RTGCPTR, uintptr_t, RTGCPTR))pvAddress, GCPhysFault, cbWrite));
for (;;)
{
union
{
void *pv;
} uShw;
LogFlow(("pgmPoolMonitorChainChanging: page idx=%d phys=%RGp (next=%d) kind=%s\n", pPage->idx, pPage->GCPhys, pPage->iMonitoredNext, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
{
{
{
Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
GstPte.u & X86_PTE_PG_MASK,
iShw);
}
break;
}
/* page/2 sized */
{
{
{
Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
GstPte.u & X86_PTE_PG_MASK,
iShw);
}
}
break;
}
{
LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
{
for (unsigned i = 0; i < 2; i++)
{
# ifndef IN_RING0
if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
{
LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
break;
}
# endif /* !IN_RING0 */
{
LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
iShw + i);
}
/* paranoia / a bit assumptive. */
if ( (off & 3)
{
{
# ifndef IN_RING0
if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
{
LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
break;
}
# endif /* !IN_RING0 */
{
LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
iShw2);
}
}
}
}
}
break;
}
{
{
Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]), GstPte.u & X86_PTE_PAE_PG_MASK));
iShw);
}
/* paranoia / a bit assumptive. */
if ( (off & 7)
{
{
# ifdef IN_RING3
int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
# else
int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
# endif
Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]), GstPte.u & X86_PTE_PAE_PG_MASK));
iShw2);
}
}
break;
}
case PGMPOOLKIND_32BIT_PD:
{
# ifndef IN_RING0
{
break;
}
# endif /* !IN_RING0 */
# ifndef IN_RING0
else
# endif /* !IN_RING0 */
{
{
LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
iShw);
}
}
/* paranoia / a bit assumptive. */
if ( (off & 3)
{
{
# ifndef IN_RING0
{
break;
}
# endif /* !IN_RING0 */
{
LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
iShw2);
}
}
}
#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
{
LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
# ifdef IN_RC /* TLB load - we're pushing things a bit... */
# endif
}
#endif
break;
}
{
#ifndef IN_RING0
{
break;
}
#endif /* !IN_RING0 */
/*
* Causes trouble when the guest uses a PDE to refer to the whole page table level
* structure. (Invalidate here; faults later on when it tries to change the page
* table entries -> recheck; probably only applies to the RC case.)
*/
# ifndef IN_RING0
else
# endif /* !IN_RING0 */
{
{
LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
iShw);
}
}
/* paranoia / a bit assumptive. */
if ( (off & 7)
{
#ifndef IN_RING0
{
break;
}
#endif /* !IN_RING0 */
# ifndef IN_RING0
else
# endif /* !IN_RING0 */
{
LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
iShw2);
}
}
break;
}
case PGMPOOLKIND_PAE_PDPT:
{
/*
* Hopefully this doesn't happen very often:
* - touching unused parts of the page
* - messing with the bits of pd pointers without changing the physical address
*/
/* PDPT roots are not page aligned; 32 byte only! */
if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
{
# ifndef IN_RING0
{
break;
}
# endif /* !IN_RING0 */
# ifndef IN_RING0
else
# endif /* !IN_RING0 */
{
LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
iShw);
}
/* paranoia / a bit assumptive. */
if ( (offPdpt & 7)
{
&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
{
# ifndef IN_RING0
{
break;
}
# endif /* !IN_RING0 */
# ifndef IN_RING0
else
# endif /* !IN_RING0 */
{
LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
iShw2);
}
}
}
}
break;
}
#ifndef IN_RC
{
{
LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
iShw);
}
/* paranoia / a bit assumptive. */
if ( (off & 7)
{
{
LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
iShw2);
}
}
break;
}
{
/*
* Hopefully this doesn't happen very often:
* - messing with the bits of pd pointers without changing the physical address
*/
{
LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
}
/* paranoia / a bit assumptive. */
if ( (off & 7)
{
{
LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
}
}
break;
}
case PGMPOOLKIND_64BIT_PML4:
{
/*
* Hopefully this doesn't happen very often:
* - messing with the bits of pd pointers without changing the physical address
*/
{
LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
}
/* paranoia / a bit assumptive. */
if ( (off & 7)
{
{
LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
}
}
break;
}
#endif /* IN_RING0 */
default:
}
/* next */
return;
}
}
# ifndef IN_RING3
/**
* Checks if a access could be a fork operation in progress.
*
* Meaning, that the guest is setting up the parent process for Copy-On-Write.
*
* @returns true if it's likely that we're forking, otherwise false.
* @param pPool The pool.
* @param pDis The disassembled instruction.
* @param offFault The access offset.
*/
{
/*
* i386 linux is using btr to clear X86_PTE_RW.
* The functions involved are (2.6.16 source inspection):
* clear_bit
* ptep_set_wrprotect
* copy_one_pte
* copy_pte_range
* copy_pmd_range
* copy_pud_range
* copy_page_range
* dup_mmap
* dup_mm
* copy_mm
* copy_process
* do_fork
*/
&& !(offFault & 4)
/** @todo Validate that the bit index is X86_PTE_RW. */
)
{
return true;
}
return false;
}
/**
* Determine whether the page is likely to have been reused.
*
* @returns true if we consider the page as being reused for a different purpose.
* @returns false if we consider it to still be a paging page.
* @param pVM The VM handle.
* @param pVCpu VMCPU Handle.
* @param pRegFrame Trap register frame.
* @param pDis The disassembly info for the faulting instruction.
* @param pvFault The fault address.
*
* @remark The REP prefix check is left to the caller because of STOSD/W.
*/
DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault)
{
#ifndef IN_RC
/** @todo could make this general, faulting close to rsp should be a safe reuse heuristic. */
if ( HWACCMHasPendingIrq(pVM)
{
/* Fault caused by stack writes while trying to inject an interrupt event. */
Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
return true;
}
#else
#endif
LogFlow(("Reused instr %RGv %d at %RGv param1.fUse=%llx param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->uOpcode, pvFault, pDis->Param1.fUse, pDis->Param1.Base.idxGenReg));
/* Non-supervisor mode write means it's used for something else. */
return true;
{
/* call implies the actual push of the return address faulted */
case OP_CALL:
Log4(("pgmPoolMonitorIsReused: CALL\n"));
return true;
case OP_PUSH:
Log4(("pgmPoolMonitorIsReused: PUSH\n"));
return true;
case OP_PUSHF:
Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
return true;
case OP_PUSHA:
Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
return true;
case OP_FXSAVE:
Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
return true;
case OP_MOVNTI: /* solaris - block_zero_no_xmm */
Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
return true;
case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
return true;
case OP_MOVSWD:
case OP_STOSWD:
)
{
Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
return true;
}
return false;
}
{
Log4(("pgmPoolMonitorIsReused: ESP\n"));
return true;
}
return false;
}
/**
* Flushes the page being accessed.
*
* @returns VBox status code suitable for scheduling.
* @param pVM The VM handle.
* @param pVCpu The VMCPU handle.
* @param pPool The pool.
* @param pPage The pool page (head).
* @param pDis The disassembly of the write instruction.
* @param pRegFrame The trap register frame.
* @param GCPhysFault The fault address as guest physical address.
* @param pvFault The fault address.
* @todo VBOXSTRICTRC
*/
static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
{
/*
* First, do the flushing.
*/
/*
* Must do this in raw mode (!); XP boot will fail otherwise.
*/
VBOXSTRICTRC rc2 = EMInterpretInstructionDisasState(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL);
if (RT_SUCCESS(rc2))
AssertMsg(rc2 == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rc2))); /* ASSUMES no complicated stuff here. */
else if (rc2 == VERR_EM_INTERPRETER)
{
#ifdef IN_RC
{
LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
rc = VINF_SUCCESS;
}
else
#endif
{
}
}
else
return rc;
}
/**
* Handles the STOSD write accesses.
*
* @returns VBox status code suitable for scheduling.
* @param pVM The VM handle.
* @param pPool The pool.
* @param pPage The pool page (head).
* @param pDis The disassembly of the write instruction.
* @param pRegFrame The trap register frame.
* @param GCPhysFault The fault address as guest physical address.
* @param pvFault The fault address.
*/
DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
{
#ifdef VBOX_STRICT
else
#endif
Log3(("pgmPoolAccessHandlerSTOSD\n"));
/*
* Increment the modification counter and insert it into the list
* of modified pages the first time.
*/
if (!pPage->cModifications++)
/*
* Execute REP STOSD.
*
* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
* write situation, meaning that it's safe to write here.
*/
{
#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
#else
#endif
#ifdef IN_RC
#else
#endif
pu32 += uIncrement;
}
LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
return VINF_SUCCESS;
}
/**
* Handles the simple write accesses.
*
* @returns VBox status code suitable for scheduling.
* @param pVM The VM handle.
* @param pVCpu The VMCPU handle.
* @param pPool The pool.
* @param pPage The pool page (head).
* @param pDis The disassembly of the write instruction.
* @param pRegFrame The trap register frame.
* @param GCPhysFault The fault address as guest physical address.
* @param pvFault The fault address.
*/
DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
{
Log3(("pgmPoolAccessHandlerSimple\n"));
/*
* Increment the modification counter and insert it into the list
* of modified pages the first time.
*/
if (!pPage->cModifications++)
/*
* Clear all the pages. ASSUMES that pvFault is readable.
*/
#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, DISGetParamSize(pDis, &pDis->Param1));
#else
pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, DISGetParamSize(pDis, &pDis->Param1));
#endif
/*
* Interpret the instruction.
*/
VBOXSTRICTRC rc = EMInterpretInstructionDisasState(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL);
if (RT_SUCCESS(rc))
AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rc))); /* ASSUMES no complicated stuff here. */
else if (rc == VERR_EM_INTERPRETER)
{
LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
}
#if 0 /* experimental code */
if (rc == VINF_SUCCESS)
{
{
{
/* Check the new value written by the guest. If present and with a bogus physical address, then
* it's fairly safe to assume the guest is reusing the PT.
*/
{
if (rc != VINF_SUCCESS)
{
*pfReused = true;
}
}
break;
}
}
}
#endif
return VBOXSTRICTRC_VAL(rc);
}
/**
* \#PF Handler callback for PT write accesses.
*
* @returns VBox status code (appropriate for GC return).
* @param pVM The VM handle.
* @param uErrorCode CPU Error code.
* @param pRegFrame Trap register frame.
* NULL on DMA and other non CPU access.
* @param pvFault The fault address (cr2).
* @param GCPhysFault The GC physical address corresponding to pvFault.
* @param pvUser User argument.
*/
DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
{
unsigned cMaxModifications;
bool fForcedFlush = false;
LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
{
/* Pool page changed while we were waiting for the lock; ignore. */
Log(("CPU%d: pgmPoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
return VINF_SUCCESS;
}
{
return VINF_SUCCESS; /* SMP guest case where we were blocking on the pgm lock while the same page was being marked dirty. */
}
#endif
#if 0 /* test code defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) */
{
void *pvGst;
}
#endif
/*
* Disassemble the faulting instruction.
*/
{
AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("Unexpected rc %d\n", rc));
return rc;
}
/*
* We should ALWAYS have the list head as user parameter. This
* is because we use that page to record the changes.
*/
#ifdef IN_RING0
/* Maximum nr of modifications depends on the page type. */
cMaxModifications = 4;
else
cMaxModifications = 24;
#else
cMaxModifications = 48;
#endif
/*
* Incremental page table updates should weigh more than random ones.
* (Only applies when started from offset 0)
*/
if ( pPage->GCPtrLastAccessHandlerRip >= pRegFrame->rip - 0x40 /* observed loops in Windows 7 x64 */
{
Log(("Possible page reuse cMods=%d -> %d (locked=%d type=%s)\n", pPage->cModifications, pPage->cModifications * 2, pgmPoolIsPageLocked(pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
{
fForcedFlush = true;
}
}
Log(("Mod overflow %RGv cMods=%d (locked=%d type=%s)\n", pvFault, pPage->cModifications, pgmPoolIsPageLocked(pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
/*
* Check if it's worth dealing with.
*/
bool fReused = false;
bool fNotReusedNotForking = false;
if ( ( pPage->cModifications < cMaxModifications /** @todo #define */ /** @todo need to check that it's not mapping EIP. */ /** @todo adjust this! */
)
{
/*
* Simple instructions, no REP prefix.
*/
{
rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused);
if (fReused)
goto flushPage;
/* A mov instruction to change the first page table entry will be remembered so we can detect
* full page table changes early on. This will reduce the amount of unnecessary traps we'll take.
*/
if ( rc == VINF_SUCCESS
&& !pPage->cLocked /* only applies to unlocked pages as we can't free locked ones (e.g. cr3 root). */
&& (pvFault & PAGE_OFFSET_MASK) == 0)
{
/* Make sure we don't kick out a page too quickly. */
}
{
/* ignore the 2nd write to this page table entry. */
}
else
{
}
STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
return rc;
}
/*
* Windows is frequently doing small memset() operations (netio test 4k+).
* We have to deal with these or we'll kill the cache and performance.
*/
{
bool fValidStosd = false;
)
{
fValidStosd = true;
}
else
)
{
fValidStosd = true;
}
if (fValidStosd)
{
STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
return rc;
}
}
/* REP prefix, don't bother. */
Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->uOpcode, pDis->fPrefix));
fNotReusedNotForking = true;
}
#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) && defined(IN_RING0)
/* E.g. Windows 7 x64 initializes page tables and touches some pages in the table during the process. This
* leads to pgm pool trashing and an excessive amount of write faults due to page monitoring.
*/
&& !fForcedFlush
&& (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT || pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_32BIT_PT)
&& ( fNotReusedNotForking
)
)
{
/* Flush any monitored duplicates as we will disable write protection. */
{
/* Find the monitor head. */
while (pPageHead)
{
{
Log(("Flush duplicate page idx=%d GCPhys=%RGp type=%s\n", pPageHead->idx, pPageHead->GCPhys, pgmPoolPoolKindToStr(pPageHead->enmKind)));
}
if (idxNext == NIL_PGMPOOL_IDX)
break;
}
}
/* The flushing above might fail for locked pages, so double check. */
{
/* Temporarily allow write access to the page table again. */
rc = PGMHandlerPhysicalPageTempOff(pVM, pPage->GCPhys & PAGE_BASE_GC_MASK, pPage->GCPhys & PAGE_BASE_GC_MASK);
if (rc == VINF_SUCCESS)
{
/* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
|| rc == VERR_PAGE_NOT_PRESENT,
# ifdef VBOX_STRICT
# endif
return rc;
}
}
}
#endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
/*
* Not worth it, so flush it.
*
* If we considered it to be reused, don't go back to ring-3
* to emulate failed instructions since we usually cannot
* interpret then. This may be a bit risky, in which case
* the reuse detection must be fixed.
*/
if ( rc == VINF_EM_RAW_EMULATE_INSTR
&& fReused)
{
/* Make sure that the current instruction still has shadow page backing, otherwise we'll end up in a loop. */
}
STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
return rc;
}
# endif /* !IN_RING3 */
# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
# if defined(VBOX_STRICT) && !defined(IN_RING3)
/**
* Check references to guest physical memory in a PAE / PAE page table.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPT The shadow page table (mapping of the page).
* @param pGstPT The guest page table.
*/
static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT)
{
unsigned cErrors = 0;
unsigned LastPTE = ~0U; /* initialized to shut up gcc */
#ifdef VBOX_STRICT
AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
#endif
{
if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
{
if ( rc != VINF_SUCCESS
{
Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
LastPTE = i;
LastHCPhys = HCPhys;
cErrors++;
{
{
for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
{
if ( PGMSHWPTEPAE_IS_P_RW(pShwPT2->a[j])
{
Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), PGMSHWPTEPAE_GET_LOG(pShwPT2->a[j])));
}
}
}
}
}
}
}
AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[LastPTE]), LastHCPhys));
}
/**
* Check references to guest physical memory in a PAE / 32-bit page table.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPT The shadow page table (mapping of the page).
* @param pGstPT The guest page table.
*/
static void pgmPoolTrackCheckPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT)
{
unsigned cErrors = 0;
unsigned LastPTE = ~0U; /* initialized to shut up gcc */
#ifdef VBOX_STRICT
AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
#endif
{
if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
{
if ( rc != VINF_SUCCESS
{
Log(("rc=%d idx=%d guest %x shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
LastPTE = i;
LastHCPhys = HCPhys;
cErrors++;
{
{
for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
{
if ( PGMSHWPTEPAE_IS_P_RW(pShwPT2->a[j])
{
Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), PGMSHWPTEPAE_GET_LOG(pShwPT2->a[j])));
}
}
}
}
}
}
}
AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %x shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[LastPTE]), LastHCPhys));
}
# endif /* VBOX_STRICT && !IN_RING3 */
/**
* Clear references to guest physical memory in a PAE / PAE page table.
*
* @returns nr of changed PTEs
* @param pPool The pool.
* @param pPage The page.
* @param pShwPT The shadow page table (mapping of the page).
* @param pGstPT The guest page table.
* @param pOldGstPT The old cached guest page table.
* @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
* @param pfFlush Flush reused page table (out)
*/
DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT,
{
unsigned cChanged = 0;
#ifdef VBOX_STRICT
AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
#endif
*pfFlush = false;
{
/* Check the new value written by the guest. If present and with a bogus physical address, then
* it's fairly safe to assume the guest is reusing the PT.
*/
if ( fAllowRemoval
{
{
*pfFlush = true;
return ++cChanged;
}
}
if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
{
/* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
{
#ifdef VBOX_STRICT
AssertMsg(rc == VINF_SUCCESS && PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
#endif
uint64_t uHostAttr = PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
if ( uHostAttr == uGuestAttr
continue;
}
cChanged++;
/* Something was changed, so flush it. */
Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
PGMSHWPTEPAE_ATOMIC_SET(pShwPT->a[i], 0);
}
}
return cChanged;
}
/**
* Clear references to guest physical memory in a PAE / PAE page table.
*
* @returns nr of changed PTEs
* @param pPool The pool.
* @param pPage The page.
* @param pShwPT The shadow page table (mapping of the page).
* @param pGstPT The guest page table.
* @param pOldGstPT The old cached guest page table.
* @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
* @param pfFlush Flush reused page table (out)
*/
DECLINLINE(unsigned) pgmPoolTrackFlushPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT,
{
unsigned cChanged = 0;
#ifdef VBOX_STRICT
AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
#endif
*pfFlush = false;
{
/* Check the new value written by the guest. If present and with a bogus physical address, then
* it's fairly safe to assume the guest is reusing the PT.
*/
if ( fAllowRemoval
{
{
*pfFlush = true;
return ++cChanged;
}
}
if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
{
/* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
{
#ifdef VBOX_STRICT
AssertMsg(rc == VINF_SUCCESS && PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) == HCPhys, ("rc=%d guest %x old %x shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
#endif
uint64_t uHostAttr = PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G);
uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G);
if ( uHostAttr == uGuestAttr
continue;
}
cChanged++;
/* Something was changed, so flush it. */
Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%x\n",
pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PG_MASK, i);
PGMSHWPTEPAE_ATOMIC_SET(pShwPT->a[i], 0);
}
}
return cChanged;
}
/**
* Flush a dirty page
*
* @param pVM The VM handle.
* @param pPool The pool.
* @param idxSlot Dirty array slot index
* @param fAllowRemoval Allow a reused page table to be removed
*/
static void pgmPoolFlushDirtyPage(PVM pVM, PPGMPOOL pPool, unsigned idxSlot, bool fAllowRemoval = false)
{
unsigned idxPage;
return;
#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
#endif
/* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */
#ifdef VBOX_STRICT
/* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
|| rc == VERR_PAGE_NOT_PRESENT,
#endif
/* Flush those PTEs that have changed. */
void *pvGst;
bool fFlush;
unsigned cChanges;
else
/* Note: we might want to consider keeping the dirty page active in case there were many changes. */
/* This page is likely to be modified again, so reduce the nr of modifications just a bit here. */
if (cChanges < 4)
else
pPool->cDirtyPages--;
if (fFlush)
{
Log(("Flush reused page table!\n"));
}
else
Log(("Removed dirty page %RGp cMods=%d cChanges=%d\n", pPage->GCPhys, pPage->cModifications, cChanges));
#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
#endif
}
# ifndef IN_RING3
/**
* Add a new dirty page
*
* @param pVM The VM handle.
* @param pPool The pool.
* @param pPage The page.
*/
{
unsigned idxFree;
{
}
AssertMsg(pPool->aDirtyPages[idxFree].uIdx == NIL_PGMPOOL_IDX, ("idxFree=%d cDirtyPages=%d\n", idxFree, pPool->cDirtyPages));
/*
* Make a copy of the guest page table as we require valid GCPhys addresses
* when removing references to physical pages.
* (The HCPhys linear lookup is *extremely* expensive!)
*/
void *pvGst;
memcpy(&pPool->aDirtyPages[idxFree].aPage[0], pvGst, (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT) ? PAGE_SIZE : PAGE_SIZE/2);
# ifdef VBOX_STRICT
else
# endif
pPool->cDirtyPages++;
{
unsigned i;
{
{
break;
}
}
}
Assert(pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages) || pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx == NIL_PGMPOOL_IDX);
return;
}
# endif /* !IN_RING3 */
/**
* Check if the specified page is dirty (not write monitored)
*
* @return dirty or not
* @param pVM The VM handle.
* @param GCPhys Guest physical address
*/
{
if (!pPool->cDirtyPages)
return false;
{
{
return true;
}
}
return false;
}
/**
* Reset all dirty pages by reinstating page monitoring.
*
* @param pVM The VM handle.
*/
{
if (!pPool->cDirtyPages)
return;
Log(("pgmPoolResetDirtyPages\n"));
pPool->idxFreeDirtyPage = 0;
{
unsigned i;
{
{
pPool->idxFreeDirtyPage = i;
break;
}
}
}
Assert(pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx == NIL_PGMPOOL_IDX || pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages));
return;
}
/**
* Invalidate the PT entry for the specified page
*
* @param pVM The VM handle.
* @param GCPtrPage Guest page to invalidate
*/
{
if (!pPool->cDirtyPages)
return;
{
}
}
/**
* Reset all dirty pages by reinstating page monitoring.
*
* @param pVM The VM handle.
* @param GCPhysPT Physical address of the page table
*/
{
if (!pPool->cDirtyPages)
return;
{
{
{
idxDirtyPage = i;
break;
}
}
}
{
{
unsigned i;
{
{
pPool->idxFreeDirtyPage = i;
break;
}
}
}
}
}
# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
/**
* Inserts a page into the GCPhys hash table.
*
* @param pPool The pool.
* @param pPage The page.
*/
{
}
/**
* Removes a page from the GCPhys hash table.
*
* @param pPool The pool.
* @param pPage The page.
*/
{
else
{
for (;;)
{
{
break;
}
if (i == NIL_PGMPOOL_IDX)
{
break;
}
iPrev = i;
}
}
}
/**
* Frees up one cache page.
*
* @returns VBox status code.
* @retval VINF_SUCCESS on success.
* @param pPool The pool.
* @param iUser The user index.
*/
{
#ifndef IN_RC
#endif
/*
* Select one page from the tail of the age list.
*/
{
/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
{
uint16_t i = pPool->aPages[iToFree].iAgePrev;
for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
{
if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
continue;
iToFree = i;
break;
}
}
*/
/*
* Reject any attempts at flushing the currently active shadow CR3 mapping.
* Call pgmPoolCacheUsed to move the page to the head of the age list.
*/
if (!pgmPoolIsPageLocked(pPage))
break;
LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
}
/*
* Found a usable page, flush it and return.
*/
/* This flush was initiated by us and not the guest, so explicitly flush the TLB. */
/* todo: find out why this is necessary; pgmPoolFlushPage should trigger a flush if one is really needed. */
if (rc == VINF_SUCCESS)
return rc;
}
/**
* Checks if a kind mismatch is really a page being reused
* or if it's just normal remappings.
*
* @returns true if reused and the cached page (enmKind1) should be flushed
* @returns false if not reused.
* @param enmKind1 The kind of the cached page.
* @param enmKind2 The kind of the requested page.
*/
{
switch (enmKind1)
{
/*
* Never reuse them. There is no remapping in non-paging mode.
*/
case PGMPOOLKIND_PAE_PD_PHYS:
case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
return false;
/*
* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
*/
case PGMPOOLKIND_32BIT_PD:
case PGMPOOLKIND_PAE_PDPT:
switch (enmKind2)
{
case PGMPOOLKIND_64BIT_PML4:
return true;
default:
return false;
}
/*
* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
*/
case PGMPOOLKIND_64BIT_PML4:
switch (enmKind2)
{
return true;
default:
return false;
}
/*
* These cannot be flushed, and it's common to reuse the PDs as PTs.
*/
case PGMPOOLKIND_ROOT_NESTED:
return false;
default:
}
}
/**
* Attempts to satisfy a pgmPoolAlloc request from the cache.
*
* @returns VBox status code.
* @retval VINF_PGM_CACHED_PAGE on success.
* @retval VERR_FILE_NOT_FOUND if not found.
* @param pPool The pool.
* @param GCPhys The GC physical address of the page we're gonna shadow.
* @param enmKind The kind of mapping.
* @param enmAccess Access type for the mapping (only relevant for big pages)
* @param fA20Enabled Whether the CPU has the A20 gate enabled.
* @param iUser The shadow page pool index of the user table.
* @param iUserTable The index into the user table (shadowed).
* @param ppPage Where to store the pointer to the page.
*/
static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
{
/*
* Look up the GCPhys in the hash.
*/
Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%d iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
if (i != NIL_PGMPOOL_IDX)
{
do
{
{
{
/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
* doesn't flush it in case there are no more free use records.
*/
if (RT_SUCCESS(rc))
{
if (pPage->cModifications)
pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
return VINF_PGM_CACHED_PAGE;
}
return rc;
}
{
/*
* The kind is different. In some cases we should now flush the page
* as it has been reused, but in most cases this is normal remapping
* of PDs as PT or big pages using the GCPhys field in a slightly
* different way than the other kinds.
*/
{
break;
}
}
}
/* next */
} while (i != NIL_PGMPOOL_IDX);
}
Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
return VERR_FILE_NOT_FOUND;
}
/**
* Inserts a page into the cache.
*
* @param pPool The pool.
* @param pPage The cached page.
* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
*/
{
/*
* Insert into the GCPhys hash if the page is fit for that.
*/
if (fCanBeCached)
{
Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
}
else
{
Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
}
/*
* Insert at the head of the age list.
*/
else
}
/**
* Flushes a cached page.
*
* @param pPool The pool.
* @param pPage The cached page.
*/
{
/*
* Remove the page from the hash.
*/
{
}
else
/*
* Remove it from the age list.
*/
else
else
}
/**
* Looks for pages sharing the monitor.
*
* @returns Pointer to the head page.
* @returns NULL if not found.
* @param pPool The Pool
* @param pNewPage The page which is going to be monitored.
*/
{
/*
* Look up the GCPhys in the hash.
*/
if (i == NIL_PGMPOOL_IDX)
return NULL;
do
{
{
{
case PGMPOOLKIND_64BIT_PML4:
case PGMPOOLKIND_32BIT_PD:
case PGMPOOLKIND_PAE_PDPT:
{
/* find the head */
{
}
return pPage;
}
/* ignore, no monitoring. */
case PGMPOOLKIND_ROOT_NESTED:
case PGMPOOLKIND_PAE_PD_PHYS:
break;
default:
}
}
/* next */
} while (i != NIL_PGMPOOL_IDX);
return NULL;
}
/**
* Enabled write monitoring of a guest page.
*
* @returns VBox status code.
* @retval VINF_SUCCESS on success.
* @param pPool The pool.
* @param pPage The cached page.
*/
{
/*
* Filter out the relevant kinds.
*/
{
case PGMPOOLKIND_64BIT_PML4:
case PGMPOOLKIND_32BIT_PD:
case PGMPOOLKIND_PAE_PDPT:
break;
case PGMPOOLKIND_ROOT_NESTED:
/* Nothing to monitor here. */
return VINF_SUCCESS;
case PGMPOOLKIND_PAE_PD_PHYS:
/* Nothing to monitor here. */
return VINF_SUCCESS;
default:
}
/*
* Install handler.
*/
int rc;
if (pPageHead)
{
pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPageHead->idxDirtyEntry, false /* do not remove */);
#endif
rc = VINF_SUCCESS;
}
else
{
/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
* the heap size should suffice. */
AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), ("fSyncFlags=%x syncff=%d\n", pVCpu->pgm.s.fSyncFlags, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
}
pPage->fMonitored = true;
return rc;
}
/**
* Disables write monitoring of a guest page.
*
* @returns VBox status code.
* @retval VINF_SUCCESS on success.
* @param pPool The pool.
* @param pPage The cached page.
*/
{
/*
* Filter out the relevant kinds.
*/
{
case PGMPOOLKIND_64BIT_PML4:
case PGMPOOLKIND_32BIT_PD:
case PGMPOOLKIND_PAE_PDPT:
break;
case PGMPOOLKIND_ROOT_NESTED:
case PGMPOOLKIND_PAE_PD_PHYS:
/* Nothing to monitor here. */
return VINF_SUCCESS;
default:
}
/*
* Remove the page from the monitored list or uninstall it if last.
*/
int rc;
{
{
}
else
{
{
}
rc = VINF_SUCCESS;
}
}
else
{
AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3),
}
pPage->fMonitored = false;
/*
* Remove it from the list of modified pages (if in it).
*/
return rc;
}
/**
* Inserts the page into the list of modified pages.
*
* @param pPool The pool.
* @param pPage The page.
*/
{
("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
pPool->cModifiedPages++;
#ifdef VBOX_WITH_STATISTICS
#endif
}
/**
* Removes the page from the list of modified pages and resets the
* modification counter.
*
* @param pPool The pool.
* @param pPage The page which is believed to be in the list of modified pages.
*/
{
Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
{
{
}
pPool->cModifiedPages--;
}
{
{
}
pPool->cModifiedPages--;
}
else
pPage->cModifications = 0;
}
/**
* Zaps the list of modified pages, resetting their modification counters in the process.
*
* @param pVM The VM handle.
*/
{
#endif
while (idx != NIL_PGMPOOL_IDX)
{
pPage->cModifications = 0;
}
pPool->cModifiedPages = 0;
}
/**
* Handle SyncCR3 pool tasks
*
* @returns VBox status code.
* @retval VINF_SUCCESS if successfully added.
* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
* @param pVCpu The VMCPU handle.
* @remark Should only be used when monitoring is available, thus placed in
* the PGMPOOL_WITH_MONITORING #ifdef.
*/
{
/*
* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
* Occasionally we will have to clear all the shadow page tables because we wanted
* to monitor a page which was mapped by too many shadowed page tables. This operation
* sometimes referred to as a 'lightweight flush'.
*/
# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
# else /* !IN_RING3 */
{
Log(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
/* Make sure all other VCPUs return to ring 3. */
{
}
return VINF_PGM_SYNC_CR3;
}
# endif /* !IN_RING3 */
else
{
/* pgmPoolMonitorModifiedClearAll can cause a pgm pool flush (dirty page clearing), so make sure we handle this! */
{
Log(("pgmPoolMonitorModifiedClearAll caused a pgm flush -> call pgmPoolSyncCR3 again!\n"));
return pgmPoolSyncCR3(pVCpu);
}
}
return VINF_SUCCESS;
}
/**
* Frees up at least one user entry.
*
* @returns VBox status code.
* @retval VINF_SUCCESS if successfully added.
* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
* @param pPool The pool.
* @param iUser The user index.
*/
{
/*
* Just free cached pages in a braindead fashion.
*/
/** @todo walk the age list backwards and free the first with usage. */
int rc = VINF_SUCCESS;
do
{
return rc;
}
/**
* Inserts a page into the cache.
*
* This will create user node for the page, insert it into the GCPhys
* hash, and insert it into the age list.
*
* @returns VBox status code.
* @retval VINF_SUCCESS if successfully added.
* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
* @param pPool The pool.
* @param pPage The cached page.
* @param GCPhys The GC physical address of the page we're gonna shadow.
* @param iUser The user index.
* @param iUserTable The user table index.
*/
DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
{
int rc = VINF_SUCCESS;
#ifdef VBOX_STRICT
/*
* Check that the entry doesn't already exists.
*/
{
do
{
AssertMsg(paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
} while (i != NIL_PGMPOOL_USER_INDEX);
}
#endif
/*
* Find free a user node.
*/
if (i == NIL_PGMPOOL_USER_INDEX)
{
if (RT_FAILURE(rc))
return rc;
i = pPool->iUserFreeHead;
}
/*
* Unlink the user node from the free list,
* initialize and insert it into the user list.
*/
/*
* Insert into cache and enable monitoring of the guest page if enabled.
*
* Until we implement caching of all levels, including the CR3 one, we'll
* have to make sure we don't try monitor & cache any recursive reuse of
* a monitored CR3 page. Because all windows versions are doing this we'll
* have to be able to do combined access monitoring, CR3 + PT and
* PD + PT (guest PAE).
*
* Update:
* We're now cooperating with the CR3 monitor if an uncachable page is found.
*/
const bool fCanBeMonitored = true;
if (fCanBeMonitored)
{
}
return rc;
}
/**
* Adds a user reference to a page.
*
* This will move the page to the head of the
*
* @returns VBox status code.
* @retval VINF_SUCCESS if successfully added.
* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
* @param pPool The pool.
* @param pPage The cached page.
* @param iUser The user index.
* @param iUserTable The user table.
*/
static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
{
Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
# ifdef VBOX_STRICT
/*
* Check that the entry doesn't already exists. We only allow multiple
* users of top-level paging structures (SHW_POOL_ROOT_IDX).
*/
{
do
{
AssertMsg(iUser != PGMPOOL_IDX_PD || iUser != PGMPOOL_IDX_PDPT || iUser != PGMPOOL_IDX_NESTED_ROOT || iUser != PGMPOOL_IDX_AMD64_CR3 ||
paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
} while (i != NIL_PGMPOOL_USER_INDEX);
}
# endif
/*
* Allocate a user node.
*/
if (i == NIL_PGMPOOL_USER_INDEX)
{
if (RT_FAILURE(rc))
return rc;
i = pPool->iUserFreeHead;
}
/*
* Initialize the user node and insert it.
*/
# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPage->idxDirtyEntry, false /* do not remove */);
# endif
/*
* Tell the cache to update its replacement stats for this page.
*/
return VINF_SUCCESS;
}
/**
* Frees a user record associated with a page.
*
* This does not clear the entry in the user table, it simply replaces the
* user record to the chain of free records.
*
* @param pPool The pool.
* @param HCPhys The HC physical address of the shadow page.
* @param iUser The shadow page pool index of the user table.
* @param iUserTable The index into the user table (shadowed).
*/
static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
{
/*
* Unlink and free the specified user entry.
*/
/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
if ( i != NIL_PGMPOOL_USER_INDEX
{
pPool->iUserFreeHead = i;
return;
}
/* General: Linear search. */
while (i != NIL_PGMPOOL_USER_INDEX)
{
{
if (iPrev != NIL_PGMPOOL_USER_INDEX)
else
pPool->iUserFreeHead = i;
return;
}
iPrev = i;
}
/* Fatal: didn't find it */
AssertFatalMsgFailed(("Didn't find the user entry! iUser=%d iUserTable=%#x GCPhys=%RGp\n",
}
/**
* Gets the entry size of a shadow table.
*
* @param enmKind The kind of page.
*
* @returns The size of the entry in bytes. That is, 4 or 8.
* @returns If the kind is not for a table, an assertion is raised and 0 is
* returned.
*/
{
switch (enmKind)
{
case PGMPOOLKIND_32BIT_PD:
return 4;
case PGMPOOLKIND_64BIT_PML4:
case PGMPOOLKIND_PAE_PDPT:
case PGMPOOLKIND_ROOT_NESTED:
case PGMPOOLKIND_PAE_PD_PHYS:
return 8;
default:
}
}
/**
* Gets the entry size of a guest table.
*
* @param enmKind The kind of page.
*
* @returns The size of the entry in bytes. That is, 0, 4 or 8.
* @returns If the kind is not for a table, an assertion is raised and 0 is
* returned.
*/
{
switch (enmKind)
{
case PGMPOOLKIND_32BIT_PD:
return 4;
case PGMPOOLKIND_64BIT_PML4:
case PGMPOOLKIND_PAE_PDPT:
return 8;
case PGMPOOLKIND_ROOT_NESTED:
case PGMPOOLKIND_PAE_PD_PHYS:
/** @todo can we return 0? (nobody is calling this...) */
AssertFailed();
return 0;
default:
}
}
/**
* Checks one shadow page table entry for a mapping of a physical page.
*
* @returns true / false indicating removal of all relevant PTEs
*
* @param pVM The VM handle.
* @param pPhysPage The guest page in question.
* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
* @param iShw The shadow page table.
* @param iPte Page table entry or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown
*/
static bool pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t iPte)
{
LogFlow(("pgmPoolTrackFlushGCPhysPTInt: pPhysPage=%RHp iShw=%d iPte=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, iPte));
bool fRet = false;
/*
* Assert sanity.
*/
/*
* Then, clear the actual mappings to the page in the shadow PT.
*/
{
{
uint32_t u32AndMask = 0;
if (!fFlushPTEs)
{
switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
{
case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
fRet = true;
break;
case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
u32OrMask = 0;
u32AndMask = ~X86_PTE_RW;
fRet = true;
break;
default:
/* (shouldn't be here, will assert below) */
break;
}
}
else
/* Update the counter if we're removing references. */
if (!u32AndMask)
{
}
{
if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
return fRet;
}
#ifdef LOG_ENABLED
{
}
#endif
AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d u32=%RX32 poolkind=%x\n", pPage->iFirstPresent, pPage->cPresent, u32, pPage->enmKind));
/*PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);*/
break;
}
case PGMPOOLKIND_EPT_PT_FOR_PHYS: /* physical mask the same as PAE; RW bit as well; be careful! */
{
uint64_t u64AndMask = 0;
if (!fFlushPTEs)
{
switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
{
case PGM_PAGE_HNDL_PHYS_STATE_NONE: /* No handler installed. */
case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /* Monitoring is temporarily disabled. */
fRet = true;
break;
case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /* Write access is monitored. */
u64OrMask = 0;
fRet = true;
break;
default:
/* (shouldn't be here, will assert below) */
break;
}
}
else
/* Update the counter if we're removing references. */
if (!u64AndMask)
{
}
if ((PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64)
{
if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
return fRet;
}
#ifdef LOG_ENABLED
Log(("Found %RX64 expected %RX64\n", PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX), u64));
if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64)
#endif
AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d u64=%RX64 poolkind=%x iPte=%d PT=%RX64\n", pPage->iFirstPresent, pPage->cPresent, u64, pPage->enmKind, iPte, PGMSHWPTEPAE_GET_LOG(pPT->a[iPte])));
/*PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);*/
break;
}
#ifdef PGM_WITH_LARGE_PAGES
/* Large page case only. */
{
{
/* Update the counter as we're removing references. */
return fRet;
}
# ifdef LOG_ENABLED
# endif
/*PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);*/
break;
}
/* AMD-V nested paging */ /** @todo merge with EPT as we only check the parts that are identical. */
case PGMPOOLKIND_PAE_PD_PHYS:
{
{
/* Update the counter as we're removing references. */
return fRet;
}
# ifdef LOG_ENABLED
# endif
/*PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);*/
break;
}
#endif /* PGM_WITH_LARGE_PAGES */
default:
}
/* not reached. */
#ifndef _MSC_VER
return fRet;
#endif
}
/**
* Scans one shadow page table for mappings of a physical page.
*
* @param pVM The VM handle.
* @param pPhysPage The guest page in question.
* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
* @param iShw The shadow page table.
*/
{
/* We should only come here with when there's only one reference to this physical page. */
Log2(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw));
bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, iShw, PGM_PAGE_GET_PTE_INDEX(pPhysPage));
if (!fKeptPTEs)
}
/**
* Flushes a list of shadow page tables mapping the same physical page.
*
* @param pVM The VM handle.
* @param pPhysPage The guest page in question.
* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
* @param iPhysExt The physical cross reference extent list to flush.
*/
static void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iPhysExt)
{
bool fKeepList = false;
Log2(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%RHp iPhysExt\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iPhysExt));
do
{
{
{
bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, pPhysExt->aidx[i], pPhysExt->apte[i]);
if (!fKeptPTEs)
{
}
else
fKeepList = true;
}
}
/* next */
} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
if (!fKeepList)
{
/* insert the list into the free list and clear the ram range entry. */
/* Invalidate the tracking data. */
}
}
/**
* Flushes all shadow page table mappings of the given guest page.
*
* This is typically called when the host page backing the guest one has been
* replaced or when the page protection was changed due to a guest access
* caught by the monitoring.
*
* @returns VBox status code.
* @retval VINF_SUCCESS if all references has been successfully cleared.
* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
* pool cleaning. FF and sync flags are set.
*
* @param pVM The VM handle.
* @param GCPhysPage GC physical address of the page in question
* @param pPhysPage The guest page in question.
* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
* flushed, it is NOT touched if this isn't necessary.
* The caller MUST initialized this to @a false.
*/
int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs)
{
int rc = VINF_SUCCESS;
#ifdef PGM_WITH_LARGE_PAGES
/* Is this page part of a large page? */
{
/* Fetch the large page base. */
if (GCPhysBase != GCPhysPage)
{
}
else
{
/* Mark the large page as disabled as we need to break it up to change a single page in the 2 MB range. */
/* Update the base as that *only* that one has a reference and there's only one PDE to clear. */
*pfFlushTLBs = true;
return rc;
}
}
#else
#endif /* PGM_WITH_LARGE_PAGES */
if (u16)
{
/*
* The zero page is currently screwing up the tracking and we'll
* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
* is defined, zero pages won't normally be mapped. Some kind of solution
* will be needed for this problem of course, but it will have to wait...
*/
if ( PGM_PAGE_IS_ZERO(pPhysPage)
else
{
# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC) /** @todo we can drop this now. */
/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
# endif
{
}
else
*pfFlushTLBs = true;
# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
# endif
}
}
if (rc == VINF_PGM_GCPHYS_ALIASED)
{
}
return rc;
}
/**
* Scans all shadow page tables for mappings of a physical page.
*
* This may be slow, but it's most likely more efficient than cleaning
* out the entire page pool / cache.
*
* @returns VBox status code.
* @retval VINF_SUCCESS if all references has been successfully cleared.
* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
* a page pool cleaning.
*
* @param pVM The VM handle.
* @param pPhysPage The guest page in question.
*/
{
LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
/*
* There is a limit to what makes sense.
*/
{
return VINF_PGM_GCPHYS_ALIASED;
}
/*
* Iterate all the pages until we've encountered all that in use.
* This is simple but not quite optimal solution.
*/
const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P; /** @todo drop X86_PTE_P here as we always test if present separately, anyway. */
while (--iPage >= PGMPOOL_IDX_FIRST)
{
{
{
/*
* We only care about shadow page tables.
*/
{
{
{
//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
pPT->a[i].u = 0;
/* Update the counter as we're removing references. */
}
if (!--cPresent)
break;
}
break;
}
{
if (PGMSHWPTEPAE_IS_P(pPT->a[i]))
{
{
//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
/* Update the counter as we're removing references. */
}
if (!--cPresent)
break;
}
break;
}
#ifndef IN_RC
{
{
{
//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
pPT->a[i].u = 0;
/* Update the counter as we're removing references. */
}
if (!--cPresent)
break;
}
break;
}
#endif
}
if (!--cLeft)
break;
}
}
/*
* There is a limit to what makes sense. The above search is very expensive, so force a pgm pool flush.
*/
{
return VINF_PGM_GCPHYS_ALIASED;
}
return VINF_SUCCESS;
}
/**
* Clears the user entry in a user table.
*
* This is used to remove all references to a page when flushing it.
*/
{
/*
* Map the user page.
*/
union
{
} u;
LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
/* Safety precaution in case we change the paging for other modes too in the future. */
#ifdef VBOX_STRICT
/*
* Some sanity checks.
*/
{
case PGMPOOLKIND_32BIT_PD:
break;
case PGMPOOLKIND_PAE_PDPT:
break;
case PGMPOOLKIND_PAE_PD_PHYS:
break;
break;
break;
case PGMPOOLKIND_64BIT_PML4:
/* GCPhys >> PAGE_SHIFT is the index here */
break;
break;
break;
case PGMPOOLKIND_ROOT_NESTED:
break;
default:
break;
}
#endif /* VBOX_STRICT */
/*
* Clear the entry in the user page.
*/
{
/* 32-bit entries */
case PGMPOOLKIND_32BIT_PD:
break;
/* 64-bit entries */
#ifdef IN_RC
/*
* In 32 bits PAE mode we *must* invalidate the TLB when changing a
* PDPT entry; the CPU fetches them only during cr3 load, so any
* non-present PDPT will continue to cause page faults.
*/
ASMReloadCR3();
/* no break */
#endif
case PGMPOOLKIND_PAE_PD_PHYS:
case PGMPOOLKIND_64BIT_PML4:
case PGMPOOLKIND_PAE_PDPT:
case PGMPOOLKIND_ROOT_NESTED:
break;
default:
AssertFatalMsgFailed(("enmKind=%d iUser=%d iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
}
}
/**
* Clears all users of a page.
*/
{
/*
* Free all the user records.
*/
while (i != NIL_PGMPOOL_USER_INDEX)
{
/* Clear enter in user table. */
/* Free it. */
pPool->iUserFreeHead = i;
/* Next. */
i = iNext;
}
}
/**
* Allocates a new physical cross reference extent.
*
* @returns Pointer to the allocated extent on success. NULL if we're out of them.
* @param pVM The VM handle.
* @param piPhysExt Where to store the phys ext index.
*/
{
if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
{
return NULL;
}
return pPhysExt;
}
/**
* Frees a physical cross reference extent.
*
* @param pVM The VM handle.
* @param iPhysExt The extent to free.
*/
{
{
}
}
/**
* Frees a physical cross reference extent.
*
* @param pVM The VM handle.
* @param iPhysExt The extent to free.
*/
{
do
{
{
}
/* next */
} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
}
/**
* Insert a reference into a list of physical cross reference extents.
*
* @returns The new tracking data for PGMPAGE.
*
* @param pVM The VM handle.
* @param iPhysExt The physical extent index of the list head.
* @param iShwPT The shadow page table index.
* @param iPte Page table entry
*
*/
static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT, uint16_t iPte)
{
/*
* Special common cases.
*/
{
}
{
}
/*
* General treatment.
*/
unsigned cMax = 15;
for (;;)
{
{
LogFlow(("pgmPoolTrackPhysExtInsert: %d:{%d pte %d} i=%d cMax=%d\n", iPhysExt, iShwPT, iPte, i, cMax));
}
if (!--cMax)
{
}
/* advance */
if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
break;
}
/*
* Add another extent to the list.
*/
if (!pNew)
{
}
LogFlow(("pgmPoolTrackPhysExtInsert: added new extent %d:{%d pte %d}->%d\n", iPhysExt, iShwPT, iPte, iPhysExtStart));
}
/**
* Add a reference to guest physical page where extents are in use.
*
* @returns The new tracking data for PGMPAGE.
*
* @param pVM The VM handle.
* @param pPhysPage Pointer to the aPages entry in the ram range.
* @param u16 The ram range flags (top 16-bits).
* @param iShwPT The shadow page table index.
* @param iPte Page table entry
*/
uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte)
{
{
/*
* Convert to extent list.
*/
if (pPhysExt)
{
LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
}
else
}
{
/*
* Insert into the extent list.
*/
}
else
return u16;
}
/**
* Clear references to guest physical memory.
*
* @param pPool The pool.
* @param pPage The page.
* @param pPhysPage Pointer to the aPages entry in the ram range.
* @param iPte Shadow PTE index
*/
void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage, uint16_t iPte)
{
AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
{
do
{
/*
* Look for the shadow page and check if it's all freed.
*/
{
{
{
return;
}
/* we can free the node. */
{
/* lonely node */
Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
}
else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
{
/* head */
Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
}
else
{
/* in list */
Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d in list\n", pPhysPage, pPage->idx));
}
return;
}
}
/* next */
} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
}
else /* nothing to do */
}
/**
* Clear references to guest physical memory.
*
* This is the same as pgmPoolTracDerefGCPhysHint except that the guest
* physical address is assumed to be correct, so the linear search can be
* skipped and we can assert at an earlier point.
*
* @param pPool The pool.
* @param pPage The page.
* @param HCPhys The host physical address corresponding to the guest page.
* @param GCPhys The guest physical address corresponding to HCPhys.
* @param iPte Shadow PTE index
*/
static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys, uint16_t iPte)
{
/*
* Lookup the page and check if it checks out before derefing it.
*/
if (pPhysPage)
{
#ifdef LOG_ENABLED
#endif
{
return;
}
AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp; found page has HCPhys=%RHp\n",
}
}
/**
* Clear references to guest physical memory.
*
* @param pPool The pool.
* @param pPage The page.
* @param HCPhys The host physical address corresponding to the guest page.
* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
* @param iPte Shadow pte index
*/
void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte)
{
/*
* Try the hint first.
*/
if (pPhysPage)
{
if (HCPhysHinted == HCPhys)
{
return;
}
}
else
/*
* Damn, the hint didn't work. We'll have to do an expensive linear search.
*/
while (pRam)
{
while (iPage-- > 0)
{
{
Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
return;
}
}
}
AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp (Hinted page has HCPhys = %RHp)\n", HCPhys, GCPhysHint, HCPhysHinted));
}
/**
* Clear references to guest physical memory in a 32-bit / 32-bit page table.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPT The shadow page table (mapping of the page).
* @param pGstPT The guest page table.
*/
DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
{
{
{
Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & fPgMask, i);
break;
}
}
}
/**
* Clear references to guest physical memory in a PAE / 32-bit page table.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPT The shadow page table (mapping of the page).
* @param pGstPT The guest page table (just a half one).
*/
DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT)
{
{
|| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
{
Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & fPgMask, i);
break;
}
}
}
/**
* Clear references to guest physical memory in a PAE / PAE page table.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPT The shadow page table (mapping of the page).
* @param pGstPT The guest page table.
*/
DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT)
{
RTGCPHYS const fPgMask = pPage->fA20Enabled ? X86_PTE_PAE_PG_MASK : X86_PTE_PAE_PG_MASK & ~RT_BIT_64(20);
{
|| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
{
Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & fPgMask, i);
break;
}
}
}
/**
* Clear references to guest physical memory in a 32-bit / 4MB page table.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPT The shadow page table (mapping of the page).
*/
{
{
{
Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
break;
}
}
}
/**
* Clear references to guest physical memory in a PAE / 2/4MB page table.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPT The shadow page table (mapping of the page).
*/
{
{
|| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
{
Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
pgmPoolTracDerefGCPhys(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), GCPhys & GCPhysA20Mask, i);
break;
}
}
}
/**
* Clear references to shadowed pages in an EPT page table.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
*/
{
{
{
Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
break;
}
}
}
/**
* Clear references to shadowed pages in a 32 bits page directory.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPD The shadow page directory (mapping of the page).
*/
{
for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
{
&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
)
{
PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
if (pSubPage)
else
}
}
}
/**
* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPD The shadow page directory (mapping of the page).
*/
{
for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
{
&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING))
{
#ifdef PGM_WITH_LARGE_PAGES
{
Log4(("pgmPoolTrackDerefPDPae: i=%d pde=%RX64 GCPhys=%RX64\n",
i);
}
else
#endif
{
PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
if (pSubPage)
else
/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
}
}
}
}
/**
* Clear references to shadowed pages in a PAE page directory pointer table.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
*/
{
for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
{
&& !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
)
{
PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
if (pSubPage)
else
}
}
}
/**
* Clear references to shadowed pages in a 64-bit page directory pointer table.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
*/
{
for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
{
{
PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
if (pSubPage)
else
/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
}
}
}
/**
* Clear references to shadowed pages in a 64-bit level 4 page table.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
*/
{
for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
{
{
PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
if (pSubPage)
else
/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
}
}
}
/**
* Clear references to shadowed pages in an EPT page directory.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPD The shadow page directory (mapping of the page).
*/
{
for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
{
{
#ifdef PGM_WITH_LARGE_PAGES
{
Log4(("pgmPoolTrackDerefPDEPT: i=%d pde=%RX64 GCPhys=%RX64\n",
i);
}
else
#endif
{
PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
if (pSubPage)
else
}
/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
}
}
}
/**
* Clear references to shadowed pages in an EPT page directory pointer table.
*
* @param pPool The pool.
* @param pPage The page.
* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
*/
{
for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
{
{
PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
if (pSubPage)
else
/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
}
}
}
/**
* Clears all references made by this page.
*
* This includes other shadow pages and GC physical addresses.
*
* @param pPool The pool.
* @param pPage The page.
*/
{
/*
* Map the shadow page and take action according to the page kind.
*/
{
{
void *pvGst;
break;
}
{
void *pvGst;
break;
}
{
void *pvGst;
break;
}
case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
{
break;
}
case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
{
break;
}
case PGMPOOLKIND_PAE_PD_PHYS:
break;
case PGMPOOLKIND_32BIT_PD:
break;
case PGMPOOLKIND_PAE_PDPT:
break;
break;
case PGMPOOLKIND_64BIT_PML4:
break;
break;
break;
break;
default:
}
/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
}
/**
* Flushes a pool page.
*
* This moves the page to the free list after removing all user references to it.
*
* @returns VBox status code.
* @retval VINF_SUCCESS on success.
* @param pPool The pool.
* @param HCPhys The HC physical address of the shadow page.
* @param fFlush Flush the TLBS when required (should only be false in very specific use cases!!)
*/
{
bool fFlushRequired = false;
int rc = VINF_SUCCESS;
LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
/*
* Quietly reject any attempts at flushing any of the special root pages.
*/
{
AssertFailed(); /* can no longer happen */
Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
return VINF_SUCCESS;
}
/*
* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
*/
if (pgmPoolIsPageLocked(pPage))
{
("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
return VINF_SUCCESS;
}
#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
/* Start a subset so we won't run out of mapping space. */
#endif
/*
* Mark the page as being in need of an ASMMemZeroPage().
*/
#endif
/* If there are any users of this table, then we *must* issue a tlb flush on all VCPUs. */
fFlushRequired = true;
/*
* Clear the page.
*/
/*
* Flush it from the cache.
*/
#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
/* Heavy stuff done. */
#endif
/*
* Deregistering the monitoring.
*/
if (pPage->fMonitored)
/*
* Free the page.
*/
pPage->fReusedFlushPending = false;
pPool->cUsedPages--;
/* Flush the TLBs of all VCPUs if required. */
if ( fFlushRequired
&& fFlush)
{
}
return rc;
}
/**
* Frees a usage of a pool page.
*
* The caller is responsible to updating the user table so that it no longer
* references the shadow page.
*
* @param pPool The pool.
* @param HCPhys The HC physical address of the shadow page.
* @param iUser The shadow page pool index of the user table.
* @param iUserTable The index into the user table (shadowed).
*/
{
LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%d iUserTable=%#x\n",
}
/**
* Makes one or more free page free.
*
* @returns VBox status code.
* @retval VINF_SUCCESS on success.
* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
*
* @param pPool The pool.
* @param enmKind Page table kind
* @param iUser The user of the page.
*/
{
/*
* If the pool isn't full grown yet, expand it.
*/
#if defined(IN_RC)
/* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
#endif
)
{
#ifdef IN_RING3
#else
#endif
if (RT_FAILURE(rc))
return rc;
return VINF_SUCCESS;
}
/*
* Free one cached page.
*/
}
/**
* Allocates a page from the pool.
*
* This page may actually be a cached page and not in need of any processing
* on the callers part.
*
* @returns VBox status code.
* @retval VINF_SUCCESS if a NEW page was allocated.
* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
*
* @param pVM The VM handle.
* @param GCPhys The GC physical address of the page we're gonna shadow.
* For 4MB and 2MB PD entries, it's the first address the
* shadow PT is covering.
* @param enmKind The kind of mapping.
* @param enmAccess Access type for the mapping (only relevant for big pages)
* @param fA20Enabled Whether the A20 gate is enabled or not.
* @param iUser The shadow page pool index of the user table.
* @param iUserTable The index into the user table (shadowed).
* @param fLockPage Lock the page
* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
*/
int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
{
LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%d iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
* (TRPMR3SyncIDT) because of FF priority. Try fix that?
* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)); */
if (pPool->fCacheEnabled)
{
int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, fA20Enabled, iUser, iUserTable, ppPage);
if (RT_SUCCESS(rc2))
{
if (fLockPage)
LogFlow(("pgmPoolAlloc: cached returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, *ppPage, (*ppPage)->Core.Key, (*ppPage)->idx));
return rc2;
}
}
/*
* Allocate a new one.
*/
int rc = VINF_SUCCESS;
if (iNew == NIL_PGMPOOL_IDX)
{
if (RT_FAILURE(rc))
{
return rc;
}
}
/* unlink the free head */
/*
* Initialize it.
*/
pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
pPage->fMonitored = false;
pPage->fReusedFlushPending = false;
pPage->cModifications = 0;
pPage->idxDirtyEntry = 0;
pPage->cLastAccessHandler = 0;
# ifdef VBOX_STRICT
# endif
/*
* Insert into the tracking and cache. If this fails, free the page.
*/
if (RT_FAILURE(rc3))
{
pPool->cUsedPages--;
return rc3;
}
/*
* Commit the allocation, clear the page and return.
*/
#ifdef VBOX_WITH_STATISTICS
#endif
{
}
if (fLockPage)
LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
return rc;
}
/**
* Frees a usage of a pool page.
*
* @param pVM The VM handle.
* @param HCPhys The HC physical address of the shadow page.
* @param iUser The shadow page pool index of the user table.
* @param iUserTable The index into the user table (shadowed).
*/
{
}
/**
* Internal worker for finding a 'in-use' shadow page give by it's physical address.
*
* @returns Pointer to the shadow page structure.
* @param pPool The pool.
* @param HCPhys The HC physical address of the shadow page.
*/
{
/*
* Look up the page.
*/
PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
return pPage;
}
/**
* Internal worker for finding a page for debugging purposes, no assertions.
*
* @returns Pointer to the shadow page structure. NULL on if not found.
* @param pPool The pool.
* @param HCPhys The HC physical address of the shadow page.
*/
{
}
#ifdef IN_RING3 /* currently only used in ring 3; save some space in the R0 & GC modules (left it here as we might need it elsewhere later on) */
/**
* Flush the specified page if present
*
* @param pVM The VM handle.
* @param GCPhys Guest physical address of the page to flush
*/
{
/*
* Look up the GCPhys in the hash.
*/
if (i == NIL_PGMPOOL_IDX)
return;
do
{
{
{
case PGMPOOLKIND_64BIT_PML4:
case PGMPOOLKIND_32BIT_PD:
case PGMPOOLKIND_PAE_PDPT:
{
else
#endif
return;
}
/* ignore, no monitoring. */
case PGMPOOLKIND_ROOT_NESTED:
case PGMPOOLKIND_PAE_PD_PHYS:
break;
default:
}
}
/* next */
} while (i != NIL_PGMPOOL_IDX);
return;
}
#endif /* IN_RING3 */
#ifdef IN_RING3
/**
* Reset CPU on hot plugging.
*
* @param pVM The VM handle.
* @param pVCpu The virtual CPU.
*/
{
}
/**
* Flushes the entire cache.
*
* It will assert a global CR3 flush (FF) and assumes the caller is aware of
* this and execute this CR3 flush.
*
* @param pPool The pool.
*/
{
LogFlow(("pgmR3PoolReset:\n"));
/*
* If there are no pages in the pool, there is nothing to do.
*/
{
return;
}
/*
* Exit the shadow mode since we're going to clear everything,
* including the root page.
*/
/*
* Nuke the free list and reinsert all pages into it.
*/
{
if (pPage->fMonitored)
pPage->cModifications = 0;
pPage->fA20Enabled = true;
pPage->fSeenNonGlobal = false;
pPage->fMonitored = false;
pPage->fReusedFlushPending = false;
pPage->cLastAccessHandler = 0;
#ifdef VBOX_STRICT
#endif
}
pPool->cUsedPages = 0;
/*
* Zap and reinitialize the user records.
*/
pPool->iUserFreeHead = 0;
for (unsigned i = 0; i < cMaxUsers; i++)
{
}
/*
* Clear all the GCPhys links and rebuild the phys ext free list.
*/
pRam;
{
while (iPage-- > 0)
}
pPool->iPhysExtFreeHead = 0;
for (unsigned i = 0; i < cMaxPhysExts; i++)
{
}
/*
* Just zap the modified list.
*/
pPool->cModifiedPages = 0;
/*
* Clear the GCPhys hash and the age list.
*/
/* Clear all dirty pages. */
pPool->idxFreeDirtyPage = 0;
pPool->cDirtyPages = 0;
#endif
/*
* Reinsert active pages into the hash and ensure monitoring chains are correct.
*/
for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
{
pPage->cModifications = 0;
/* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
if (pPage->fMonitored)
{
}
}
{
/*
* Re-enter the shadowing mode and assert Sync CR3 FF.
*/
}
}
#endif /* IN_RING3 */
#ifdef LOG_ENABLED
/**
* Stringifies a PGMPOOLKIND value.
*/
{
switch ((PGMPOOLKIND)enmKind)
{
case PGMPOOLKIND_INVALID:
return "PGMPOOLKIND_INVALID";
case PGMPOOLKIND_FREE:
return "PGMPOOLKIND_FREE";
return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
case PGMPOOLKIND_32BIT_PD:
return "PGMPOOLKIND_32BIT_PD";
return "PGMPOOLKIND_32BIT_PD_PHYS";
return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
case PGMPOOLKIND_PAE_PD_PHYS:
return "PGMPOOLKIND_PAE_PD_PHYS";
return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
case PGMPOOLKIND_PAE_PDPT:
return "PGMPOOLKIND_PAE_PDPT";
return "PGMPOOLKIND_PAE_PDPT_PHYS";
return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
case PGMPOOLKIND_64BIT_PML4:
return "PGMPOOLKIND_64BIT_PML4";
return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
case PGMPOOLKIND_ROOT_NESTED:
return "PGMPOOLKIND_ROOT_NESTED";
}
return "Unknown kind!";
}
#endif /* LOG_ENABLED*/