PGMAllMap.cpp revision 7517e6036eaa4efe0735dd66f1ec09dedc0664e7
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync/* $Id$ */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync/** @file
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * PGM - Page Manager and Monitor - All context code.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync/*
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync *
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * available from http://www.virtualbox.org. This file is free software;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * you can redistribute it and/or modify it under the terms of the GNU
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * General Public License (GPL) as published by the Free Software
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync *
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * additional information or have any questions.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync/*******************************************************************************
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync* Header Files *
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync*******************************************************************************/
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#define LOG_GROUP LOG_GROUP_PGM
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#include <VBox/pgm.h>
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#include "PGMInternal.h"
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#include <VBox/vm.h>
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#include <iprt/assert.h>
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#include <iprt/asm.h>
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#include <VBox/err.h>
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync/**
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Maps a range of physical pages at a given virtual address
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * in the guest context.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync *
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * The GC virtual address range must be within an existing mapping.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync *
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @returns VBox status code.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @param pVM The virtual machine.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @param GCPtr Where to map the page(s). Must be page aligned.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @param HCPhys Start of the range of physical pages. Must be page aligned.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @param cbPages Number of bytes to map. Must be page aligned.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @param fFlags Page flags (X86_PTE_*).
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsyncVMMDECL(int) PGMMap(PVM pVM, RTGCUINTPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync{
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /*
39cac49f62afd27b0ffdbb779c7c64211939030cvboxsync * Validate input.
39cac49f62afd27b0ffdbb779c7c64211939030cvboxsync */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync AssertMsg(RT_ALIGN_T(GCPtr, PAGE_SIZE, RTGCUINTPTR) == GCPtr, ("Invalid alignment GCPtr=%#x\n", GCPtr));
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync AssertMsg(cbPages > 0 && RT_ALIGN_32(cbPages, PAGE_SIZE) == cbPages, ("Invalid cbPages=%#x\n", cbPages));
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync AssertMsg(!(fFlags & X86_PDE_PG_MASK), ("Invalid flags %#x\n", fFlags));
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /* hypervisor defaults */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync if (!fFlags)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync fFlags = X86_PTE_P | X86_PTE_A | X86_PTE_D;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /*
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Find the mapping.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync while (pCur)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync {
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync if (GCPtr - pCur->GCPtr < pCur->cb)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync {
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync if (GCPtr + cbPages - 1 > pCur->GCPtrLast)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync {
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync AssertMsgFailed(("Invalid range!!\n"));
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync return VERR_INVALID_PARAMETER;
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync }
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /*
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Setup PTE.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync X86PTEPAE Pte;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync Pte.u = fFlags | (HCPhys & X86_PTE_PAE_PG_MASK);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /*
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Update the page tables.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync for (;;)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync {
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync RTGCUINTPTR off = GCPtr - pCur->GCPtr;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync const unsigned iPT = off >> X86_PD_SHIFT;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync const unsigned iPageNo = (off >> PAGE_SHIFT) & X86_PT_MASK;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /* 32-bit */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPageNo].u = (uint32_t)Pte.u; /* ASSUMES HCPhys < 4GB and/or that we're never gonna do 32-bit on a PAE host! */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /* pae */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPageNo / 512].a[iPageNo % 512].u = Pte.u;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /* next */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync cbPages -= PAGE_SIZE;
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync if (!cbPages)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync break;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync GCPtr += PAGE_SIZE;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync Pte.u += PAGE_SIZE;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync }
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync return VINF_SUCCESS;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync }
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /* next */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync pCur = pCur->CTX_SUFF(pNext);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync }
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync AssertMsgFailed(("GCPtr=%#x was not found in any mapping ranges!\n", GCPtr));
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync return VERR_INVALID_PARAMETER;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync}
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync/**
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Sets (replaces) the page flags for a range of pages in a mapping.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync *
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @returns VBox status.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @param pVM VM handle.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @param GCPtr Virtual address of the first page in the range.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @param cb Size (in bytes) of the range to apply the modification to.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsyncVMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync{
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync return PGMMapModifyPage(pVM, GCPtr, cb, fFlags, 0);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync}
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync/**
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Modify page flags for a range of pages in a mapping.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync *
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * The existing flags are ANDed with the fMask and ORed with the fFlags.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync *
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @returns VBox status code.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @param pVM VM handle.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @param GCPtr Virtual address of the first page in the range.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @param cb Size (in bytes) of the range to apply the modification to.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsyncVMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync{
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /*
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Validate input.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync */
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#x\n", fFlags));
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync Assert(cb);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync /*
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync * Align the input.
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync cb = RT_ALIGN_Z(cb, PAGE_SIZE);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync /*
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync * Find the mapping.
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync */
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync while (pCur)
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync {
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync RTGCUINTPTR off = (RTGCUINTPTR)GCPtr - (RTGCUINTPTR)pCur->GCPtr;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync if (off < pCur->cb)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync {
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync AssertMsgReturn(off + cb <= pCur->cb,
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync ("Invalid page range %#x LB%#x. mapping '%s' %#x to %#x\n",
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync GCPtr, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast),
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync VERR_INVALID_PARAMETER);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
39cac49f62afd27b0ffdbb779c7c64211939030cvboxsync /*
39cac49f62afd27b0ffdbb779c7c64211939030cvboxsync * Perform the requested operation.
39cac49f62afd27b0ffdbb779c7c64211939030cvboxsync */
39cac49f62afd27b0ffdbb779c7c64211939030cvboxsync while (cb > 0)
39cac49f62afd27b0ffdbb779c7c64211939030cvboxsync {
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync unsigned iPT = off >> X86_PD_SHIFT;
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync while (cb > 0 && iPTE < RT_ELEMENTS(pCur->aPTs[iPT].CTX_SUFF(pPT)->a))
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync {
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync /* 32-Bit */
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u &= fMask | X86_PTE_PG_MASK;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u |= fFlags & ~X86_PTE_PG_MASK;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /* PAE */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512].u &= fMask | X86_PTE_PAE_PG_MASK;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512].u |= fFlags & ~X86_PTE_PAE_PG_MASK;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /* invalidate tls */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync PGM_INVL_PG((RTGCUINTPTR)pCur->GCPtr + off);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /* next */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync iPTE++;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync cb -= PAGE_SIZE;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync off += PAGE_SIZE;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync }
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync }
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync return VINF_SUCCESS;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync }
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /* next */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync pCur = pCur->CTX_SUFF(pNext);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync }
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync AssertMsgFailed(("Page range %#x LB%#x not found\n", GCPtr, cb));
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync return VERR_INVALID_PARAMETER;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync}
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync#ifndef IN_RING0
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync/**
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Sets all PDEs involved with the mapping in the shadow page table.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync *
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync * @param pVM The VM handle.
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync * @param pMap Pointer to the mapping in question.
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync * @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync */
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsyncvoid pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync{
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync Log4(("pgmMapSetShadowPDEs new pde %x (mappings enabled %d)\n", iNewPDE, pgmMapAreMappingsEnabled(&pVM->pgm.s)));
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync return;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync if (!pVM->pgm.s.CTX_SUFF(pShwPageCR3))
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync return; /* too early */
39cac49f62afd27b0ffdbb779c7c64211939030cvboxsync#endif
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync PGMMODE enmShadowMode = PGMGetShadowMode(pVM);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync Assert(enmShadowMode <= PGMMODE_PAE_NX);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /*
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Init the page tables and insert them into the page directories.
39cac49f62afd27b0ffdbb779c7c64211939030cvboxsync */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync unsigned i = pMap->cPTs;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync iNewPDE += i;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync while (i-- > 0)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync {
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync iNewPDE--;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync switch(enmShadowMode)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync {
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync case PGMMODE_32_BIT:
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync {
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(&pVM->pgm.s);
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync AssertFatal(pShw32BitPd);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync if (pShw32BitPd->a[iNewPDE].n.u1Present)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync {
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync Assert(!(pShw32BitPd->a[iNewPDE].u & PGM_PDFLAGS_MAPPING));
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync pgmPoolFree(pVM, pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iNewPDE);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync }
X86PDE Pde;
/* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags */
Pde.u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT;
pShw32BitPd->a[iNewPDE] = Pde;
break;
}
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
{
PX86PDPT pShwPdpt;
PX86PDPAE pShwPaePd;
const unsigned iPdPt = iNewPDE / 256;
unsigned iPDE = iNewPDE * 2 % 512;
pShwPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
Assert(pShwPdpt);
pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, (iPdPt << X86_PDPT_SHIFT));
#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
if (!pShwPaePd)
{
X86PDPE GstPdpe;
if (PGMGetGuestMode(pVM) < PGMMODE_PAE)
{
/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
GstPdpe.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
}
else
{
PX86PDPE pGstPdpe;
pGstPdpe = pgmGstGetPaePDPEPtr(&pVM->pgm.s, (iPdPt << X86_PDPT_SHIFT));
if (pGstPdpe)
GstPdpe = *pGstPdpe;
else
GstPdpe.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
}
int rc = pgmShwSyncPaePDPtr(pVM, (iPdPt << X86_PDPT_SHIFT), &GstPdpe, &pShwPaePd);
AssertFatal(RT_SUCCESS(rc));
if (rc != VINF_SUCCESS)
{
rc = pgmShwSyncPaePDPtr(pVM, (iPdPt << X86_PDPT_SHIFT), &GstPdpe, &pShwPaePd);
AssertFatalMsg(rc == VINF_SUCCESS, ("rc = %Rrc\n", rc));
}
}
#endif
AssertFatal(pShwPaePd);
PPGMPOOLPAGE pPoolPagePde = pgmPoolGetPageByHCPhys(pVM, pShwPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
AssertFatal(pPoolPagePde);
if (pShwPaePd->a[iPDE].n.u1Present)
{
Assert(!(pShwPaePd->a[iPDE].u & PGM_PDFLAGS_MAPPING));
pgmPoolFree(pVM, pShwPaePd->a[iPDE].u & X86_PDE_PG_MASK, pPoolPagePde->idx, iNewPDE);
}
X86PDEPAE PdePae0;
PdePae0.u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT0;
pShwPaePd->a[iPDE] = PdePae0;
/* 2nd 2 MB PDE of the 4 MB region */
iPDE++;
AssertFatal(iPDE < 512);
if (pShwPaePd->a[iPDE].n.u1Present)
{
Assert(!(pShwPaePd->a[iPDE].u & PGM_PDFLAGS_MAPPING));
pgmPoolFree(pVM, pShwPaePd->a[iPDE].u & X86_PDE_PG_MASK, pPoolPagePde->idx, iNewPDE);
}
X86PDEPAE PdePae1;
PdePae1.u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT1;
pShwPaePd->a[iPDE] = PdePae1;
/* Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode) */
pShwPdpt->a[iPdPt].u |= PGM_PLXFLAGS_MAPPING;
break;
}
default:
AssertFailed();
break;
}
}
}
/**
* Clears all PDEs involved with the mapping in the shadow page table.
*
* @param pVM The VM handle.
* @param pShwPageCR3 CR3 root page
* @param pMap Pointer to the mapping in question.
* @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
*/
void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE)
{
Log(("pgmMapClearShadowPDEs old pde %x (mappings enabled %d)\n", iOldPDE, pgmMapAreMappingsEnabled(&pVM->pgm.s)));
if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
return;
#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
Assert(pShwPageCR3);
#endif
unsigned i = pMap->cPTs;
PGMMODE enmShadowMode = PGMGetShadowMode(pVM);
iOldPDE += i;
while (i-- > 0)
{
iOldPDE--;
switch(enmShadowMode)
{
case PGMMODE_32_BIT:
{
#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
PX86PD pShw32BitPd = (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
#else
PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(&pVM->pgm.s);
#endif
AssertFatal(pShw32BitPd);
pShw32BitPd->a[iOldPDE].u = 0;
break;
}
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
{
PX86PDPT pPdpt = NULL;
PX86PDPAE pShwPaePd = NULL;
const unsigned iPD = iOldPDE / 256; /* iOldPDE * 2 / 512; iOldPDE is in 4 MB pages */
unsigned iPDE = iOldPDE * 2 % 512;
#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, pPdpt, (iPD << X86_PDPT_SHIFT));
#else
pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, (iPD << X86_PDPT_SHIFT));
#endif
AssertFatal(pShwPaePd);
pShwPaePd->a[iPDE].u = 0;
iPDE++;
AssertFatal(iPDE < 512);
pShwPaePd->a[iPDE].u = 0;
/* Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode) */
pPdpt->a[iPD].u &= ~PGM_PLXFLAGS_MAPPING;
break;
}
default:
AssertFailed();
break;
}
}
}
#endif /* !IN_RING0 */
#ifdef VBOX_STRICT
/**
* Clears all PDEs involved with the mapping in the shadow page table.
*
* @param pVM The VM handle.
* @param pShwPageCR3 CR3 root page
* @param pMap Pointer to the mapping in question.
* @param iPDE The index of the 32-bit PDE corresponding to the base of the mapping.
*/
void pgmMapCheckShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iPDE)
{
Log(("pgmMapCheckShadowPDEs pde %x (mappings enabled %d)\n", iPDE, pgmMapAreMappingsEnabled(&pVM->pgm.s)));
if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
return;
#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
Assert(pShwPageCR3);
#endif
unsigned i = pMap->cPTs;
PGMMODE enmShadowMode = PGMGetShadowMode(pVM);
iPDE += i;
while (i-- > 0)
{
iPDE--;
switch(enmShadowMode)
{
case PGMMODE_32_BIT:
{
#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
PX86PD pShw32BitPd = (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
#else
PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(&pVM->pgm.s);
#endif
AssertFatal(pShw32BitPd);
AssertMsg(pShw32BitPd->a[iPDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT),
("Expected %x vs %x\n", pShw32BitPd->a[iPDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT)));
break;
}
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
{
PX86PDPT pPdpt = NULL;
PX86PDPAE pShwPaePd = NULL;
const unsigned iPD = iPDE / 256; /* iPDE * 2 / 512; iPDE is in 4 MB pages */
unsigned iPaePDE = iPDE * 2 % 512;
#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, pPdpt, (iPD << X86_PDPT_SHIFT));
#else
pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, (iPD << X86_PDPT_SHIFT));
#endif
AssertFatal(pShwPaePd);
AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT0),
("Expected %RX64 vs %RX64\n", pShwPaePd->a[iPDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT)));
iPaePDE++;
AssertFatal(iPaePDE < 512);
AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT1),
("Expected %RX64 vs %RX64\n", pShwPaePd->a[iPDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT)));
break;
}
default:
AssertFailed();
break;
}
}
}
/**
* Check the hypervisor mappings in the active CR3.
*
* @param pVM The virtual machine.
*/
VMMDECL(void) PGMMapCheck(PVM pVM)
{
#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
Log(("PGMMapCheck fixed mappings=%d\n", pVM->pgm.s.fMappingsFixed));
/*
* Can skip this if mappings are disabled.
*/
if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
return;
# ifdef IN_RING0
AssertFailed();
# else
# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
# endif
/*
* Iterate mappings.
*/
for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
{
unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
pgmMapCheckShadowPDEs(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pCur, iPDE);
}
# endif /* IN_RING0 */
#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
}
#endif
/**
* Apply the hypervisor mappings to the active CR3.
*
* @returns VBox status.
* @param pVM The virtual machine.
*/
VMMDECL(int) PGMMapActivateAll(PVM pVM)
{
/* @note A log flush (in RC) can cause problems when called from MapCR3 (inconsistent state will trigger assertions). */
Log4(("PGMMapActivateAll fixed mappings=%d\n", pVM->pgm.s.fMappingsFixed));
#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
/*
* Can skip this if mappings are disabled.
*/
if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
#else
/*
* Can skip this if mappings are safely fixed.
*/
if (pVM->pgm.s.fMappingsFixed)
#endif
return VINF_SUCCESS;
#ifdef IN_RING0
AssertFailed();
return VERR_INTERNAL_ERROR;
#else
# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
# endif
/*
* Iterate mappings.
*/
for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
{
unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
pgmMapSetShadowPDEs(pVM, pCur, iPDE);
}
return VINF_SUCCESS;
#endif /* IN_RING0 */
}
/**
* Remove the hypervisor mappings from the active CR3
*
* @returns VBox status.
* @param pVM The virtual machine.
*/
VMMDECL(int) PGMMapDeactivateAll(PVM pVM)
{
Log(("PGMMapDeactivateAll fixed mappings=%d\n", pVM->pgm.s.fMappingsFixed));
#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
/*
* Can skip this if mappings are disabled.
*/
if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
#else
/*
* Can skip this if mappings are safely fixed.
*/
if (pVM->pgm.s.fMappingsFixed)
#endif
return VINF_SUCCESS;
#ifdef IN_RING0
AssertFailed();
return VERR_INTERNAL_ERROR;
#else
# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
# endif
/*
* Iterate mappings.
*/
for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
{
unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
pgmMapClearShadowPDEs(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pCur, iPDE);
}
return VINF_SUCCESS;
#endif /* IN_RING0 */
}
/**
* Remove the hypervisor mappings from the specified CR3
*
* @returns VBox status.
* @param pVM The virtual machine.
* @param pShwPageCR3 CR3 root page
*/
int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
{
#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
/*
* Can skip this if mappings are disabled.
*/
if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
#else
/*
* Can skip this if mappings are safely fixed.
*/
if (pVM->pgm.s.fMappingsFixed)
#endif
return VINF_SUCCESS;
#ifdef IN_RING0
AssertFailed();
return VERR_INTERNAL_ERROR;
#else
# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
# endif
/*
* Iterate mappings.
*/
for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
{
unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
pgmMapClearShadowPDEs(pVM, pShwPageCR3, pCur, iPDE);
}
return VINF_SUCCESS;
#endif /* IN_RING0 */
}
#ifndef IN_RING0
/**
* Checks guest PD for conflicts with VMM GC mappings.
*
* @returns true if conflict detected.
* @returns false if not.
* @param pVM The virtual machine.
*/
VMMDECL(bool) PGMMapHasConflicts(PVM pVM)
{
/*
* Can skip this if mappings are safely fixed.
*/
if (pVM->pgm.s.fMappingsFixed)
return false;
PGMMODE const enmGuestMode = PGMGetGuestMode(pVM);
Assert(enmGuestMode <= PGMMODE_PAE_NX);
/*
* Iterate mappings.
*/
if (enmGuestMode == PGMMODE_32_BIT)
{
/*
* Resolve the page directory.
*/
PX86PD pPD = pgmGstGet32bitPDPtr(&pVM->pgm.s);
Assert(pPD);
for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
{
unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
unsigned iPT = pCur->cPTs;
while (iPT-- > 0)
if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
&& (pVM->fRawR0Enabled || pPD->a[iPDE + iPT].n.u1User))
{
STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
#ifdef IN_RING3
Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
" iPDE=%#x iPT=%#x PDE=%RGp.\n",
(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
#else
Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
" iPDE=%#x iPT=%#x PDE=%RGp.\n",
(iPT + iPDE) << X86_PD_SHIFT,
iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
#endif
return true;
}
}
}
else if ( enmGuestMode == PGMMODE_PAE
|| enmGuestMode == PGMMODE_PAE_NX)
{
for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
{
RTGCPTR GCPtr = pCur->GCPtr;
unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
while (iPT-- > 0)
{
X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
if ( Pde.n.u1Present
&& (pVM->fRawR0Enabled || Pde.n.u1User))
{
STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
#ifdef IN_RING3
Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
" PDE=%016RX64.\n",
GCPtr, pCur->pszDesc, Pde.u));
#else
Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
" PDE=%016RX64.\n",
GCPtr, Pde.u));
#endif
return true;
}
GCPtr += (1 << X86_PD_PAE_SHIFT);
}
}
}
else
AssertFailed();
return false;
}
# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
/**
* Checks and resolves (ring 3 only) guest conflicts with VMM GC mappings.
*
* @returns VBox status.
* @param pVM The virtual machine.
*/
VMMDECL(int) PGMMapResolveConflicts(PVM pVM)
{
/*
* Can skip this if mappings are safely fixed.
*/
if (pVM->pgm.s.fMappingsFixed)
return VINF_SUCCESS;
PGMMODE const enmGuestMode = PGMGetGuestMode(pVM);
Assert(enmGuestMode <= PGMMODE_PAE_NX);
/*
* Iterate mappings.
*/
if (enmGuestMode == PGMMODE_32_BIT)
{
/*
* Resolve the page directory.
*/
PX86PD pPD = pgmGstGet32bitPDPtr(&pVM->pgm.s);
Assert(pPD);
for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
{
unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
unsigned iPT = pCur->cPTs;
while (iPT-- > 0)
{
if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
&& (pVM->fRawR0Enabled || pPD->a[iPDE + iPT].n.u1User))
{
STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
#ifdef IN_RING3
Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
" iPDE=%#x iPT=%#x PDE=%RGp.\n",
(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
int rc = pgmR3SyncPTResolveConflict(pVM, pCur, pPD, iPDE << X86_PD_SHIFT);
AssertRCReturn(rc, rc);
/*
* Update pCur.
*/
pCur = pVM->pgm.s.CTX_SUFF(pMappings);
while (pCur && pCur->GCPtr < (iPDE << X86_PD_SHIFT))
pCur = pCur->CTX_SUFF(pNext);
break;
#else
Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
" iPDE=%#x iPT=%#x PDE=%RGp.\n",
(iPT + iPDE) << X86_PD_SHIFT,
iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
return VINF_PGM_SYNC_CR3;
#endif
}
}
if (!pCur)
break;
}
}
else if ( enmGuestMode == PGMMODE_PAE
|| enmGuestMode == PGMMODE_PAE_NX)
{
for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
{
RTGCPTR GCPtr = pCur->GCPtr;
unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
while (iPT-- > 0)
{
X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
if ( Pde.n.u1Present
&& (pVM->fRawR0Enabled || Pde.n.u1User))
{
STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
#ifdef IN_RING3
Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
" PDE=%016RX64.\n",
GCPtr, pCur->pszDesc, Pde.u));
int rc = pgmR3SyncPTResolveConflictPAE(pVM, pCur, GCPtr);
AssertRCReturn(rc, rc);
/*
* Update pCur.
*/
pCur = pVM->pgm.s.CTX_SUFF(pMappings);
while (pCur && pCur->GCPtr < GCPtr)
pCur = pCur->CTX_SUFF(pNext);
break;
#else
Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
" PDE=%016RX64.\n",
GCPtr, Pde.u));
return VINF_PGM_SYNC_CR3;
#endif
}
GCPtr += (1 << X86_PD_PAE_SHIFT);
}
if (!pCur)
break;
}
}
else
AssertFailed();
return VINF_SUCCESS;
}
# endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
#endif /* IN_RING0 */