VMM/VMMAll/PGMAllGst.h

	PGMAllGst.h revision 9f9a20823b87e89c1b5cb45eb9b5699b29bfefeb
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync/* $Id$ */
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync/** @file
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync * VBox - Page Manager, Guest Paging Template - All context code.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync */
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync/*
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * Copyright (C) 2006-2010 Oracle Corporation
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync *
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * available from http://www.virtualbox.org. This file is free software;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * you can redistribute it and/or modify it under the terms of the GNU
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * General Public License (GPL) as published by the Free Software
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync */
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync/*******************************************************************************
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync*   Internal Functions                                                         *
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync*******************************************************************************/
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsyncRT_C_DECLS_BEGIN
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT \
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync || PGM_GST_TYPE == PGM_TYPE_PAE \
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync || PGM_GST_TYPE == PGM_TYPE_AMD64
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsyncstatic int PGM_GST_NAME(Walk)(PVMCPU pVCpu, RTGCPTR GCPtr, PGSTPTWALK pWalk);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync#endif
da957c069c2a3c582fe265ff88170ce4c42b499dvboxsyncPGM_GST_DECL(int,  GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsyncPGM_GST_DECL(int,  ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsyncPGM_GST_DECL(int,  GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsyncPGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsyncRT_C_DECLS_END
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT \
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync || PGM_GST_TYPE == PGM_TYPE_PAE \
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync || PGM_GST_TYPE == PGM_TYPE_AMD64
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsyncDECLINLINE(int) PGM_GST_NAME(WalkReturnNotPresent)(PVMCPU pVCpu, PGSTPTWALK pWalk, int iLevel)
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync{
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync    NOREF(iLevel);
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync    pWalk->Core.fNotPresent     = true;
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync    pWalk->Core.uLevel          = (uint8_t)iLevel;
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync    return VERR_PAGE_TABLE_NOT_PRESENT;
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync}
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsyncDECLINLINE(int) PGM_GST_NAME(WalkReturnBadPhysAddr)(PVMCPU pVCpu, PGSTPTWALK pWalk, int rc, int iLevel)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync{
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc));
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    pWalk->Core.fBadPhysAddr    = true;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    pWalk->Core.uLevel          = (uint8_t)iLevel;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    return VERR_PAGE_TABLE_NOT_PRESENT;
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync}
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsyncDECLINLINE(int) PGM_GST_NAME(WalkReturnRsvdError)(PVMCPU pVCpu, PGSTPTWALK pWalk, int iLevel)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync{
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    pWalk->Core.fRsvdError      = true;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    pWalk->Core.uLevel          = (uint8_t)iLevel;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    return VERR_PAGE_TABLE_NOT_PRESENT;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync}
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync/**
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * Performs a guest page table walk.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync *
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @returns VBox status code.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @retval  VINF_SUCCESS on success.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @retval  VERR_PAGE_TABLE_NOT_PRESENT on failure.  Check pWalk for details.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync *
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync * @param   pVCpu       The current CPU.
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync * @param   GCPtr       The guest virtual address to walk by.
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync * @param   pWalk       Where to return the walk result. This is always set.
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync */
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsyncstatic int PGM_GST_NAME(Walk)(PVMCPU pVCpu, RTGCPTR GCPtr, PGSTPTWALK pWalk)
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync{
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync    int rc;
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync    /*
fe96bc0e43d9c137304462ef8c2d79cbff22446fvboxsync     * Init the walking structure.
fa033b734cf3b131680f290326ccbbd23c42946bvboxsync     */
fe96bc0e43d9c137304462ef8c2d79cbff22446fvboxsync    RT_ZERO(*pWalk);
fe96bc0e43d9c137304462ef8c2d79cbff22446fvboxsync    pWalk->Core.GCPtr = GCPtr;
fe96bc0e43d9c137304462ef8c2d79cbff22446fvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# if PGM_GST_TYPE == PGM_TYPE_32BIT \
fa033b734cf3b131680f290326ccbbd23c42946bvboxsync  || PGM_GST_TYPE == PGM_TYPE_PAE
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    /*
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync     * Boundary check for PAE and 32-bit (prevents trouble further down).
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync     */
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    if (RT_UNLIKELY(GCPtr >= _4G))
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 8);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# endif
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync    {
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# if PGM_GST_TYPE == PGM_TYPE_AMD64
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync        /*
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync         * The PMLE4.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync         */
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync        rc = pgmGstGetLongModePML4PtrEx(pVCpu, &pWalk->pPml4);
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync        if (RT_FAILURE(rc))
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync            return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 4, rc);
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync        PX86PML4  register  pPml4 = pWalk->pPml4;
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync        X86PML4E  register  Pml4e;
ee4d840f54fd2dcea8a73b1b86d5ec0db370b05dvboxsync        PX86PML4E register  pPml4e;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        pWalk->pPml4e  = pPml4e  = &pPml4->a[(GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK];
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        pWalk->Pml4e.u = Pml4e.u = pPml4e->u;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        if (!Pml4e.n.u1Present)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync            return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 4);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        if (RT_UNLIKELY(!GST_IS_PML4E_VALID(pVCpu, Pml4e)))
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync            return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 4);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync        /*
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync         * The PDPE.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync         */
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pWalk->pPdpt);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        if (RT_FAILURE(rc))
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync            return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync# elif PGM_GST_TYPE == PGM_TYPE_PAE
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync        rc = pgmGstGetPaePDPTPtrEx(pVCpu, &pWalk->pPdpt);
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync        if (RT_FAILURE(rc))
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync            return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync# endif
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync    }
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync    {
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync# if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync        PX86PDPT register   pPdpt = pWalk->pPdpt;
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync        PX86PDPE register   pPdpe;
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync        X86PDPE  register   Pdpe;
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync
aa32d4906f2f685992091893d5abdf27a2352a85vboxsync        pWalk->pPdpe  = pPdpe  = &pPdpt->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
e3f5c51715cbf77ae2d2e9d05bafd00d69b1bec9vboxsync        pWalk->Pdpe.u = Pdpe.u = pPdpe->u;
aa32d4906f2f685992091893d5abdf27a2352a85vboxsync        if (!Pdpe.n.u1Present)
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync            return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 3);
aa32d4906f2f685992091893d5abdf27a2352a85vboxsync        if (RT_UNLIKELY(!GST_IS_PDPE_VALID(pVCpu, Pdpe)))
e3f5c51715cbf77ae2d2e9d05bafd00d69b1bec9vboxsync            return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 3);
aa32d4906f2f685992091893d5abdf27a2352a85vboxsync
aa32d4906f2f685992091893d5abdf27a2352a85vboxsync        /*
aa32d4906f2f685992091893d5abdf27a2352a85vboxsync         * The PDE.
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync         */
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync        rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pWalk->pPd);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        if (RT_FAILURE(rc))
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync            return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 2, rc);
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync# elif PGM_GST_TYPE == PGM_TYPE_32BIT
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync        rc = pgmGstGet32bitPDPtrEx(pVCpu, &pWalk->pPd);
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync        if (RT_FAILURE(rc))
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync            return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync# endif
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync    }
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync    {
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync        PGSTPD  register    pPd = pWalk->pPd;
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync        PGSTPDE register    pPde;
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync        GSTPDE              Pde;
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync        pWalk->pPde  = pPde  = &pPd->a[(GCPtr >> GST_PD_SHIFT) & GST_PD_MASK];
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync        pWalk->Pde.u = Pde.u = pPde->u;
b7a5b3f9f9ecce32ddacf8404c625ce0451bbdc1vboxsync        if (!Pde.n.u1Present)
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync            return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 2);
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync        if (Pde.n.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync        {
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync            if (RT_UNLIKELY(!GST_IS_BIG_PDE_VALID(pVCpu, Pde)))
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync                return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync            pWalk->Core.GCPhys       = GST_GET_BIG_PDE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pde)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync                                     | (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync            uint8_t fEffectiveXX     = (uint8_t)pWalk->Pde.u
b514c03a427443a7ad18c1202d2ee7acc47cf9afvboxsync#  if PGM_GST_TYPE == PGM_TYPE_AMD64
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync                                     & (uint8_t)pWalk->Pde.u
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync                                     & (uint8_t)pWalk->Pml4e.u
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync#  endif
b7a5b3f9f9ecce32ddacf8404c625ce0451bbdc1vboxsync                                     ;
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync            pWalk->Core.fEffectiveRW = !!(fEffectiveXX & X86_PTE_RW);
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync            pWalk->Core.fEffectiveUS = !!(fEffectiveXX & X86_PTE_US);
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync# if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync            pWalk->Core.fEffectiveNX = (   pWalk->Pde.n.u1NoExecute
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync#  if PGM_GST_TYPE == PGM_TYPE_AMD64
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync                                        || pWalk->Pde.n.u1NoExecute
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync                                        || pWalk->Pml4e.n.u1NoExecute
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync#  endif
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync                                       ) && GST_IS_NX_ACTIVE(pVCpu);
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync# else
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync            pWalk->Core.fEffectiveNX = false;
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync# endif
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync            pWalk->Core.fBigPage     = true;
fe813b3594039ba864493438e78ee0e7132bc445vboxsync            pWalk->Core.fSucceeded   = true;
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync            return VINF_SUCCESS;
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync        }
b514c03a427443a7ad18c1202d2ee7acc47cf9afvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        if (RT_UNLIKELY(!GST_IS_PDE_VALID(pVCpu, Pde)))
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync            return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        /*
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync         * The PTE.
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync         */
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync        rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GST_GET_PDE_GCPHYS(Pde), &pWalk->pPt);
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync        if (RT_FAILURE(rc))
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync            return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    }
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    {
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        PGSTPT  register    pPt = pWalk->pPt;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        PGSTPTE register    pPte;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        GSTPTE  register    Pte;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        pWalk->pPte  = pPte  = &pPt->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        pWalk->Pte.u = Pte.u = pPte->u;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        if (!Pte.n.u1Present)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync            return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 1);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        if (RT_UNLIKELY(!GST_IS_PTE_VALID(pVCpu, Pte)))
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync            return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 1);
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        /*
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync         * We're done.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync         */
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        pWalk->Core.GCPhys       = GST_GET_PDE_GCPHYS(Pte)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync                                 | (GCPtr & PAGE_OFFSET_MASK);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        uint8_t fEffectiveXX     = (uint8_t)pWalk->Pte.u
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync                                 & (uint8_t)pWalk->Pde.u
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync#  if PGM_GST_TYPE == PGM_TYPE_AMD64
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync                                 & (uint8_t)pWalk->Pde.u
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync                                 & (uint8_t)pWalk->Pml4e.u
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync#  endif
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync                                 ;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        pWalk->Core.fEffectiveRW = !!(fEffectiveXX & X86_PTE_RW);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        pWalk->Core.fEffectiveUS = !!(fEffectiveXX & X86_PTE_US);
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync# if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
b7a5b3f9f9ecce32ddacf8404c625ce0451bbdc1vboxsync        pWalk->Core.fEffectiveNX = (   pWalk->Pte.n.u1NoExecute
c6958b923ed12aadcf58ebbdbc80aadebbd9493evboxsync                                    || pWalk->Pde.n.u1NoExecute
fe813b3594039ba864493438e78ee0e7132bc445vboxsync#  if PGM_GST_TYPE == PGM_TYPE_AMD64
c6958b923ed12aadcf58ebbdbc80aadebbd9493evboxsync                                    || pWalk->Pde.n.u1NoExecute
c6958b923ed12aadcf58ebbdbc80aadebbd9493evboxsync                                    || pWalk->Pml4e.n.u1NoExecute
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync#  endif
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync                                   ) && GST_IS_NX_ACTIVE(pVCpu);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# else
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        pWalk->Core.fEffectiveNX = false;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# endif
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        pWalk->Core.fSucceeded   = true;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        return VINF_SUCCESS;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    }
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync}
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync#endif /* 32BIT, PAE, AMD64 */
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync/**
b7a5b3f9f9ecce32ddacf8404c625ce0451bbdc1vboxsync * Gets effective Guest OS page information.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync *
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * When GCPtr is in a big page, the function will return as if it was a normal
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * 4KB page. If the need for distinguishing between big and normal page becomes
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * necessary at a later point, a PGMGstGetPage Ex() will be created for that
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync * purpose.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync *
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @returns VBox status.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @param   pVCpu       The VMCPU handle.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @param   GCPtr       Guest Context virtual address of the page.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @param   pfFlags     Where to store the flags. These are X86_PTE_*, even for big pages.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @param   pGCPhys     Where to store the GC physical address of the page.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync *                      This is page aligned!
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync */
b1cc88518a7578ee20491f3d97b9792c24c6428dvboxsyncPGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
fe813b3594039ba864493438e78ee0e7132bc445vboxsync{
b1cc88518a7578ee20491f3d97b9792c24c6428dvboxsync#if PGM_GST_TYPE == PGM_TYPE_REAL \
b1cc88518a7578ee20491f3d97b9792c24c6428dvboxsync || PGM_GST_TYPE == PGM_TYPE_PROT
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    /*
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync     * Fake it.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync     */
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync    if (pfFlags)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        *pfFlags = X86_PTE_P | X86_PTE_RW | X86_PTE_US;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    if (pGCPhys)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        *pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    return VINF_SUCCESS;
362838d79d234a41380be42aae9118850cc3c929vboxsync
362838d79d234a41380be42aae9118850cc3c929vboxsync#elif PGM_GST_TYPE == PGM_TYPE_32BIT \
362838d79d234a41380be42aae9118850cc3c929vboxsync   || PGM_GST_TYPE == PGM_TYPE_PAE \
362838d79d234a41380be42aae9118850cc3c929vboxsync   || PGM_GST_TYPE == PGM_TYPE_AMD64
362838d79d234a41380be42aae9118850cc3c929vboxsync
bc36547e8dd3d35e5f756643a267bbe01e2c1d4cvboxsync    GSTPTWALK Walk;
bc36547e8dd3d35e5f756643a267bbe01e2c1d4cvboxsync    int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk);
362838d79d234a41380be42aae9118850cc3c929vboxsync    if (RT_FAILURE(rc))
bc36547e8dd3d35e5f756643a267bbe01e2c1d4cvboxsync        return rc;
362838d79d234a41380be42aae9118850cc3c929vboxsync
362838d79d234a41380be42aae9118850cc3c929vboxsync    if (pGCPhys)
362838d79d234a41380be42aae9118850cc3c929vboxsync        *pGCPhys = Walk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
362838d79d234a41380be42aae9118850cc3c929vboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    if (pfFlags)
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync    {
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync        if (!Walk.Core.fBigPage)
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync            *pfFlags = (Walk.Pte.u & ~(GST_PTE_PG_MASK | X86_PTE_RW | X86_PTE_US))                      /* NX not needed */
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync                     | (Walk.Core.fEffectiveRW ? X86_PTE_RW : 0)
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync                     | (Walk.Core.fEffectiveUS ? X86_PTE_US : 0)
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync                     | (Walk.Core.fEffectiveNX ? X86_PTE_PAE_NX : 0)
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync# endif
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync                     ;
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync        else
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync        {
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync            *pfFlags = (Walk.Pde.u & ~(GST_PTE_PG_MASK | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PS))   /* NX not needed */
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync                     | ((Walk.Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT)
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync                     | (Walk.Core.fEffectiveRW ? X86_PTE_RW : 0)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync                     | (Walk.Core.fEffectiveUS ? X86_PTE_US : 0)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync                     | (Walk.Core.fEffectiveNX ? X86_PTE_PAE_NX : 0)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# endif
ad77e3ec3cde24263bc7537575f5cae442bee3b1vboxsync                     ;
cba6719bd64ec749967bbe931230452664109857vboxsync        }
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    }
cba6719bd64ec749967bbe931230452664109857vboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    return VINF_SUCCESS;
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync#else
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# error "shouldn't be here!"
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    /* something else... */
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    return VERR_NOT_SUPPORTED;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync#endif
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync}
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync/**
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * Modify page flags for a range of pages in the guest's tables
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync *
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync * The existing flags are ANDed with the fMask and ORed with the fFlags.
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync *
22bdb1ce26b2d5a41d1b071c16f1078e5348bb0dvboxsync * @returns VBox status code.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @param   pVCpu       The VMCPU handle.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @param   GCPtr       Virtual address of the first page in the range. Page aligned!
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @param   cb          Size (in bytes) of the page range to apply the modification to. Page aligned!
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @param   fFlags      The OR  mask - page flags X86_PTE_*, excluding the page mask of course.
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync * @param   fMask       The AND mask - page flags X86_PTE_*.
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync */
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsyncPGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync{
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    Assert((cb & PAGE_OFFSET_MASK) == 0);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT \
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync || PGM_GST_TYPE == PGM_TYPE_PAE \
cba6719bd64ec749967bbe931230452664109857vboxsync || PGM_GST_TYPE == PGM_TYPE_AMD64
b7a5b3f9f9ecce32ddacf8404c625ce0451bbdc1vboxsync    for (;;)
30adc6dd25ed9fef4d800a6d9f1ab7e765b4c340vboxsync    {
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync        GSTPTWALK Walk;
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync        int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        if (RT_FAILURE(rc))
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync            return rc;
ad77e3ec3cde24263bc7537575f5cae442bee3b1vboxsync
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync        if (!Walk.Core.fBigPage)
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync        {
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync            /*
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync             * 4KB Page table, process
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync             *
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync             * Walk pages till we're done.
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync             */
801238b286a80a5dd67ba56a1f26c0bc98a2a1eavboxsync            unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync            while (iPTE < RT_ELEMENTS(Walk.pPt->a))
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync            {
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync                GSTPTE Pte = Walk.pPt->a[iPTE];
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync                Pte.u = (Pte.u & (fMask | X86_PTE_PAE_PG_MASK_FULL))
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync                      | (fFlags & ~GST_PTE_PG_MASK);
b7a5b3f9f9ecce32ddacf8404c625ce0451bbdc1vboxsync                Walk.pPt->a[iPTE] = Pte;
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync                /* next page */
fe96bc0e43d9c137304462ef8c2d79cbff22446fvboxsync                cb -= PAGE_SIZE;
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync                if (!cb)
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync                    return VINF_SUCCESS;
e3f5c51715cbf77ae2d2e9d05bafd00d69b1bec9vboxsync                GCPtr += PAGE_SIZE;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync                iPTE++;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync            }
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        }
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        else
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        {
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync            /*
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync             * 2/4MB Page table
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync             */
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync            GSTPDE PdeNew;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# if PGM_GST_TYPE == PGM_TYPE_32BIT
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync            PdeNew.u = (Walk.Pde.u & (fMask | ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) | GST_PDE_BIG_PG_MASK | X86_PDE4M_PG_HIGH_MASK | X86_PDE4M_PS))
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# else
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync            PdeNew.u = (Walk.Pde.u & (fMask | ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) | GST_PDE_BIG_PG_MASK | X86_PDE4M_PS))
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# endif
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync                     | (fFlags & ~GST_PTE_PG_MASK)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync                     | ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync            *Walk.pPde = PdeNew;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync            /* advance */
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync            const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
97dc0e92bcc0cddf896cbf620b689b095c7346davboxsync            if (cbDone >= cb)
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync                return VINF_SUCCESS;
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync            cb    -= cbDone;
97dc0e92bcc0cddf896cbf620b689b095c7346davboxsync            GCPtr += cbDone;
97dc0e92bcc0cddf896cbf620b689b095c7346davboxsync        }
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync    }
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync#else
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync    /* real / protected mode: ignore. */
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync    return VINF_SUCCESS;
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync#endif
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync}
914d33aebb63d8c288dfd1b7e74f8e2acf3eaa66vboxsync
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync
97dc0e92bcc0cddf896cbf620b689b095c7346davboxsync/**
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync * Retrieve guest PDE information.
548ca31b6b47c36bacce49bed3339cb8075b9681vboxsync *
97dc0e92bcc0cddf896cbf620b689b095c7346davboxsync * @returns VBox status code.
97dc0e92bcc0cddf896cbf620b689b095c7346davboxsync * @param   pVCpu       The VMCPU handle.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @param   GCPtr       Guest context pointer.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @param   pPDE        Pointer to guest PDE structure.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync */
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsyncPGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE)
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync{
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT \
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync || PGM_GST_TYPE == PGM_TYPE_PAE   \
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync || PGM_GST_TYPE == PGM_TYPE_AMD64
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# if PGM_GST_TYPE != PGM_TYPE_AMD64
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    /* Boundary check. */
ad77e3ec3cde24263bc7537575f5cae442bee3b1vboxsync    if (RT_UNLIKELY(GCPtr >= _4G))
ad77e3ec3cde24263bc7537575f5cae442bee3b1vboxsync        return VERR_PAGE_TABLE_NOT_PRESENT;
ad77e3ec3cde24263bc7537575f5cae442bee3b1vboxsync# endif
ad77e3ec3cde24263bc7537575f5cae442bee3b1vboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# if PGM_GST_TYPE == PGM_TYPE_32BIT
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    unsigned    iPd = (GCPtr >> GST_PD_SHIFT) & GST_PD_MASK;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    PX86PD      pPd = pgmGstGet32bitPDPtr(pVCpu);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# elif PGM_GST_TYPE == PGM_TYPE_PAE
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    unsigned    iPd = 0;                /* shut up gcc */
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    PCX86PDPAE  pPd = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPd, NULL);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync# elif PGM_GST_TYPE == PGM_TYPE_AMD64
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    PX86PML4E   pPml4eIgn;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    X86PDPE     PdpeIgn;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    unsigned    iPd = 0;                /* shut up gcc */
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    PCX86PDPAE  pPd = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eIgn, &PdpeIgn, &iPd);
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    /* Note! We do not return an effective PDE here like we do for the PTE in GetPage method. */
ad77e3ec3cde24263bc7537575f5cae442bee3b1vboxsync# endif
ad77e3ec3cde24263bc7537575f5cae442bee3b1vboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    if (RT_LIKELY(pPd))
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        pPDE->u = (X86PGPAEUINT)pPd->a[iPd].u;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    else
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync        pPDE->u = 0;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    return VINF_SUCCESS;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync#else
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    AssertFailed();
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync    return VERR_NOT_IMPLEMENTED;
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync#endif
cba6719bd64ec749967bbe931230452664109857vboxsync}
cba6719bd64ec749967bbe931230452664109857vboxsync
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync
ad77e3ec3cde24263bc7537575f5cae442bee3b1vboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT \
cba6719bd64ec749967bbe931230452664109857vboxsync || PGM_GST_TYPE == PGM_TYPE_PAE \
ad77e3ec3cde24263bc7537575f5cae442bee3b1vboxsync || PGM_GST_TYPE == PGM_TYPE_AMD64
cba6719bd64ec749967bbe931230452664109857vboxsync/**
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * Updates one virtual handler range.
cba6719bd64ec749967bbe931230452664109857vboxsync *
cba6719bd64ec749967bbe931230452664109857vboxsync * @returns 0
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @param   pNode   Pointer to a PGMVIRTHANDLER.
5b1d6bab9f4cf5dacf1883e7c4a40c84349f597fvboxsync * @param   pvUser  Pointer to a PGMVHUARGS structure (see PGM.cpp).
 */
static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
{
    PPGMVIRTHANDLER pCur   = (PPGMVIRTHANDLER)pNode;
    PPGMHVUSTATE    pState = (PPGMHVUSTATE)pvUser;
    PVM             pVM    = pState->pVM;
    PVMCPU          pVCpu  = pState->pVCpu;
    Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);

# if PGM_GST_TYPE == PGM_TYPE_32BIT
    PX86PD          pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
# endif

    RTGCPTR         GCPtr  = pCur->Core.Key;
# if PGM_GST_TYPE != PGM_TYPE_AMD64
    /* skip all stuff above 4GB if not AMD64 mode. */
    if (RT_UNLIKELY(GCPtr >= _4G))
        return 0;
# endif

    unsigned        offPage = GCPtr & PAGE_OFFSET_MASK;
    unsigned        iPage = 0;
    while (iPage < pCur->cPages)
    {
# if PGM_GST_TYPE == PGM_TYPE_32BIT
        X86PDE      Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
# elif PGM_GST_TYPE == PGM_TYPE_PAE
        X86PDEPAE   Pde = pgmGstGetPaePDE(pVCpu, GCPtr);
# elif PGM_GST_TYPE == PGM_TYPE_AMD64
        X86PDEPAE   Pde = pgmGstGetLongModePDE(pVCpu, GCPtr);
# endif
# if PGM_GST_TYPE == PGM_TYPE_32BIT
        bool const  fBigPage = Pde.b.u1Size && (pState->cr4 & X86_CR4_PSE);
# else
        bool const  fBigPage = Pde.b.u1Size;
# endif
        if (    Pde.n.u1Present
            &&  (  !fBigPage
                 ? GST_IS_PDE_VALID(pVCpu, Pde)
                 : GST_IS_BIG_PDE_VALID(pVCpu, Pde)) )
        {
            if (!fBigPage)
            {
                /*
                 * Normal page table.
                 */
                PGSTPT pPT;
                int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(Pde), &pPT);
                if (RT_SUCCESS(rc))
                {
                    for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
                         iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
                         iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
                    {
                        GSTPTE      Pte = pPT->a[iPTE];
                        RTGCPHYS    GCPhysNew;
                        if (Pte.n.u1Present)
                            GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
                        else
                            GCPhysNew = NIL_RTGCPHYS;
                        if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
                        {
                            if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
                                pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
                            AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
                                             ("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
                                              pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
                                              pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
#endif
                            pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
                            pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
                        }
                    }
                }
                else
                {
                    /* not-present. */
                    offPage = 0;
                    AssertRC(rc);
                    for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
                         iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
                         iPTE++, iPage++, GCPtr += PAGE_SIZE)
                    {
                        if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
                        {
                            pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
                            AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
                                             ("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
                                              pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
                                              pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
#endif
                            pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
                            pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
                        }
                    }
                }
            }
            else
            {
                /*
                 * 2/4MB page.
                 */
                RTGCPHYS GCPhys = (RTGCPHYS)GST_GET_PDE_GCPHYS(Pde);
                for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
                     i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
                     i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
                {
                    RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
                    if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
                    {
                        if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
                            pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
                        AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
                                         ("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
                                          pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
                                          pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
#endif
                        pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
                        pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
                    }
                }
            } /* pde type */
        }
        else
        {
            /* not-present / invalid. */
            Log(("VirtHandler: Not present / invalid Pde=%RX64\n", (uint64_t)Pde.u));
            for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
                 cPages && iPage < pCur->cPages;
                 iPage++, GCPtr += PAGE_SIZE)
            {
                if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
                {
                    pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
                    pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
                    pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
                }
            }
            offPage = 0;
        }
    } /* for pages in virtual mapping. */

    return 0;
}
#endif /* 32BIT, PAE and AMD64 */


/**
 * Updates the virtual page access handlers.
 *
 * @returns true if bits were flushed.
 * @returns false if bits weren't flushed.
 * @param   pVM     VM handle.
 * @param   pPDSrc  The page directory.
 * @param   cr4     The cr4 register value.
 */
PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
{
#if PGM_GST_TYPE == PGM_TYPE_32BIT \
 || PGM_GST_TYPE == PGM_TYPE_PAE \
 || PGM_GST_TYPE == PGM_TYPE_AMD64

    /** @todo
     * In theory this is not sufficient: the guest can change a single page in a range with invlpg
     */

    /*
     * Resolve any virtual address based access handlers to GC physical addresses.
     * This should be fairly quick.
     */
    RTUINT      fTodo = 0;

    pgmLock(pVM);
    STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);

    for (VMCPUID i = 0; i < pVM->cCpus; i++)
    {
        PGMHVUSTATE State;
        PVMCPU      pVCpu = &pVM->aCpus[i];

        State.pVM   = pVM;
        State.pVCpu = pVCpu;
        State.fTodo = pVCpu->pgm.s.fSyncFlags;
        State.cr4   = cr4;
        RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);

        fTodo |= State.fTodo;
    }
    STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);


    /*
     * Set / reset bits?
     */
    if (fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
    {
        STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
        Log(("HandlerVirtualUpdate: resets bits\n"));
        RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);

        for (VMCPUID i = 0; i < pVM->cCpus; i++)
        {
            PVMCPU pVCpu = &pVM->aCpus[i];
            pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
        }

        STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
    }
    pgmUnlock(pVM);

    return !!(fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);

#else /* real / protected */
    return false;
#endif
}