PGMAllGst.h revision 5d46374ccbed9c443b45deacc8c3f4b09df96a40
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/* $Id$ */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/** @file
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * VBox - Page Manager, Guest Paging Template - All context code.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * available from http://www.virtualbox.org. This file is free software;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * you can redistribute it and/or modify it under the terms of the GNU
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * General Public License (GPL) as published by the Free Software
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * additional information or have any questions.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/*******************************************************************************
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync* Defined Constants And Macros *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync*******************************************************************************/
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GSTPT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef PGSTPT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GSTPTE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef PGSTPTE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GSTPD
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef PGSTPD
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GSTPDE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef PGSTPDE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_BIG_PAGE_SIZE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_BIG_PAGE_OFFSET_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_PDE_PG_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_PDE_BIG_PG_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_PD_SHIFT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_PD_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_PTE_PG_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_PT_SHIFT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_PT_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_TOTAL_PD_ENTRIES
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_CR3_PAGE_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_PDPE_ENTRIES
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_PDPT_SHIFT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_PDPT_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef GST_PDPE_PG_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_REAL \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_PROT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GSTPT X86PT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define PGSTPT PX86PT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GSTPTE X86PTE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define PGSTPTE PX86PTE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GSTPD X86PD
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define PGSTPD PX86PD
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GSTPDE X86PDE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define PGSTPDE PX86PDE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PDE_PG_MASK X86_PDE_PG_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PD_SHIFT X86_PD_SHIFT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PD_MASK X86_PD_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PTE_PG_MASK X86_PTE_PG_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PT_SHIFT X86_PT_SHIFT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PT_MASK X86_PT_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#elif PGM_GST_TYPE == PGM_TYPE_PAE \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GSTPT X86PTPAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define PGSTPT PX86PTPAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GSTPTE X86PTEPAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define PGSTPTE PX86PTEPAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GSTPD X86PDPAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define PGSTPD PX86PDPAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GSTPDE X86PDEPAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define PGSTPDE PX86PDEPAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PD_SHIFT X86_PD_PAE_SHIFT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PD_MASK X86_PD_PAE_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# if PGM_GST_TYPE == PGM_TYPE_PAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PDPT_SHIFT X86_PDPT_SHIFT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PDPT_MASK X86_PDPT_MASK_PAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PDPT_SHIFT X86_PDPT_SHIFT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_CR3_PAGE_MASK X86_CR3_AMD64_PAGE_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PT_SHIFT X86_PT_PAE_SHIFT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# define GST_PT_MASK X86_PT_PAE_MASK
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/*******************************************************************************
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync* Internal Functions *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync*******************************************************************************/
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync__BEGIN_DECLS
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, UnmapCR3)(PVM pVM);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#ifndef IN_RING3
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# if PGM_GST_TYPE == PGM_TYPE_PAE \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync__END_DECLS
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/**
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Gets effective Guest OS page information.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * When GCPtr is in a big page, the function will return as if it was a normal
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * 4KB page. If the need for distinguishing between big and normal page becomes
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * necessary at a later point, a PGMGstGetPage Ex() will be created for that
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * purpose.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @returns VBox status.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pVM VM Handle.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param GCPtr Guest Context virtual address of the page. Page aligned!
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pGCPhys Where to store the GC physical address of the page.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * This is page aligned. The fact that the
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync{
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_TYPE == PGM_TYPE_REAL \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_PROT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Fake it.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pfFlags)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *pfFlags = X86_PTE_P | X86_PTE_RW | X86_PTE_US;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pGCPhys)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VINF_SUCCESS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#elif PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Get the PDE.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# if PGM_GST_TYPE == PGM_TYPE_32BIT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#elif PGM_GST_TYPE == PGM_TYPE_PAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync X86PDEPAE Pde;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#elif PGM_GST_TYPE == PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PX86PML4E pPml4e;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync X86PDPE Pdpe;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync X86PDEPAE Pde;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(pPml4e);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VERR_PAGE_TABLE_NOT_PRESENT;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* Merge accessed, write, user and no-execute bits into the PDE. */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Lookup the page.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (!Pde.n.u1Present)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VERR_PAGE_TABLE_NOT_PRESENT;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if ( !Pde.b.u1Size
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# if PGM_GST_TYPE != PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync )
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PGSTPT pPT;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (VBOX_FAILURE(rc))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return rc;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Get PT entry and check presence.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (!Pte.n.u1Present)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VERR_PAGE_NOT_PRESENT;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Store the result.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * where the PDPE is simplified.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pfFlags)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync & ((Pde.u & (X86_PTE_RW | X86_PTE_US)) | ~(uint64_t)(X86_PTE_RW | X86_PTE_US));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# if PGM_WITH_NX(PGM_GST_TYPE)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* The NX bit is determined by a bitwise OR between the PT and PD */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (fNoExecuteBitValid)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *pfFlags |= (Pte.u & Pde.u & X86_PTE_PAE_NX);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pGCPhys)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *pGCPhys = Pte.u & GST_PTE_PG_MASK;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Map big to 4k PTE and store the result
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pfFlags)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *pfFlags = (Pde.u & ~(GST_PTE_PG_MASK | X86_PTE_PAT))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync | ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# if PGM_WITH_NX(PGM_GST_TYPE)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* The NX bit is determined by a bitwise OR between the PT and PD */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (fNoExecuteBitValid)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *pfFlags |= (Pde.u & X86_PTE_PAE_NX);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pGCPhys)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *pGCPhys = (Pde.u & GST_PDE_BIG_PG_MASK) | (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK)); /** @todo pse36 */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VINF_SUCCESS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# error "shouldn't be here!"
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* something else... */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VERR_NOT_SUPPORTED;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync}
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/**
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Modify page flags for a range of pages in the guest's tables
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * The existing flags are ANDed with the fMask and ORed with the fFlags.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @returns VBox status code.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pVM VM handle.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param GCPtr Virtual address of the first page in the range. Page aligned!
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param fMask The AND mask - page flags X86_PTE_*.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync{
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_PAE \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync for (;;)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Get the PD entry.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# if PGM_GST_TYPE == PGM_TYPE_32BIT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# elif PGM_GST_TYPE == PGM_TYPE_PAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(pPde);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (!pPde)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VERR_PAGE_TABLE_NOT_PRESENT;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# elif PGM_GST_TYPE == PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(pPde);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (!pPde)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VERR_PAGE_TABLE_NOT_PRESENT;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif
e04781b223e38e3b0c386d7e7c1dd7f30e9f6e90vboxsync GSTPDE Pde = *pPde;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(Pde.n.u1Present);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (!Pde.n.u1Present)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VERR_PAGE_TABLE_NOT_PRESENT;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if ( !Pde.b.u1Size
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# if PGM_GST_TYPE != PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync )
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
e04781b223e38e3b0c386d7e7c1dd7f30e9f6e90vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * 4KB Page table
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Walk page tables and pages till we're done.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PGSTPT pPT;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (VBOX_FAILURE(rc))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return rc;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync while (iPTE < RT_ELEMENTS(pPT->a))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync GSTPTE Pte = pPT->a[iPTE];
e04781b223e38e3b0c386d7e7c1dd7f30e9f6e90vboxsync Pte.u = (Pte.u & (fMask | X86_PTE_PAE_PG_MASK))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync | (fFlags & ~GST_PTE_PG_MASK);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pPT->a[iPTE] = Pte;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* next page */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync cb -= PAGE_SIZE;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (!cb)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VINF_SUCCESS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync GCPtr += PAGE_SIZE;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync iPTE++;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * 4MB Page table
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Pde.u = (Pde.u & (fMask | ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) | GST_PDE_BIG_PG_MASK | X86_PDE4M_PS)) /** @todo pse36 */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync | (fFlags & ~GST_PTE_PG_MASK)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync | ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *pPde = Pde;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* advance */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (cbDone >= cb)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VINF_SUCCESS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync cb -= cbDone;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync GCPtr += cbDone;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* real / protected mode: ignore. */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VINF_SUCCESS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync}
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/**
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Retrieve guest PDE information
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @returns VBox status code.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pVM The virtual machine.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param GCPtr Guest context pointer
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pPDE Pointer to guest PDE structure
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync{
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_PAE \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# if PGM_GST_TYPE == PGM_TYPE_32BIT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync X86PDE Pde;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# elif PGM_GST_TYPE == PGM_TYPE_PAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync X86PDEPAE Pde;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# elif PGM_GST_TYPE == PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync X86PDEPAE Pde;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pPDE->u = (X86PGPAEUINT)Pde.u;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VINF_SUCCESS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertFailed();
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VERR_NOT_IMPLEMENTED;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync}
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/**
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Maps the CR3 into HMA in GC and locate it in HC.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @returns VBox status, no specials.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pVM VM handle.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param GCPhysCR3 The physical address in the CR3 register.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync{
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_PAE \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync LogFlow(("MapCR3: %VGp\n", GCPhysCR3));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Map the page CR3 points at.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync RTHCPHYS HCPhysGuestCR3;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync RTHCPTR HCPtrGuestCR3;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (VBOX_SUCCESS(rc))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (VBOX_SUCCESS(rc))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# if PGM_GST_TYPE == PGM_TYPE_32BIT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
e04781b223e38e3b0c386d7e7c1dd7f30e9f6e90vboxsync pVM->pgm.s.pGuestPDGC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# elif PGM_GST_TYPE == PGM_TYPE_PAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync unsigned offset = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT)) HCPtrGuestCR3;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pGstPaePDPTGC = (RCPTRTYPE(PX86PDPT)) ((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + offset);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Log(("Cached mapping %VGv\n", pVM->pgm.s.pGstPaePDPTGC));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Map the 4 PDs too.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].n.u1Present)
e04781b223e38e3b0c386d7e7c1dd7f30e9f6e90vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync RTHCPTR HCPtr;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync RTHCPHYS HCPhys;
e04781b223e38e3b0c386d7e7c1dd7f30e9f6e90vboxsync RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (VBOX_SUCCESS(rc2))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertRCReturn(rc, rc);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.apGstPaePDsHC[i] = (R3R0PTRTYPE(PX86PDPAE))HCPtr;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.apGstPaePDsGC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PGM_INVL_PG(GCPtr);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync continue;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.apGstPaePDsHC[i] = 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.apGstPaePDsGC[i] = 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PGM_INVL_PG(GCPtr);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# elif PGM_GST_TYPE == PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pGstPaePML4HC = (R3R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (!HWACCMIsNestedPagingActive(pVM))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pVM->pgm.s.pHCShwAmd64CR3)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pgmPoolFreeByPage(pPool, pVM->pgm.s.pHCShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pHCShwAmd64CR3->GCPhys >> PAGE_SHIFT);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pHCShwAmd64CR3 = 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.pHCShwAmd64CR3);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (rc == VERR_PGM_POOL_FLUSHED)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertFailed(); /* check if we handle this properly!! */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VINF_PGM_SYNC_CR3;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pHCPaePML4 = (PX86PML4)PGMPOOL_PAGE_2_PTR(pPool->CTXSUFF(pVM), pVM->pgm.s.pHCShwAmd64CR3);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.HCPhysPaePML4 = pVM->pgm.s.pHCShwAmd64CR3->Core.Key;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#else /* prot/real stub */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync int rc = VINF_SUCCESS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return rc;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync}
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/**
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Unmaps the CR3.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @returns VBox status, no specials.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pVM VM handle.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param GCPhysCR3 The physical address in the CR3 register.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, UnmapCR3)(PVM pVM)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync{
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync LogFlow(("UnmapCR3\n"));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync int rc = VINF_SUCCESS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pGuestPDHC = 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pGuestPDGC = 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#elif PGM_GST_TYPE == PGM_TYPE_PAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pGstPaePDPTHC = 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pGstPaePDPTGC = 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync for (unsigned i=0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.apGstPaePDsHC[i] = 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.apGstPaePDsGC[i] = 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#elif PGM_GST_TYPE == PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pGstPaePML4HC = 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (!HWACCMIsNestedPagingActive(pVM))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pHCPaePML4 = 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pVM->pgm.s.pHCShwAmd64CR3)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pgmPoolFreeByPage(pPool, pVM->pgm.s.pHCShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pHCShwAmd64CR3->GCPhys >> PAGE_SHIFT);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pHCShwAmd64CR3 = NULL;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#else /* prot/real mode stub */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* nothing to do */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return rc;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync}
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef LOG_GROUP
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#define LOG_GROUP LOG_GROUP_PGM_POOL
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/**
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Registers physical page monitors for the necessary paging
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * structures to detect conflicts with our guest mappings.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * This is always called after mapping CR3.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * This is never called with fixed mappings.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @returns VBox status, no specials.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pVM VM handle.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param GCPhysCR3 The physical address in the CR3 register.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync{
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(!pVM->pgm.s.fMappingsFixed);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync int rc = VINF_SUCCESS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Register/Modify write phys handler for guest's CR3 if it changed.
e04781b223e38e3b0c386d7e7c1dd7f30e9f6e90vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# ifndef PGMPOOL_WITH_MIXED_PT_CR3
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pfnGCGstWriteHandlerCR3, 0,
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.pszR3GstWriteHandlerCR3);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.enmShadowMode == PGMMODE_PAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync ? PGMPOOL_IDX_PAE_PD
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync : PGMPOOL_IDX_PD,
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync GCPhysCR3);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (VBOX_FAILURE(rc))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return rc;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
6a3eee2950400e0aa97b20b906e679ea4a6e366cvboxsync pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#elif PGM_GST_TYPE == PGM_TYPE_PAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* Monitor the PDPT page */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Register/Modify write phys handler for guest's CR3 if it changed.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# ifndef PGMPOOL_WITH_MIXED_PT_CR3
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertFailed();
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif
6594fa9834a20895966c8226893b08f5273c5d4dvboxsync if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
6594fa9834a20895966c8226893b08f5273c5d4dvboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (VBOX_FAILURE(rc))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
e04781b223e38e3b0c386d7e7c1dd7f30e9f6e90vboxsync return rc;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Do the 4 PDs.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync RTGCPHYS GCPhys = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
600c8d4d6ed27e47f2b365cbf0db7a1f198608f3vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (VBOX_FAILURE(rc))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return rc;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertRC(rc);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* prot/real/amd64 mode stub */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
6a3eee2950400e0aa97b20b906e679ea4a6e366cvboxsync#endif
6594fa9834a20895966c8226893b08f5273c5d4dvboxsync return rc;
6a3eee2950400e0aa97b20b906e679ea4a6e366cvboxsync}
6594fa9834a20895966c8226893b08f5273c5d4dvboxsync
6594fa9834a20895966c8226893b08f5273c5d4dvboxsync/**
6594fa9834a20895966c8226893b08f5273c5d4dvboxsync * Deregisters any physical page monitors installed by MonitorCR3.
6594fa9834a20895966c8226893b08f5273c5d4dvboxsync *
6594fa9834a20895966c8226893b08f5273c5d4dvboxsync * @returns VBox status code, no specials.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pVM The VM handle.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync{
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync int rc = VINF_SUCCESS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Deregister the access handlers.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * before we enter GC again.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# ifndef PGMPOOL_WITH_MIXED_PT_CR3
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertRCReturn(rc, rc);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.enmShadowMode == PGMMODE_PAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync ? PGMPOOL_IDX_PAE_PD
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync : PGMPOOL_IDX_PD);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertRCReturn(rc, rc);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#elif PGM_GST_TYPE == PGM_TYPE_PAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* The PDPT page */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# ifndef PGMPOOL_WITH_MIXED_PT_CR3
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertFailed();
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertRC(rc);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* The 4 PDs. */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertRC(rc2);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (VBOX_FAILURE(rc2))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = rc2;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* prot/real/amd64 mode stub */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return rc;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync}
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#undef LOG_GROUP
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#define LOG_GROUP LOG_GROUP_PGM
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_PAE \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/**
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Updates one virtual handler range.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @returns 0
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pNode Pointer to a PGMVIRTHANDLER.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncstatic DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync{
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->GCPtr;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_MODE != PGM_MODE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* skip all stuff above 4GB if not AMD64 mode. */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (GCPtr >= _4GB)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync unsigned iPage = 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync while (iPage < pCur->cPages)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#elif PGM_GST_TYPE == PGM_TYPE_PAE
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync X86PDEPAE Pde;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#elif PGM_GST_TYPE == PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync X86PDEPAE Pde;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Pde.u = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (Pde.n.u1Present)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if ( !Pde.b.u1Size
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# if PGM_GST_TYPE != PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || !(pState->cr4 & X86_CR4_PSE)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync# endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync )
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Normal page table.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PGSTPT pPT;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (VBOX_SUCCESS(rc))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync GSTPTE Pte = pPT->a[iPTE];
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync RTGCPHYS GCPhysNew;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (Pte.n.u1Present)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync GCPhysNew = NIL_RTGCPHYS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync ("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* not-present. */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync offPage = 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertRC(rc);
e04781b223e38e3b0c386d7e7c1dd7f30e9f6e90vboxsync for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync iPTE++, iPage++, GCPtr += PAGE_SIZE)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync ("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * 2/4MB page.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync ("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync } /* pde type */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /* not-present. */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync cPages && iPage < pCur->cPages;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync iPage++, GCPtr += PAGE_SIZE)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync offPage = 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync } /* for pages in virtual mapping. */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return 0;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync}
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif /* 32BIT, PAE and AMD64 */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/**
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Updates the virtual page access handlers.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @returns true if bits were flushed.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @returns false if bits weren't flushed.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pVM VM handle.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pPDSrc The page directory.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param cr4 The cr4 register value.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync{
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_PAE \
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || PGM_GST_TYPE == PGM_TYPE_AMD64
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /** @todo
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * In theory this is not sufficient: the guest can change a single page in a range with invlpg
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Resolve any virtual address based access handlers to GC physical addresses.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * This should be fairly quick.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PGMHVUSTATE State;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pgmLock(pVM);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync State.pVM = pVM;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync State.fTodo = pVM->pgm.s.fSyncFlags;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync State.cr4 = cr4;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Set / reset bits?
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pgmUnlock(pVM);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#else /* real / protected */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return false;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync}
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/**
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Write access handler for the Guest CR3 page in 32-bit mode.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * This will try interpret the instruction, if failure fail back to the recompiler.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Check if the changed PDEs are marked present and conflicts with our
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * mappings. If conflict, we'll switch to the host context and resolve it there
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @returns VBox status code (appropritate for trap handling and GC return).
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pVM VM Handle.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param uErrorCode CPU Error code.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pRegFrame Trap register frame.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pvFault The fault address (cr2).
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param GCPhysFault The GC physical address corresponding to pvFault.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pvUser User argument.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync{
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Try interpret the instruction.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync uint32_t cb;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (VBOX_SUCCESS(rc) && cb)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Check if the modified PDEs are present and mappings.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync const unsigned iPD1 = offPD / sizeof(X86PDE);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(cb > 0 && cb <= 8);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(iPD1 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a)); /// @todo R3/R0 separation.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(iPD2 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#ifdef DEBUG
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD1, iPD1 << X86_PD_SHIFT));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (iPD1 != iPD2)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD2, iPD2 << X86_PD_SHIFT));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (!pVM->pgm.s.fMappingsFixed)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if ( ( pPDSrc->a[iPD1].n.u1Present
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync && pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || ( iPD1 != iPD2
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync && pPDSrc->a[iPD2].n.u1Present
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync && pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync )
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (rc == VINF_SUCCESS)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = VINF_PGM_SYNC_CR3;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return rc;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(VBOX_FAILURE(rc));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (rc == VERR_EM_INTERPRETER)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return rc;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync}
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif /* PGM_TYPE_32BIT && !IN_RING3 */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/**
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Write access handler for the Guest CR3 page in PAE mode.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * This will try interpret the instruction, if failure fail back to the recompiler.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Check if the changed PDEs are marked present and conflicts with our
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * mappings. If conflict, we'll switch to the host context and resolve it there
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @returns VBox status code (appropritate for trap handling and GC return).
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pVM VM Handle.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param uErrorCode CPU Error code.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pRegFrame Trap register frame.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pvFault The fault address (cr2).
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param GCPhysFault The GC physical address corresponding to pvFault.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pvUser User argument.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync{
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Try interpret the instruction.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync uint32_t cb;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (VBOX_SUCCESS(rc) && cb)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Check if any of the PDs have changed.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * We'll simply check all of them instead of figuring out which one/two to check.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync && ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync != pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * The PDPE has changed.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * We will schedule a monitoring update for the next TLB Flush,
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * InvalidatePage or SyncCR3.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * This isn't perfect, because a lazy page sync might be dealing with an half
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * updated PDPE. However, we assume that the guest OS is disabling interrupts
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * and being extremely careful (cmpxchg8b) when updating a PDPE where it's
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * executing.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync pVM->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%VGp\n",
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync i, CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(VBOX_FAILURE(rc));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (rc == VERR_EM_INTERPRETER)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return rc;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync}
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync/**
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Write access handler for the Guest PDs in PAE mode.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * This will try interpret the instruction, if failure fail back to the recompiler.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Check if the changed PDEs are marked present and conflicts with our
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * mappings. If conflict, we'll switch to the host context and resolve it there
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync *
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @returns VBox status code (appropritate for trap handling and GC return).
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pVM VM Handle.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param uErrorCode CPU Error code.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pRegFrame Trap register frame.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pvFault The fault address (cr2).
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param GCPhysFault The GC physical address corresponding to pvFault.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * @param pvUser User argument.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsyncPGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync{
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Try interpret the instruction.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync uint32_t cb;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (VBOX_SUCCESS(rc) && cb)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync /*
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync * Figure out which of the 4 PDs this is.
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync RTGCUINTPTR i;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(cb > 0 && cb <= 8);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(iPD1 < X86_PG_PAE_ENTRIES);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(iPD2 < X86_PG_PAE_ENTRIES);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#ifdef DEBUG
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%VGv)\n",
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync i, iPD1, (i << X86_PDPT_SHIFT) | (iPD1 << X86_PD_PAE_SHIFT)));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (iPD1 != iPD2)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%VGv)\n",
1d2d0112a43cf3bec74a2cf81134c215e9d1d72fvboxsync i, iPD2, (i << X86_PDPT_SHIFT) | (iPD2 << X86_PD_PAE_SHIFT)));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (!pVM->pgm.s.fMappingsFixed)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if ( ( pPDSrc->a[iPD1].n.u1Present
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync && pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) | (iPD1 << X86_PD_PAE_SHIFT))) )
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync || ( iPD1 != iPD2
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync && pPDSrc->a[iPD2].n.u1Present
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync && pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) | (iPD2 << X86_PD_PAE_SHIFT))) )
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync )
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return VINF_PGM_SYNC_CR3;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync break; /* ASSUMES no duplicate entries... */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(i < 4);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync {
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Assert(VBOX_FAILURE(rc));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync if (rc == VERR_EM_INTERPRETER)
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync else
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync }
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync return rc;
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync}
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync#endif /* PGM_TYPE_PAE && !IN_RING3 */
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync
97b634ea021fd984782256de4ba4ff31cdb96c47vboxsync