PGMAllBth.h revision 6b022885f2cb6a55167609edecd89570cd80001d
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * VBox - Page Manager, Shadow+Guest Paging Template - All context code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * This file is a big challenge!
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * available from http://www.virtualbox.org. This file is free software;
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * you can redistribute it and/or modify it under the terms of the GNU
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * General Public License (GPL) as published by the Free Software
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * additional information or have any questions.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync/*******************************************************************************
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync* Internal Functions *
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync*******************************************************************************/
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncPGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncPGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncPGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
7e960d3a0a8a3a84d7aba2cca45d72b1c31cc97bvboxsyncPGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncPGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncPGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncPGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncPGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsyncPGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncDECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# error "Invalid combination; PAE guest implies PAE shadow"
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#if (PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) \
223cf005b18af2c21352a70693ebaf0582f68ebcvboxsync && !(PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT)
223cf005b18af2c21352a70693ebaf0582f68ebcvboxsync# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE) \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && !(PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * #PF Handler for raw-mode guest execution.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code (appropriate for trap handling and GC return).
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM VM Handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param uErr The trap error code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pRegFrame Trap register frame.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pvFault The fault address.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncPGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64) \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && (PGM_SHW_TYPE != PGM_TYPE_EPT || PGM_GST_TYPE == PGM_TYPE_PROT)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Hide the instruction fetch trap indicator for now.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @todo NXE will change this and we must fix NXE in the switcher too! */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
22e281e75ed636601178296c6daebda8f1d17c59vboxsync# elif PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64
22e281e75ed636601178296c6daebda8f1d17c59vboxsync PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync /* Quick check for a valid guest trap. */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
22e281e75ed636601178296c6daebda8f1d17c59vboxsync LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%VGp\n", (int)(((RTGCUINTPTR)pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
22e281e75ed636601178296c6daebda8f1d17c59vboxsync LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%VGp\n", iPDSrc, CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
22e281e75ed636601178296c6daebda8f1d17c59vboxsync STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eGuestTrap; });
22e281e75ed636601178296c6daebda8f1d17c59vboxsync const unsigned iPDSrc = 0;
410f9d3ddfa779d92ca3662eb68fea60d314199avboxsync const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Did we mark the PDPT as not present in SyncCR3? */
726fc44ad0bd65a178ad4c3ab46ebd6cd3208e99vboxsync unsigned iPdpte = ((RTGCUINTPTR)pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (!pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present)
726fc44ad0bd65a178ad4c3ab46ebd6cd3208e99vboxsync pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present = 1;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* AMD-V nested paging */
726fc44ad0bd65a178ad4c3ab46ebd6cd3208e99vboxsync /* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
fdea543f71872a3ec3909536a4fce37ab7aa3a8bvboxsync Pml4eSrc.u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A;
726fc44ad0bd65a178ad4c3ab46ebd6cd3208e99vboxsync PdpeSrc.u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A;
fdea543f71872a3ec3909536a4fce37ab7aa3a8bvboxsync rc = PGMShwSyncLongModePDPtr(pVM, (RTGCUINTPTR)pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
726fc44ad0bd65a178ad4c3ab46ebd6cd3208e99vboxsync AssertReturn(rc == VINF_SUCCESS /* *must* test for VINF_SUCCESS!! */, rc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGMShwGetEPTPDPtr(pVM, (RTGCUINTPTR)pvFault, NULL, &pPDDst);
50df3da42ff6589b0ecc4f50f2288811bc370186vboxsync AssertReturn(rc == VINF_SUCCESS /* *must* test for VINF_SUCCESS!! */, rc);
726fc44ad0bd65a178ad4c3ab46ebd6cd3208e99vboxsync * If we successfully correct the write protection fault due to dirty bit
50df3da42ff6589b0ecc4f50f2288811bc370186vboxsync * tracking, or this page fault is a genuine one, then return immediately.
726fc44ad0bd65a178ad4c3ab46ebd6cd3208e99vboxsync STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
50df3da42ff6589b0ecc4f50f2288811bc370186vboxsync rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
50df3da42ff6589b0ecc4f50f2288811bc370186vboxsync STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
726fc44ad0bd65a178ad4c3ab46ebd6cd3208e99vboxsync STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
50df3da42ff6589b0ecc4f50f2288811bc370186vboxsync = rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
50df3da42ff6589b0ecc4f50f2288811bc370186vboxsync LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
726fc44ad0bd65a178ad4c3ab46ebd6cd3208e99vboxsync return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
726fc44ad0bd65a178ad4c3ab46ebd6cd3208e99vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
50df3da42ff6589b0ecc4f50f2288811bc370186vboxsync# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
26824086a3f6b36cd911058f1d9b4c0b944706fbvboxsync * A common case is the not-present error caused by lazy page table syncing.
68ef804c4ec232c58e2c03c8fc6afe3765c5c0d1vboxsync * It is IMPORTANT that we weed out any access to non-present shadow PDEs here
68ef804c4ec232c58e2c03c8fc6afe3765c5c0d1vboxsync * so we can safely assume that the shadow PT is present when calling SyncPage later.
50df3da42ff6589b0ecc4f50f2288811bc370186vboxsync * On failure, we ASSUME that SyncPT is out of memory or detected some kind
50df3da42ff6589b0ecc4f50f2288811bc370186vboxsync * of mapping conflict and defer to SyncCR3 in R3.
50df3da42ff6589b0ecc4f50f2288811bc370186vboxsync * (Again, we do NOT support access handlers for non-present guest pages.)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Check if this address is within any of our mappings.
a11c569636fa6838bd423f4631a9660a5a84204bvboxsync * This is *very* fast and it's gonna save us a bit of effort below and prevent
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * (BTW, it's impossible to have physical access handlers in a mapping.)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * The first thing we check is if we've got an undetected conflict.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync while (iPT-- > 0)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Check if the fault address is in a virtual page access handler range.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key);
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Pretend we're not here and let the guest handle the trap.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync } /* pgmAreMappingsEnabled(&pVM->pgm.s) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Check if this fault address is flagged for special treatment,
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * which means we'll have to figure out the physical address and
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * check flags associated with it.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * ASSUME that we can limit any special access handling to pages
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * in page tables which the guest believes to be present.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync | ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* No paging so the fault address is the physical address */
247b55faa8d054157f2481e68caca36f4dc9542cvboxsync GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync * If we have a GC address we'll check if it has any flags set.
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Physical page access handler.
22e281e75ed636601178296c6daebda8f1d17c59vboxsync const RTGCPHYS GCPhysFault = GCPhys | ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * If the region is write protected and we got a page not present fault, then sync
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * the pages. If the fault was caused by a read, then restart the instruction.
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync * In case of write access continue to the GC write handler.
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync * ASSUMES that there is only one handler per page or that they have similar write properties.
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync || (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync ("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
57399ab65e2825c324fb9dcb4642d4ae2c232509vboxsync rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
22e281e75ed636601178296c6daebda8f1d17c59vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
806d0b554daa555364af5f87bc96eccbe760db7avboxsync STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * If the region is write protected and we got a page not present fault, then sync
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * the pages. If the fault was caused by a read, then restart the instruction.
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * In case of write access continue to the GC write handler.
ebbb1f6c7e8bae363a4efda4b35b58c8467d24bcvboxsync if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
1843553dbdf4e46417158b4c6348c503adf10740vboxsync rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
1843553dbdf4e46417158b4c6348c503adf10740vboxsync STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * Ok, it's an virtual page access handler.
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * Since it's faster to search by address, we'll do that first
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * and then retry by GCPhys if that fails.
22e281e75ed636601178296c6daebda8f1d17c59vboxsync /** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
1843553dbdf4e46417158b4c6348c503adf10740vboxsync /** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
1843553dbdf4e46417158b4c6348c503adf10740vboxsync PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb)
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync || (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync ("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key);
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync /* Unhandled part of a monitored page */
0e77737b0ba913683e614db11463b31ca67aacbevboxsync /* Check by physical address. */
0e77737b0ba913683e614db11463b31ca67aacbevboxsync rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
2d53f6e472561965d363674e17f48d3bdffc24d3vboxsync Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->Core.Key & PAGE_OFFSET_MASK);
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
2d53f6e472561965d363674e17f48d3bdffc24d3vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync * There is a handled area of the page, but this fault doesn't belong to it.
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync * We must emulate the instruction.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync * we first check if this was a page-not-present fault for a page with only
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * write access handlers. Restart the instruction if it wasn't a write access.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync /** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
806d0b554daa555364af5f87bc96eccbe760db7avboxsync * It's writing to an unhandled part of the LDT page several million times.
806d0b554daa555364af5f87bc96eccbe760db7avboxsync rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
806d0b554daa555364af5f87bc96eccbe760db7avboxsync LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
806d0b554daa555364af5f87bc96eccbe760db7avboxsync PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
806d0b554daa555364af5f87bc96eccbe760db7avboxsync PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
806d0b554daa555364af5f87bc96eccbe760db7avboxsync STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
806d0b554daa555364af5f87bc96eccbe760db7avboxsync } /* if any kind of handler */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * The page isn't marked, but it might still be monitored by a virtual page access handler.
e08de24d4792d31b7f2aac29db5cb8840d940009vboxsync * (ASSUMES no temporary disabling of virtual handlers.)
806d0b554daa555364af5f87bc96eccbe760db7avboxsync /** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * we should correct both the shadow page table and physical memory flags, and not only check for
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync * accesses within the handler region but for access to pages with virtual handlers. */
806d0b554daa555364af5f87bc96eccbe760db7avboxsync PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb)
806d0b554daa555364af5f87bc96eccbe760db7avboxsync || (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync ("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb
806d0b554daa555364af5f87bc96eccbe760db7avboxsync rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key);
806d0b554daa555364af5f87bc96eccbe760db7avboxsync rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
806d0b554daa555364af5f87bc96eccbe760db7avboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
806d0b554daa555364af5f87bc96eccbe760db7avboxsync STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
7e960d3a0a8a3a84d7aba2cca45d72b1c31cc97bvboxsync /* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * back to the recompiler to emulate the instruction.
22e281e75ed636601178296c6daebda8f1d17c59vboxsync LogFlow(("pgmPhysGetPageEx %VGp failed with %Vrc\n", GCPhys, rc));
858aad6160628a88d8a273db0344fc3ba7dcc9abvboxsync * We are here only if page is present in Guest page tables and trap is not handled
65eb75d34c65a45c0945358715253950d63e440cvboxsync * by our handlers.
65eb75d34c65a45c0945358715253950d63e440cvboxsync * Check it for page out-of-sync situation.
d98e61ba075ed7d0b567a5d884bc85d643fe3de7vboxsync * Page is not present in our page tables.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Try to sync it!
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * BTW, fPageShw is invalid in this branch!
d98e61ba075ed7d0b567a5d884bc85d643fe3de7vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
d98e61ba075ed7d0b567a5d884bc85d643fe3de7vboxsync else /* supervisor */
d98e61ba075ed7d0b567a5d884bc85d643fe3de7vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
d98e61ba075ed7d0b567a5d884bc85d643fe3de7vboxsync Log(("Page out of sync: %VGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
d98e61ba075ed7d0b567a5d884bc85d643fe3de7vboxsync pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
22e281e75ed636601178296c6daebda8f1d17c59vboxsync# endif /* LOG_ENABLED */
da936e0446fb2b56b813d5d938f1dfc6e4bf8b13vboxsync# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
7e960d3a0a8a3a84d7aba2cca45d72b1c31cc97bvboxsync /* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
d98e61ba075ed7d0b567a5d884bc85d643fe3de7vboxsync || ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
d98e61ba075ed7d0b567a5d884bc85d643fe3de7vboxsync && CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
440444d68cda7866c59e2e3d3f236608ef1c316fvboxsync# endif /* CSAM_DETECT_NEW_CODE_PAGES */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * CSAM needs to perform a job in ring 3.
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync * Sync the page before going to the host context; otherwise we'll end up in a loop if
79b24ef0ab7cd4a03a3571b3954c52ab8b573137vboxsync * CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
22e281e75ed636601178296c6daebda8f1d17c59vboxsync int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
79b24ef0ab7cd4a03a3571b3954c52ab8b573137vboxsync STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
03319aeaef07ef63a404237f2cb56199131f4a03vboxsync && pRegFrame->ecx >= 0x100 /* early check for movswd count */
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsync /* In case of a write to a non-present supervisor shadow page, we'll take special precautions
5e797edc29f96c8367de4fbf5874171c24a89ba7vboxsync * to detect loading of new code pages.
8e8844a522f5d335f177a0313b03067d79cce201vboxsync * Decode the instruction.
7bae75e0b207aa4d4cad2a951271ad1a0e8ab9fdvboxsync rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
7bae75e0b207aa4d4cad2a951271ad1a0e8ab9fdvboxsync rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
5e797edc29f96c8367de4fbf5874171c24a89ba7vboxsync /* For now we'll restrict this to rep movsw/d instructions */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync# endif /* CSAM_DETECT_NEW_CODE_PAGES */
79b24ef0ab7cd4a03a3571b3954c52ab8b573137vboxsync * Mark this page as safe.
79b24ef0ab7cd4a03a3571b3954c52ab8b573137vboxsync /** @todo not correct for pages that contain both code and data!! */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync Log2(("CSAMMarkPage %VGv; scanned=%d\n", pvFault, true));
79b24ef0ab7cd4a03a3571b3954c52ab8b573137vboxsync# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
57399ab65e2825c324fb9dcb4642d4ae2c232509vboxsync /* The page was successfully synced, return to the guest. */
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
7bae75e0b207aa4d4cad2a951271ad1a0e8ab9fdvboxsync * A side effect of not flushing global PDEs are out of sync pages due
7bae75e0b207aa4d4cad2a951271ad1a0e8ab9fdvboxsync * to physical monitored regions, that are no longer valid.
9a12d720d4db6c26d09600ddab781ad8df5e1826vboxsync * Assume for now it only applies to the read/write flag
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
03319aeaef07ef63a404237f2cb56199131f4a03vboxsync else /* supervisor */
79b24ef0ab7cd4a03a3571b3954c52ab8b573137vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync * Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync * Page was successfully synced, return to guest.
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
22e281e75ed636601178296c6daebda8f1d17c59vboxsync AssertMsg(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Vrc fPageShw=%VX64\n", rc, fPageShw));
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync# endif /* VBOX_STRICT */
f9147fe1eaa4e35287f8f39282c7f92f0d7de0b7vboxsync STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
22e281e75ed636601178296c6daebda8f1d17c59vboxsync /* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync && ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP|X86_CR0_PG)) == X86_CR0_PG)
5cf54b3ffeb7ee90685dcaec329ef71a729f5947vboxsync && (uErr & (X86_TRAP_PF_RW | X86_TRAP_PF_P)) == (X86_TRAP_PF_RW | X86_TRAP_PF_P))
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync AssertMsgFailed(("Unexpected r/w page %x flag=%x\n", pvFault, (uint32_t)fPageGst));
f9147fe1eaa4e35287f8f39282c7f92f0d7de0b7vboxsync * Check for VMM page flags vs. Guest page flags consistency.
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync * Currently only for debug purposes.
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync /* Get guest page flags. */
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync * Compare page flags.
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync * Note: we have AVL, A, D bits desynched.
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync AssertMsg((fPageShw & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK)),
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync ("Page flags mismatch! pvFault=%VGv GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync# endif /* VBOX_STRICT */
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
f9147fe1eaa4e35287f8f39282c7f92f0d7de0b7vboxsync# endif /* PGM_OUT_OF_SYNC_IN_GC */
7e960d3a0a8a3a84d7aba2cca45d72b1c31cc97bvboxsync * Page not present in Guest OS or invalid page table address.
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync * This is potential virtual page access handler food.
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * For the present we'll say that our access handlers don't
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync * work for this case - we've already discarded the page table
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync * not present case which is identical to this.
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync * When we perchance find we need this, we will probably have AVL
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync * trees (offset based) to operate on and we can measure their speed
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * agains mapping a page table and probably rearrange this handling
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync * a bit. (Like, searching virtual ranges before checking the
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync * physical address.)
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync * Conclusion, this is a guest trap.
22e281e75ed636601178296c6daebda8f1d17c59vboxsync LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync /* present, but not a monitored page; perhaps the guest is probing physical memory */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync * Emulation of the invlpg instruction.
46df4404c8dbbf3672e7aae8cd0b2770356e5b73vboxsync * @returns VBox status code.
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * @param pVM VM handle.
35eac6afc99c1d18789ea5fe75379695aec478b9vboxsync * @param GCPtrPage Page to invalidate.
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * @remark ASSUMES that the guest is updating before invalidating. This order
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsync * isn't required by the CPU, so this is speculative and could cause
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsync * @todo Flush page or page directory only if necessary!
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * @todo Add a #define for simply invalidating the page.
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsyncPGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsync * Get the shadow PD entry and skip out if this PD isn't present.
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
46df4404c8dbbf3672e7aae8cd0b2770356e5b73vboxsync PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
46df4404c8dbbf3672e7aae8cd0b2770356e5b73vboxsync const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
46df4404c8dbbf3672e7aae8cd0b2770356e5b73vboxsync const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte);
5db1d52ffbcaa46c3d944c6c2d9c552306817d9avboxsync PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync /* If the shadow PDPE isn't present, then skip the invalidate. */
35eac6afc99c1d18789ea5fe75379695aec478b9vboxsync Assert(!(pPdptDst->a[iPdpte].u & PGM_PLXFLAGS_MAPPING));
22e281e75ed636601178296c6daebda8f1d17c59vboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync const unsigned iPml4e = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync PX86PML4E pPml4eDst = &pVM->pgm.s.pHCPaePML4->a[iPml4e];
e08de24d4792d31b7f2aac29db5cb8840d940009vboxsync rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Get the guest PD entry and calc big page.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# else /* AMD64 */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * If a CR3 Sync is pending we may ignore the invalidate page operation
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * depending on the kind of sync and if it's a global page or not.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * This doesn't make sense in GC/R0 so we'll skip it entirely there.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# endif /* IN_RING3 */
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync /* Fetch the pgm pool shadow descriptor. */
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync /* Fetch the pgm pool shadow descriptor. */
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & SHW_PDPE_PG_MASK);
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
49748bb305bd71f672cd083af208f4bb08c5d6abvboxsync LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %VGv GCPhys=%VGp vs %VGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Mark not present so we can resync the PML4E when it's used.
b9ca93dd1ad44cb8b27679dc5624be2f7b7f7af5vboxsync LogFlow(("InvalidatePage: Out-of-sync PML4E at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
b9ca93dd1ad44cb8b27679dc5624be2f7b7f7af5vboxsync GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
b9ca93dd1ad44cb8b27679dc5624be2f7b7f7af5vboxsync pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
b9ca93dd1ad44cb8b27679dc5624be2f7b7f7af5vboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
e9a217d585085a6a6d129d27ca0d96a1b8e6d0eevboxsync * Mark not present so we can set the accessed bit.
51d4024e2984de499ecd878341898f71f55cf9e0vboxsync LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
8b984478b755f4d3091b977d9beac9fb7434279fvboxsync GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
e9a217d585085a6a6d129d27ca0d96a1b8e6d0eevboxsync pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
e9a217d585085a6a6d129d27ca0d96a1b8e6d0eevboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Check if the PDPT entry has changed. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %VGv GCPhys=%VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Mark not present so we can resync the PDPTE when it's used.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("InvalidatePage: Out-of-sync PDPE at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Mark not present so we can set the accessed bit.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1a25adaca81841abf5e6cdfed02eaff64941357dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Note: This shouldn't actually be necessary as we monitor the PDPT page for changes. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Guest PDPE not present */
5b6e2c9a765c3c72295acc15791af8a700746956vboxsync PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* root of the 2048 PDE array */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpte * X86_PG_PAE_ENTRIES];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Assert(!(CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte].n.u1Present));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("InvalidatePage: guest PDPE %d not present; clear shw pdpe\n", iPdpte));
5b6e2c9a765c3c72295acc15791af8a700746956vboxsync /* for each page directory entry */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync for (unsigned iPD = 0; iPD < X86_PG_PAE_ENTRIES; iPD++)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpte * X86_PG_PAE_ENTRIES + iPD);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (!(pPdptDst->a[iPdpte].u & PGM_PLXFLAGS_MAPPING))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsg(pVM->pgm.s.fMappingsFixed || (PdpeSrc.u & X86_PDPE_PG_MASK) == pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpte], ("%VGp vs %VGp (mon)\n", (PdpeSrc.u & X86_PDPE_PG_MASK), pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpte]));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Deal with the Guest PDE.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Conflict - Let SyncPT deal with it to avoid duplicate code.
3123bb2477edc752585e4bbd8e4cfedaf87997d1vboxsync rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Mark not present so we can resync the PDE when it's used.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
0975ae0a0fb615c945150c48e4a73187c1f4f84dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
0975ae0a0fb615c945150c48e4a73187c1f4f84dvboxsync * Mark not present so we can set the accessed bit.
0975ae0a0fb615c945150c48e4a73187c1f4f84dvboxsync LogFlow(("InvalidatePage: Out-of-sync (A) at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
0975ae0a0fb615c945150c48e4a73187c1f4f84dvboxsync GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
78a205e3fc6719d59e8c561b3d287d3a4f879852vboxsync pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
7e960d3a0a8a3a84d7aba2cca45d72b1c31cc97bvboxsync pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
eb90d5a431eee79842fb6c676c05aa9ca51ca6a9vboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * 4KB - page.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* This is very unlikely with caching/monitoring enabled. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * The page table address changed.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
0975ae0a0fb615c945150c48e4a73187c1f4f84dvboxsync pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * 2/4MB - page.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Before freeing the page, check if anything really changed. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1a25adaca81841abf5e6cdfed02eaff64941357dvboxsync RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
47b5427d1a541bcd269bc625c35b19d849071edfvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
a11c569636fa6838bd423f4631a9660a5a84204bvboxsync && pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* ASSUMES a the given bits are identical for 4M and normal PDEs */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @todo PAT */
5cf54b3ffeb7ee90685dcaec329ef71a729f5947vboxsync if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync == (PdeDst.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("Skipping flush for big page containing %VGv (PD=%X .u=%VX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Ok, the page table is present and it's been changed in the guest.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * If we're in host context, we'll just mark it as not present taking the lazy approach.
5cf54b3ffeb7ee90685dcaec329ef71a729f5947vboxsync * We could do this for some flushes in GC too, but we need an algorithm for
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * deciding which 4MB pages containing code likely to be executed very soon.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("InvalidatePage: Out-of-sync PD at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Page directory is not present, mark shadow PDE not present.
b1c3cdef473df2fbc621d5da81acc82dbfb8a11avboxsync pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#else /* guest real and protected mode */
0f5d1b2abd9e82c7ee46f1327287c44856604bcbvboxsync /* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync * Update the tracking of shadowed pages.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pShwPage The shadow page.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param HCPhys The physical page we is being dereferenced.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncDECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @todo If this turns out to be a bottle neck (*very* likely) two things can be done:
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * 2. write protect all shadowed pages. I.e. implement caching.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Find the guest address.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync while (iPage-- > 0)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
0f5d1b2abd9e82c7ee46f1327287c44856604bcbvboxsync# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Update the tracking of shadowed pages.
0f5d1b2abd9e82c7ee46f1327287c44856604bcbvboxsync * @param pVM The VM handle.
0f5d1b2abd9e82c7ee46f1327287c44856604bcbvboxsync * @param pShwPage The shadow page.
5b6e2c9a765c3c72295acc15791af8a700746956vboxsync * @param u16 The top 16-bit of the pPage->HCPhys.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pPage Pointer to the guest page. this will be modified.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param iPTDst The index into the shadow table.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncDECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync * We're making certain assumptions about the placement of cRef and idx.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Just deal with the simple first time here.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) | pShwPage->idx;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* write back, trying to be clever... */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) | ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync *((uint16_t *)&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* update statistics. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#endif /* PGMPOOL_WITH_USER_TRACKING */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Creates a 4K shadow page for a guest page.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * physical address. The PdeSrc argument only the flags are used. No page structured
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * will be mapped in this function.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pPteDst Destination page table entry.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Can safely assume that only the flags are being used.
b1c3cdef473df2fbc621d5da81acc82dbfb8a11avboxsync * @param PteSrc Source page table entry (i.e. Guest OS page table entry).
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pShwPage Pointer to the shadow page.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param iPTDst The index into the shadow table.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @remark Not used for 2/4MB pages!
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncDECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Find the ram range.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @todo investiage PWT, PCD and PAT. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Make page table entry.
7e960d3a0a8a3a84d7aba2cca45d72b1c31cc97bvboxsync const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* PteDst.n.u1Write = 0 && PteDst.n.u1Big = 0 */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT | X86_PTE_RW))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @todo count these two kinds. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * If the page or page directory entry is not marked accessed,
8b03ab0bcd5c238021bc8a43d887dd9d0870c0f5vboxsync * we mark the page not present.
8b03ab0bcd5c238021bc8a43d887dd9d0870c0f5vboxsync LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
7e2fce486e7e2e45eb61d78ee206ba42ed89e016vboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
8b03ab0bcd5c238021bc8a43d887dd9d0870c0f5vboxsync * If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
8b03ab0bcd5c238021bc8a43d887dd9d0870c0f5vboxsync * when the page is modified.
8b03ab0bcd5c238021bc8a43d887dd9d0870c0f5vboxsync if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
8b03ab0bcd5c238021bc8a43d887dd9d0870c0f5vboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
8b03ab0bcd5c238021bc8a43d887dd9d0870c0f5vboxsync PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT | X86_PTE_RW))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* PteDst.n.u1Big = 0 */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Keep user track up to date.
e85d76a7e5a047db3cdc8576ff5f412c7b73bbabvboxsync PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
9b45880674da6f82ca27cc28b0272de3dd3cc7dfvboxsync else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
e85d76a7e5a047db3cdc8576ff5f412c7b73bbabvboxsync PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
e85d76a7e5a047db3cdc8576ff5f412c7b73bbabvboxsync PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
e85d76a7e5a047db3cdc8576ff5f412c7b73bbabvboxsync PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#endif /* PGMPOOL_WITH_USER_TRACKING */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Update statistics and commit the entry.
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync /* else MMIO or invalid page, we must handle them manually in the #PF handler. */
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync /** @todo count these. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Page not-present.
10e1bc06b2908a0af56d92ffdbadd25b36a5ef61vboxsync LogFlow(("SyncPageWorker: page not present in Pte\n"));
5db1d52ffbcaa46c3d944c6c2d9c552306817d9avboxsync /* Keep user track up to date. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
9b45880674da6f82ca27cc28b0272de3dd3cc7dfvboxsync PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync#endif /* PGMPOOL_WITH_USER_TRACKING */
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync /** @todo count these. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Syncs a guest OS page.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * There are no conflicts at this point, neither is there any need for
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * page table allocations.
10e1bc06b2908a0af56d92ffdbadd25b36a5ef61vboxsync * @returns VBox status code.
8f7bc6ad2b7bbcb4b3b96248cd2478e45f2e3b88vboxsync * @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
5db1d52ffbcaa46c3d944c6c2d9c552306817d9avboxsync * @param pVM VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param PdeSrc Page directory entry of the guest.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param GCPtrPage Guest context page address.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param uErr Fault error (X86_TRAP_PF_*).
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncPGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Assert preconditions.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Get the shadow PDE, find the shadow page table in the pool.
ec588a4ac8429a8b6c744544818b3ce3b2c75690vboxsync X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte); /* no mask; flat index into the 2048 entry array. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
afed5ab737f4aacfae3fe73776f40e989190a7cavboxsync /* Fetch the pgm pool shadow descriptor. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Check that the page is present and that the shadow PDE isn't out of sync.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1a25adaca81841abf5e6cdfed02eaff64941357dvboxsync /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && (PdeSrc.n.u1Write == PdeDst.n.u1Write || !PdeDst.n.u1Write)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && (!fNoExecuteBitValid || PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Check that the PDE is marked accessed already.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Since we set the accessed bit *before* getting here on a #PF, this
223cf005b18af2c21352a70693ebaf0582f68ebcvboxsync * check is only meant for dealing with non-#PF'ing paths.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * 4KB Page - Map the guest page table.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * This code path is currently only taken when the caller is PGMTrap0eHandler
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * for non-present pages!
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * deal with locality.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned offPTSrc = 0;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) | ((offPTSrc + iPTDst) << PAGE_SHIFT);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Assuming kernel code will be marked as supervisor - and not as user level
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * and executed using a conforming code selector - And marked as readonly.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Also assume that if we're monitoring a page, it's of no interest to CSAM.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW | X86_PTE_US))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#endif /* else: CSAM not active */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
c33db29e7b41467a35675031f5f5233839909083vboxsync# endif /* PGM_SYNC_N_PAGES */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync else /* MMIO or invalid page: emulated in #PF handler. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * 4/2MB page - lazy syncing shadow 4K pages.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * (There are many causes of getting here, it's no longer only CSAM.)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Calculate the GC physical address of this 4KB shadow page. */
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) | ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Find ram range. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Make shadow PTE entry.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * If the page is not flagged as dirty and is writable, then make it read-only
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * at PD level, so we can set the dirty bit when the page is modified.
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync * ASSUMES that page access handlers are implemented on page table entry level.
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync * Thus we will first catch the dirty access and set PDE.D and restart. If
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync * there is an access handler, we'll trap again and let it work on the problem.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
10e1bc06b2908a0af56d92ffdbadd25b36a5ef61vboxsync * As for invlpg, it simply frees the whole shadow PT.
8f7bc6ad2b7bbcb4b3b96248cd2478e45f2e3b88vboxsync * ...It's possibly because the guest clears it and the guest doesn't really tell us... */
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
75fca099c974cbbd48f132af1378c60232614760vboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
75fca099c974cbbd48f132af1378c60232614760vboxsync Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
75fca099c974cbbd48f132af1378c60232614760vboxsync GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Yea, I'm lazy.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#elif (PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && (PGM_SHW_TYPE != PGM_TYPE_EPT || PGM_GST_TYPE == PGM_TYPE_PROT)
c33db29e7b41467a35675031f5f5233839909083vboxsync * Get the shadow PDE, find the shadow page table in the pool.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
a27fbcbb29ffc2196c2ebd0f2dad92f40c7ec65dvboxsync const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
10e1bc06b2908a0af56d92ffdbadd25b36a5ef61vboxsync const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpte);
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = PGMShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertReturn(rc == VINF_SUCCESS /* *must* test for VINF_SUCCESS!! */, rc);
9b45880674da6f82ca27cc28b0272de3dd3cc7dfvboxsync PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
9b45880674da6f82ca27cc28b0272de3dd3cc7dfvboxsync PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * This code path is currently only taken when the caller is PGMTrap0eHandler
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * for non-present pages!
75fca099c974cbbd48f132af1378c60232614760vboxsync * We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
75fca099c974cbbd48f132af1378c60232614760vboxsync * deal with locality.
57f41f24b7a290eba73c63449f44017d7917561dvboxsync unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
a3db4ff1e0aa7f94c9176ef16264df572eec0aebvboxsync const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) | (iPTDst << PAGE_SHIFT);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Fake the page table entry */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log4(("%VGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) | (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# endif /* PGM_SYNC_N_PAGES */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
09d4e754a010196fe0d9d972b6ccc005ecb8b116vboxsync RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) | (iPTDst << PAGE_SHIFT);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Fake the page table entry */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
a27fbcbb29ffc2196c2ebd0f2dad92f40c7ec65dvboxsync * Investigate page fault and handle write protection page faults caused by
10e1bc06b2908a0af56d92ffdbadd25b36a5ef61vboxsync * dirty bit tracking.
5db1d52ffbcaa46c3d944c6c2d9c552306817d9avboxsync * @returns VBox status code.
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync * @param pVM VM handle.
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync * @param uErr Page fault error code.
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync * @param pPdeDst Shadow page directory entry.
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync * @param pPdeSrc Guest page directory entry.
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync * @param GCPtrPage Guest context page address.
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsyncPGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
7cced997f7e362bb903898de921271b5e1011e3dvboxsync bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
9b45880674da6f82ca27cc28b0272de3dd3cc7dfvboxsync bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
ec588a4ac8429a8b6c744544818b3ce3b2c75690vboxsync STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
75fca099c974cbbd48f132af1378c60232614760vboxsync LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync * Real page fault? (PML4E level)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault || fWriteProtect))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# else /* PAE */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDPE pPdpeSrc = &pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtrPage >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
6ee326f4243bcf103c001da26f5d914360b6d312vboxsync * Real page fault? (PDPE level)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
09d4e754a010196fe0d9d972b6ccc005ecb8b116vboxsync || (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault || fWriteProtect))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Real page fault? (PDE level)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault || fWriteProtect))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * First check the easy case where the page directory has been marked read-only to track
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * the dirty bit of an emulated BIG page
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Mark guest page directory as accessed */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Only write protection page faults are relevant here.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Mark guest page directory as dirty (BIG page only). */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* else: 4KB page table */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Map the guest page table.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Real page fault?
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault || fWriteProtect))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Check the present bit as the shadow tables can cause different error codes by being out of sync.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * See the 2nd case above as well.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync TRPMSetErrorCode(pVM, uErr | X86_TRAP_PF_P); /* page-level protection violation */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Set the accessed bits in the page directory and the page table.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Only write protection page faults are relevant here.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Write access, so mark guest entry as dirty. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Our individual shadow handlers will provide more information and force a fatal exit.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Map shadow page table.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync ("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync/** @todo Optimize accessed bit emulation? */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Sanity check.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# endif /* VBOX_STRICT */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Pagefault detected while checking the PML4E, PDPE or PDE.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Single exit handler to get rid of duplicate code paths.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("CheckPageFault: real page fault at %VGv (%d)\n", GCPtrPage, uPageFaultLevel));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync TRPMSetErrorCode(pVM, uErr | X86_TRAP_PF_P); /* page-level protection violation */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Map the guest page table.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync TRPMSetErrorCode(pVM, uErr | X86_TRAP_PF_P); /* page-level protection violation */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Sync a shadow page table.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * The shadow page table is not present. This includes the case where
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * there is a conflict with a mapping.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param iPD Page directory index.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pPDSrc Source page directory (i.e. Guest OS page directory).
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Assume this is a temporary mapping.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param GCPtrPage GC Pointer of the page that caused the fault
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncPGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Validate input a little bit.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%VGv\n", iPDSrc, GCPtrPage));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
9c425bdea5f0991df62922b1584b805a86f2f898vboxsync const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Fetch the pgm pool shadow descriptor. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Check for conflicts.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * HC: Simply resolve the conflict.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# else /* PGM_WITHOUT_MAPPINGS */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# endif /* PGM_WITHOUT_MAPPINGS */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Sync page directory entry.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Allocate & map the page table.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const bool fPageTable = !PdeSrc.b.u1Size || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
5dda7f07dab8a954e6c4cf2378b15f921e60d9aavboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
5dda7f07dab8a954e6c4cf2378b15f921e60d9aavboxsync /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
5dda7f07dab8a954e6c4cf2378b15f921e60d9aavboxsync rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
5dda7f07dab8a954e6c4cf2378b15f921e60d9aavboxsync rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
5dda7f07dab8a954e6c4cf2378b15f921e60d9aavboxsync pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
5dda7f07dab8a954e6c4cf2378b15f921e60d9aavboxsync * The PT was cached, just hook it up.
5dda7f07dab8a954e6c4cf2378b15f921e60d9aavboxsync | (PdeSrc.u & ~(GST_PDE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
26824086a3f6b36cd911058f1d9b4c0b944706fbvboxsync | (PdeSrc.u & ~(GST_PDE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
5dda7f07dab8a954e6c4cf2378b15f921e60d9aavboxsync /* (see explanation and assumptions further down.) */
5dda7f07dab8a954e6c4cf2378b15f921e60d9aavboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Page directory has been accessed (this is a fault situation, remember).
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Page table - 4KB.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
1a25adaca81841abf5e6cdfed02eaff64941357dvboxsync rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Start by syncing the page directory entry so CSAM's TLB trick works.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK | X86_PDE_AVL_MASK))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync | (PdeSrc.u & ~(GST_PDE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Directory/page user or supervisor privilege: (same goes for read/write)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Directory Page Combined
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * U/S U/S U/S
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Simple AND operation. Table listed for completeness.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
afed5ab737f4aacfae3fe73776f40e989190a7cavboxsync# else /* !PGM_SYNC_N_PAGES */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync unsigned iPTDst = 0;
32f98f3d0fb00168315b4ece1f0808df4cd88248vboxsync# endif /* !PGM_SYNC_N_PAGES */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2c080f6fc6ab70995d6390eeaa199d590c1a34d5vboxsync /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
8a132edc1577cbe2a19cd778c1b2bea6ae5e8515vboxsync const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
32f98f3d0fb00168315b4ece1f0808df4cd88248vboxsync const unsigned offPTSrc = 0;
32f98f3d0fb00168315b4ece1f0808df4cd88248vboxsync if (PteSrc.n.u1Present) /* we've already cleared it above */
32f98f3d0fb00168315b4ece1f0808df4cd88248vboxsync * Assuming kernel code will be marked as supervisor - and not as user level
32f98f3d0fb00168315b4ece1f0808df4cd88248vboxsync * and executed using a conforming code selector - And marked as readonly.
32f98f3d0fb00168315b4ece1f0808df4cd88248vboxsync * Also assume that if we're monitoring a page, it's of no interest to CSAM.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW | X86_PTE_US))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) | (iPTSrc << PAGE_SHIFT)))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1a25adaca81841abf5e6cdfed02eaff64941357dvboxsync PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync (RTGCPTR)((iPDSrc << GST_PD_SHIFT) | (iPTSrc << PAGE_SHIFT)),
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync (PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
32f98f3d0fb00168315b4ece1f0808df4cd88248vboxsync } /* for PTEs */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Big page - 2/4MB.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * We'll walk the ram range list in parallel and optimize lookups.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * We will only sync on shadow page table at a time.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Start by syncing the page directory entry.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK | (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
6b022885f2cb6a55167609edecd89570cd80001dvboxsync | (PdeSrc.u & ~(GST_PDE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * If the page is not flagged as dirty and is writable, then make it read-only
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * at PD level, so we can set the dirty bit when the page is modified.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * ASSUMES that page access handlers are implemented on page table entry level.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Thus we will first catch the dirty access and set PDE.D and restart. If
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * there is an access handler, we'll trap again and let it work on the problem.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @todo move the above stuff to a section in the PGM documentation. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Fill the shadow page table.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Get address and flags from the source PDE. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Loop thru the entries in the shadow PT. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync unsigned iPTDst = 0;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Advance ram range list. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
afed5ab737f4aacfae3fe73776f40e989190a7cavboxsync /* Make shadow PTE. */
907da3b41f191bef4c8eb94accb9d16fcbe77019vboxsync /* Make sure the RAM has already been allocated. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) | PteDstBase.u;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Assuming kernel code will be marked as supervisor and not as user level and executed
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * using a conforming code selector. Don't check for readonly, as that implies the whole
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * 4MB can be code or readonly data. Linux enables write access for its large pages.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT))))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) | PteDstBase.u;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* commit it */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* advance */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync } /* while more PTEs */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync } /* 4KB / 4MB */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#elif (PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && (PGM_SHW_TYPE != PGM_TYPE_EPT || PGM_GST_TYPE == PGM_TYPE_PROT)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Validate input a little bit.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
b1c3cdef473df2fbc621d5da81acc82dbfb8a11avboxsync rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Fetch the pgm pool shadow descriptor. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
19b725c530eb49600728765de7ed451cbe290740vboxsync const unsigned iPdpte = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGMShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
223cf005b18af2c21352a70693ebaf0582f68ebcvboxsync AssertReturn(rc == VINF_SUCCESS /* *must* test for VINF_SUCCESS!! */, rc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Fetch the pgm pool shadow descriptor. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync * Allocate & map the page table.
5db1d52ffbcaa46c3d944c6c2d9c552306817d9avboxsync /* Virtual address = physical address */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_EPT
8f7bc6ad2b7bbcb4b3b96248cd2478e45f2e3b88vboxsync rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
75fca099c974cbbd48f132af1378c60232614760vboxsync AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
19b725c530eb49600728765de7ed451cbe290740vboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync * Prefetch a page/set of pages.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Typically used to sync commonly used pages before entering raw mode
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync * after a CR3 reload.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync * @param pVM VM handle.
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync * @param GCPtrPage Page to invalidate.
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsyncPGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64) \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Check that all Guest levels thru the PDE are present, getting the
10e1bc06b2908a0af56d92ffdbadd25b36a5ef61vboxsync * PD and PDE in the processes.
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
9b45880674da6f82ca27cc28b0272de3dd3cc7dfvboxsync const unsigned iPDSrc = 0;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* AMD-V nested paging */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Pml4eSrc.u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_NX | X86_PML4E_A;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PdpeSrc.u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_NX | X86_PDPE_A;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertReturn(rc == VINF_SUCCESS /* *must* test for VINF_SUCCESS!! */, rc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** r=bird: This guy will set the A bit on the PDE, probably harmless. */
e4ea543752422f1139923e3e506c625b0a1827c5vboxsync rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * makes no sense to prefetch more than one page.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#elif PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Syncs a page during a PGMVerifyAccess() call.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code (informational included).
9c425bdea5f0991df62922b1584b805a86f2f898vboxsync * @param GCPtrPage The address of the page to sync.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param fPage The effective guest page flags.
aaeb2e2f6ed5b164f1dec9a16a7adeb84f64cf31vboxsync * @param uErr The trap error code.
e4ea543752422f1139923e3e506c625b0a1827c5vboxsyncPGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_TYPE_AMD64) \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Mark this page as safe.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @todo not correct for pages that contain both code and data!! */
8c9d2065ca6efecd5661174e382314868c0d4b94vboxsync Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
8c9d2065ca6efecd5661174e382314868c0d4b94vboxsync * Get guest PD and index.
8c9d2065ca6efecd5661174e382314868c0d4b94vboxsync const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
8c9d2065ca6efecd5661174e382314868c0d4b94vboxsync PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
8c9d2065ca6efecd5661174e382314868c0d4b94vboxsync Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
8c9d2065ca6efecd5661174e382314868c0d4b94vboxsync PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPDSrc = 0;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * First check if the shadow pd is present.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* AMD-V nested paging */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Pml4eSrc.u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_NX | X86_PML4E_A;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PdpeSrc.u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_NX | X86_PDPE_A;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
223cf005b18af2c21352a70693ebaf0582f68ebcvboxsync AssertReturn(rc == VINF_SUCCESS /* *must* test for VINF_SUCCESS!! */, rc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Check for dirty bit fault */
6b022885f2cb6a55167609edecd89570cd80001dvboxsync rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
57399ab65e2825c324fb9dcb4642d4ae2c232509vboxsync#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync else /* supervisor */
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
11c599b71a8c202a506b8623af57432c3d415ddavboxsync rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
11c599b71a8c202a506b8623af57432c3d415ddavboxsync /* Page was successfully synced */
11c599b71a8c202a506b8623af57432c3d415ddavboxsync Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
11c599b71a8c202a506b8623af57432c3d415ddavboxsync#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
11c599b71a8c202a506b8623af57432c3d415ddavboxsync AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
11c599b71a8c202a506b8623af57432c3d415ddavboxsync#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
11c599b71a8c202a506b8623af57432c3d415ddavboxsync#if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64
11c599b71a8c202a506b8623af57432c3d415ddavboxsync# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64
11c599b71a8c202a506b8623af57432c3d415ddavboxsync * Figures out which kind of shadow page this guest PDE warrants.
11c599b71a8c202a506b8623af57432c3d415ddavboxsync * @returns Shadow page kind.
11c599b71a8c202a506b8623af57432c3d415ddavboxsync * @param pPdeSrc The guest PDE in question.
11c599b71a8c202a506b8623af57432c3d415ddavboxsync * @param cr4 The current guest cr4 value.
11c599b71a8c202a506b8623af57432c3d415ddavboxsyncDECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
11c599b71a8c202a506b8623af57432c3d415ddavboxsync //switch (pPdeSrc->u & (X86_PDE4M_RW | X86_PDE4M_US /*| X86_PDE4M_PAE_NX*/))
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // case X86_PDE4M_RW:
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // case X86_PDE4M_US:
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // case X86_PDE4M_RW | X86_PDE4M_US:
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // case X86_PDE4M_PAE_NX:
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // case X86_PDE4M_RW | X86_PDE4M_PAE_NX:
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // case X86_PDE4M_US | X86_PDE4M_PAE_NX:
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // case X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PAE_NX:
11c599b71a8c202a506b8623af57432c3d415ddavboxsync // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
11c599b71a8c202a506b8623af57432c3d415ddavboxsync#define MY_STAM_COUNTER_INC(a) do { } while (0)
11c599b71a8c202a506b8623af57432c3d415ddavboxsync * Syncs the paging hierarchy starting at CR3.
11c599b71a8c202a506b8623af57432c3d415ddavboxsync * @returns VBox status code, no specials.
11c599b71a8c202a506b8623af57432c3d415ddavboxsync * @param pVM The virtual machine.
11c599b71a8c202a506b8623af57432c3d415ddavboxsync * @param cr0 Guest context CR0 register
11c599b71a8c202a506b8623af57432c3d415ddavboxsync * @param cr3 Guest context CR3 register
11c599b71a8c202a506b8623af57432c3d415ddavboxsync * @param cr4 Guest context CR4 register
11c599b71a8c202a506b8623af57432c3d415ddavboxsync * @param fGlobal Including global page directories or not
11c599b71a8c202a506b8623af57432c3d415ddavboxsyncPGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
11c599b71a8c202a506b8623af57432c3d415ddavboxsync fGlobal = true; /* Change this CR3 reload to be a global one. */
11c599b71a8c202a506b8623af57432c3d415ddavboxsync#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
11c599b71a8c202a506b8623af57432c3d415ddavboxsync * Update page access handlers.
11c599b71a8c202a506b8623af57432c3d415ddavboxsync * The virtual are always flushed, while the physical are only on demand.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * have to look into that later because it will have a bad influence on the performance.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @note SvL: There's no need for that. Just invalidate the virtual range(s).
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * bird: Yes, but that won't work for aliases.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @todo this MUST go away. See #1557. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#if PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
bee80f3f77b15c166b7debd080a70e5231ba6751vboxsync /** @todo check if this is really necessary */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* No need to check all paging levels; we zero out the shadow parts when the guest modifies its tables. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Get page directory addresses.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# else /* PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64*/
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
e4ea543752422f1139923e3e506c625b0a1827c5vboxsync * Iterate the page directory.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Only check mappings if they are supposed to be put into the shadow page table. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync for (uint64_t iPml4e = 0; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Anything significant changed? */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if ( pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Free it. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("SyncCR3: Out-of-sync PML4E (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
57399ab65e2825c324fb9dcb4642d4ae2c232509vboxsync (uint64_t)iPml4e << X86_PML4_SHIFT, pShwPdpt->GCPhys, GCPhysPdptSrc, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Force an attribute sync. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pPml4eDst->n.u1NoExecute = pPml4eSrc->n.u1NoExecute;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync for (uint64_t iPdpte = 0; iPdpte < GST_PDPE_ENTRIES; iPdpte++)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpte * X86_PG_PAE_ENTRIES];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpte << X86_PDPT_SHIFT, &iPDSrc);
7bae75e0b207aa4d4cad2a951271ad1a0e8ab9fdvboxsync PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
da936e0446fb2b56b813d5d938f1dfc6e4bf8b13vboxsync X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
da936e0446fb2b56b813d5d938f1dfc6e4bf8b13vboxsync /* PDPE not present */
da936e0446fb2b56b813d5d938f1dfc6e4bf8b13vboxsync if (pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present)
da936e0446fb2b56b813d5d938f1dfc6e4bf8b13vboxsync LogFlow(("SyncCR3: guest PDPE %d not present; clear shw pdpe\n", iPdpte));
da936e0446fb2b56b813d5d938f1dfc6e4bf8b13vboxsync /* for each page directory entry */
da936e0446fb2b56b813d5d938f1dfc6e4bf8b13vboxsync for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpte * X86_PG_PAE_ENTRIES + iPD);
1b7f3a92e42fb9cabf96cf31c20481da466edf76vboxsync if (!(pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].u & PGM_PLXFLAGS_MAPPING))
7e2fce486e7e2e45eb61d78ee206ba42ed89e016vboxsync pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present = 0;
6b022885f2cb6a55167609edecd89570cd80001dvboxsync# else /* PGM_GST_TYPE != PGM_TYPE_PAE */
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync RTGCUINTPTR GCPtr = (iPml4e << X86_PML4_SHIFT) || (iPdpte << X86_PDPT_SHIFT);
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
9f1e0743f565b1975bb4efd7311b30cfa0d3e384vboxsync int rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
da936e0446fb2b56b813d5d938f1dfc6e4bf8b13vboxsync break; /* next PML4E */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
9f1e0743f565b1975bb4efd7311b30cfa0d3e384vboxsync continue; /* next PDPTE */
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync /* Fetch the pgm pool shadow descriptor if the shadow pdpte is present. */
2b88b28162a49c6fa769c03d56767a9806d4f456vboxsync continue; /* next PDPTE */
8f7bc6ad2b7bbcb4b3b96248cd2478e45f2e3b88vboxsync pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
da936e0446fb2b56b813d5d938f1dfc6e4bf8b13vboxsync /* Anything significant changed? */
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync /* Free it. */
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync LogFlow(("SyncCR3: Out-of-sync PDPE (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync ((uint64_t)iPml4e << X86_PML4_SHIFT) + ((uint64_t)iPdpte << X86_PDPT_SHIFT), pShwPde->GCPhys, GCPhysPdeSrc, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
da936e0446fb2b56b813d5d938f1dfc6e4bf8b13vboxsync /* Mark it as not present if there's no hypervisor mapping present. (bit flipped at the top of Trap0eHandler) */
4cad44a5f7cfa7db8d5fb255a1df3b3cd1687853vboxsync pgmPoolFreeByPage(pPool, pShwPde, pShwPde->idx, iPdpte);
da936e0446fb2b56b813d5d938f1dfc6e4bf8b13vboxsync continue; /* next guest PDPTE */
8f7bc6ad2b7bbcb4b3b96248cd2478e45f2e3b88vboxsync /* Force an attribute sync. */
5db1d52ffbcaa46c3d944c6c2d9c552306817d9avboxsync# endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
54fe68d807196dc565de24055996e634ee40ee92vboxsync# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
54fe68d807196dc565de24055996e634ee40ee92vboxsync for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync AssertMsg(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst, ("%p vs %p\n", &pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512], pPDEDst));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Check for conflicts with GC mappings.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (iPD + iPdpte * X86_PG_PAE_ENTRIES == iPdNoMapping)
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync /* It's fixed, just skip the mapping. */
75fca099c974cbbd48f132af1378c60232614760vboxsync const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
da936e0446fb2b56b813d5d938f1dfc6e4bf8b13vboxsync iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
e751d1e1e4ae424d4846a23da32f663d14960796vboxsync * Update iPdNoMapping and pMapping.
2b88b28162a49c6fa769c03d56767a9806d4f456vboxsync while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
10e1bc06b2908a0af56d92ffdbadd25b36a5ef61vboxsync iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
5db1d52ffbcaa46c3d944c6c2d9c552306817d9avboxsync LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
54fe68d807196dc565de24055996e634ee40ee92vboxsync# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) || PGM_WITHOUT_MAPPINGS */
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) || PGM_WITHOUT_MAPPINGS */
2b88b28162a49c6fa769c03d56767a9806d4f456vboxsync * Sync page directory entry.
54fe68d807196dc565de24055996e634ee40ee92vboxsync * The current approach is to allocated the page table but to set
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync * the entry to not-present and postpone the page table synching till
ec588a4ac8429a8b6c744544818b3ce3b2c75690vboxsync * it's actually used.
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
da936e0446fb2b56b813d5d938f1dfc6e4bf8b13vboxsync for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
5be6801527b2bb09f4b481e28d771f366961cdacvboxsync const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
907da3b41f191bef4c8eb94accb9d16fcbe77019vboxsync /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || ( (PdeSrc.u & (X86_PDE4M_PS | X86_PDE4M_G)) == (X86_PDE4M_PS | X86_PDE4M_G)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && (cr4 & (X86_CR4_PGE | X86_CR4_PSE)) == (X86_CR4_PGE | X86_CR4_PSE)) /* global 2/4MB page. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && ( (PdeSrc.u & (X86_PDE_US | X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US | X86_PDE_RW))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && ((PdeSrc.u & (X86_PDE_US | X86_PDE4M_PS | X86_PDE4M_D)) | PGM_PDFLAGS_TRACK_DIRTY)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync == ((PdeDst.u & (X86_PDE_US | X86_PDE_RW | PGM_PDFLAGS_TRACK_DIRTY)) | X86_PDE4M_PS))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && (PdeSrc.u & (X86_PDE4M_PS | X86_PDE4M_G)) == (X86_PDE4M_PS | X86_PDE4M_G)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && (cr4 & (X86_CR4_PGE | X86_CR4_PSE)) == (X86_CR4_PGE | X86_CR4_PSE))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# endif /* VBOX_WITH_STATISTICS */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync //# ifdef PGMPOOL_WITH_CACHE
50df3da42ff6589b0ecc4f50f2288811bc370186vboxsync // pgmPoolCacheUsed(pPool, pShwPage);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPdShw);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync else if (iPD + iPdpte * X86_PG_PAE_ENTRIES != iPdNoMapping)
e4ea543752422f1139923e3e506c625b0a1827c5vboxsync * Check if there is any page directory to mark not present here.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), pShwPde->idx, iPdShw);
65ff326ac3915638f5c4e79c2c3e836aeeeb86devboxsync pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* It's fixed, just skip the mapping. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Check for conflicts for subsequent pagetables
e4ea543752422f1139923e3e506c625b0a1827c5vboxsync * and advance to the next mapping.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && (pPDSrc->a[iPD + iPT].n.u1User || fRawR0Enabled))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
65ff326ac3915638f5c4e79c2c3e836aeeeb86devboxsync int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Update iPdNoMapping and pMapping.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* advance. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) || PGM_WITHOUT_MAPPINGS */
65ff326ac3915638f5c4e79c2c3e836aeeeb86devboxsync# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) || PGM_WITHOUT_MAPPINGS */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync } /* for iPD */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync } /* for each PDPTE (PAE) */
65ff326ac3915638f5c4e79c2c3e836aeeeb86devboxsync } /* for each page map level 4 entry (amd64) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# else /* guest real and protected mode */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code (VINF_SUCCESS).
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param cr3 The root of the hierarchy.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param crr The cr4, only PAE and PSE is currently used.
aaeb2e2f6ed5b164f1dec9a16a7adeb84f64cf31vboxsync * @param fLongMode Set if long mode, false if not long mode.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param cMaxDepth Number of levels to dump.
aaeb2e2f6ed5b164f1dec9a16a7adeb84f64cf31vboxsync * @param pHlp Pointer to the output functions.
bee80f3f77b15c166b7debd080a70e5231ba6751vboxsyncVMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
6b022885f2cb6a55167609edecd89570cd80001dvboxsync * Checks that the shadow page table is in sync with the guest one.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns The number of errors.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The virtual machine.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param cr3 Guest context CR3 register
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param cr4 Guest context CR4 register
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param GCPtr Where to start. Defaults to 0.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param cb How much to check. Defaults to everything.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncPGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#if PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
e4ea543752422f1139923e3e506c625b0a1827c5vboxsync unsigned cErrors = 0;
bee80f3f77b15c166b7debd080a70e5231ba6751vboxsync /* @todo currently broken; crashes below somewhere */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Check that the Guest CR3 and all its mappings are correct.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
bee80f3f77b15c166b7debd080a70e5231ba6751vboxsync ("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGuestPDGC, NULL, &HCPhysShw);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePDPTGC, NULL, &HCPhysShw);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
bee80f3f77b15c166b7debd080a70e5231ba6751vboxsync rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#endif /* !IN_RING0 */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Get and check the Shadow CR3.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync unsigned ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync unsigned ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync/** @todo call the other two PGMAssert*() functions. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
6f516ad9911d9037a18778742caa955fe362f8ffvboxsync /* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* not correct to call pgmPoolGetPage */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
fa7355597d7eba5b4ca8a23056ebe1b8fb306fdbvboxsync AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Physical address doesn't match! iPml4e %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
aaeb2e2f6ed5b164f1dec9a16a7adeb84f64cf31vboxsync || pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Check the PDPTEs too.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync unsigned iPdpte = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync continue; /* next PDPTE */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync continue; /* next PDPTE */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
fa7355597d7eba5b4ca8a23056ebe1b8fb306fdbvboxsync AssertMsgFailed(("Physical address doesn't match! iPml4e %d iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Physical address doesn't match! iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync const PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Iterate the shadow page directory.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || ((PdeDst.u & (X86_PDE_P | PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P | PGM_PDFLAGS_TRACK_DIRTY))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync const SHWPT *pPTDst = (const SHWPT *)PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
9f1e0743f565b1975bb4efd7311b30cfa0d3e384vboxsync AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
9f1e0743f565b1975bb4efd7311b30cfa0d3e384vboxsync AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
9f1e0743f565b1975bb4efd7311b30cfa0d3e384vboxsync const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
9f1e0743f565b1975bb4efd7311b30cfa0d3e384vboxsync AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
e4ea543752422f1139923e3e506c625b0a1827c5vboxsync AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync != (!PdeSrc.b.u1Size || !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
9f1e0743f565b1975bb4efd7311b30cfa0d3e384vboxsync AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Page Table.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
40f47bc231ff6c86a7ddc3295eed7010e889e78avboxsync AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
40f47bc231ff6c86a7ddc3295eed7010e889e78avboxsync if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_US | X86_PDE_RW/* | X86_PDE_A*/))
40f47bc231ff6c86a7ddc3295eed7010e889e78avboxsync != (PdeDst.u & (X86_PDE_P | X86_PDE_US | X86_PDE_RW/* | X86_PDE_A*/)))
40f47bc231ff6c86a7ddc3295eed7010e889e78avboxsync /// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
e4ea543752422f1139923e3e506c625b0a1827c5vboxsync // (This problem will go away when/if we shadow multiple CR3s.)
40f47bc231ff6c86a7ddc3295eed7010e889e78avboxsync AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
40f47bc231ff6c86a7ddc3295eed7010e889e78avboxsync AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync /* iterate the page table. */
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync const unsigned offPTSrc = 0;
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync /* skip not-present entries. */
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync if (!(PteDst.u & (X86_PTE_P | PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync (PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync uint64_t fIgnoreFlags = GST_PTE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_G | X86_PTE_D | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT;
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync /* match the physical addresses */
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
22e281e75ed636601178296c6daebda8f1d17c59vboxsync else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
6b022885f2cb6a55167609edecd89570cd80001dvboxsync /* flags */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
d86aa8a95e908fa0d5e88ed662ea0a919f17756fvboxsync# if 0 /** @todo sync access bit properly... */
9c425bdea5f0991df62922b1584b805a86f2f898vboxsync AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
9c425bdea5f0991df62922b1584b805a86f2f898vboxsync /* access bit emulation (not implemented). */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
9f1e0743f565b1975bb4efd7311b30cfa0d3e384vboxsync GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
9f1e0743f565b1975bb4efd7311b30cfa0d3e384vboxsync AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
9f1e0743f565b1975bb4efd7311b30cfa0d3e384vboxsync GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
40f47bc231ff6c86a7ddc3295eed7010e889e78avboxsync if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
40f47bc231ff6c86a7ddc3295eed7010e889e78avboxsync && (PteSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync } /* foreach PTE */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Big Page.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync uint64_t fIgnoreFlags = X86_PDE_AVL_MASK | GST_PDE_PG_MASK | X86_PDE4M_G | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_PWT | X86_PDE4M_PCD;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
5e9dc1c79a0a8fc61c32f6dbbe21ce385fdbebd2vboxsync AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# if 0 /** @todo sync access bit properly... */
f3c0757250e08fe6b4890aee39c38c5688715682vboxsync AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* access bit emulation (not implemented). */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
68ef804c4ec232c58e2c03c8fc6afe3765c5c0d1vboxsync /* iterate the page table. */
ec588a4ac8429a8b6c744544818b3ce3b2c75690vboxsync AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
ec588a4ac8429a8b6c744544818b3ce3b2c75690vboxsync GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* skip not-present entries. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync fIgnoreFlags = X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT | X86_PTE_D | X86_PTE_A | X86_PTE_G | X86_PTE_PAE_NX;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* match the physical addresses */
f3c0757250e08fe6b4890aee39c38c5688715682vboxsync rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
5ab935df052385fd74329486db23ea63b2004b41vboxsync AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
5ab935df052385fd74329486db23ea63b2004b41vboxsync GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
5ab935df052385fd74329486db23ea63b2004b41vboxsync else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* flags */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
cea1d6e05b07cd0c9438beb30e628187e4969cffvboxsync if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
cea1d6e05b07cd0c9438beb30e628187e4969cffvboxsync && (PdeSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync } /* for each PTE */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* not present */
6b022885f2cb6a55167609edecd89570cd80001dvboxsync } /* for each PDE */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync } /* for each PDPTE */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync } /* for each PML4E */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#endif /* VBOX_STRICT */