PGMAll.cpp revision 77682510bcb3d646d564faf87accf7cae38d9e61
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * PGM - Page Manager and Monitor - All context code.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Copyright (C) 2006-2007 Oracle Corporation
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * available from http://www.virtualbox.org. This file is free software;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * you can redistribute it and/or modify it under the terms of the GNU
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * General Public License (GPL) as published by the Free Software
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync/*******************************************************************************
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync* Header Files *
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync*******************************************************************************/
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync/*******************************************************************************
7d6ce198fd361f58bd1ebdeee7772f76b4e58966vboxsync* Structures and Typedefs *
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync*******************************************************************************/
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
40839c441cb305d84420565f7ca25403d8177413vboxsynctypedef struct PGMHVUSTATE
7d6ce198fd361f58bd1ebdeee7772f76b4e58966vboxsync /** The VM handle. */
7d6ce198fd361f58bd1ebdeee7772f76b4e58966vboxsync /** The VMCPU handle. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /** The todo flags. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /** The CR4 register value. */
a1d9d394b49969e730c5a8e037ea2d672a48dbf6vboxsync/*******************************************************************************
edde275acba04aca58db4172a163741e3abadfbcvboxsync* Internal Functions *
edde275acba04aca58db4172a163741e3abadfbcvboxsync*******************************************************************************/
edde275acba04aca58db4172a163741e3abadfbcvboxsyncDECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
edde275acba04aca58db4172a163741e3abadfbcvboxsyncDECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncstatic int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncstatic int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Shadow - 32-bit mode
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync/* Guest - real mode */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync/* Guest - protected mode */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync/* Guest - 32-bit mode */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Shadow - PAE mode
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync/* Guest - real mode */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync/* Guest - protected mode */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync/* Guest - 32-bit mode */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
0c2ffca957882f38c677fc23f324cfd695b96947vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync/* Guest - PAE mode */
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
0c2ffca957882f38c677fc23f324cfd695b96947vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
0c2ffca957882f38c677fc23f324cfd695b96947vboxsync#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
88d7b87c38cc3800f532139696785e8c96bfd531vboxsync * Shadow - AMD64 mode
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
0c2ffca957882f38c677fc23f324cfd695b96947vboxsync/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync/* Guest - AMD64 mode */
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync# endif /* VBOX_WITH_64_BITS_GUESTS */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Shadow - Nested paging mode
f20463d06f9bf3f81e2c049c697dcd20a0b0c435vboxsync# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
4db69c2a1302fa56bc5dd7181377b9f47cfd875evboxsync/* Guest - real mode */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync/* Guest - protected mode */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync/* Guest - 32-bit mode */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync/* Guest - PAE mode */
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync/* Guest - AMD64 mode */
9f997e760f610c92e3a365be21ead6972bc46130vboxsync# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
9f997e760f610c92e3a365be21ead6972bc46130vboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync# endif /* VBOX_WITH_64_BITS_GUESTS */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Shadow - EPT
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync/* Guest - real mode */
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
100b161379af7255c69e27587cc746e5f76ff050vboxsync/* Guest - protected mode */
100b161379af7255c69e27587cc746e5f76ff050vboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
100b161379af7255c69e27587cc746e5f76ff050vboxsync# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
1f64240a0fda7b4c7cc9fcd4ef610f26623485b8vboxsync/* Guest - 32-bit mode */
1f64240a0fda7b4c7cc9fcd4ef610f26623485b8vboxsync# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
100b161379af7255c69e27587cc746e5f76ff050vboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1f64240a0fda7b4c7cc9fcd4ef610f26623485b8vboxsync# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
1f64240a0fda7b4c7cc9fcd4ef610f26623485b8vboxsync/* Guest - PAE mode */
beed5fc4d17b85d6d05516ae63e6308af82ad96fvboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
beed5fc4d17b85d6d05516ae63e6308af82ad96fvboxsync# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
f81115e612ee8fa2bc082db9d4c8879e33babc5avboxsync/* Guest - AMD64 mode */
9f997e760f610c92e3a365be21ead6972bc46130vboxsync# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync# endif /* VBOX_WITH_64_BITS_GUESTS */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#endif /* !IN_RC */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * #PF Handler.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns VBox status code (appropriate for trap handling and GC return).
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pVCpu VMCPU handle.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param uErr The trap error code.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pRegFrame Trap register frame.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pvFault The fault address.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncVMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, a);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Error code stats.
4db69c2a1302fa56bc5dd7181377b9f47cfd875evboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentWrite);
4db69c2a1302fa56bc5dd7181377b9f47cfd875evboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentRead);
4db69c2a1302fa56bc5dd7181377b9f47cfd875evboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSWrite);
4db69c2a1302fa56bc5dd7181377b9f47cfd875evboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSReserved);
4db69c2a1302fa56bc5dd7181377b9f47cfd875evboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNXE);
4db69c2a1302fa56bc5dd7181377b9f47cfd875evboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSRead);
4db69c2a1302fa56bc5dd7181377b9f47cfd875evboxsync { /* Supervisor */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentWrite);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentRead);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVWrite);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSNXE);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVReserved);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#endif /* VBOX_WITH_STATISTICS */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Call the worker.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync bool fLockTaken = false;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync LogFlow(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv rc=%Rrc\n", uErr, pvFault, rc));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Return code tweaks.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* Note: hack alert for difficult to reproduce problem. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
30f07af559efcbd967e801903746fc21f81ee533vboxsync || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPF); });
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Misc; });
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#endif /* !IN_RING3 */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Prefetch a page
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Typically used to sync commonly used pages before entering raw mode
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * after a CR3 reload.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns VBox status code suitable for scheduling.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @retval VINF_SUCCESS on success.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pVCpu VMCPU handle.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param GCPtrPage Page to invalidate.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncVMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Gets the mapping corresponding to the specified address (if any).
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns Pointer to the mapping.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns NULL if not
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM The virtual machine.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param GCPtr The guest context pointer.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Verifies a range of pages for read or write access
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Only checks the guest's page tables
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns VBox status code.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVCpu VMCPU handle.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param Addr Guest virtual address to check
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param cbSize Access size
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @remarks Current not in use.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncVMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Validate input.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Check if the access would cause a page fault
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Note that hypervisor page directories are not present in the guest's tables, so this check
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * is sufficient.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Verifies a range of pages for read or write access
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Supports handling of pages marked for dirty bit tracking and CSAM
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns VBox status code.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pVCpu VMCPU handle.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param Addr Guest virtual address to check
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param cbSize Access size
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsyncVMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Get going.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Check if the access would cause a page fault
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Note that hypervisor page directories are not present in the guest's tables, so this check
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * is sufficient.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Page is not present in our page tables.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Try to sync it!
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
e17f6f8a70a7709a9a6319d9a473596fb600b552vboxsync uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
30f07af559efcbd967e801903746fc21f81ee533vboxsync AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#if 0 /* def VBOX_STRICT; triggers too often now */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * This check is a bit paranoid, but useful.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* Note! This will assert when writing to monitored pages (a bit annoying actually). */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Emulation of the invlpg instruction (HC only actually).
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns Strict VBox status code, special care required.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @retval VINF_PGM_SYNC_CR3 - handled.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVCpu VMCPU handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param GCPtrPage Page to invalidate.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @remark ASSUMES the page table entry or page directory is valid. Fairly
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * safe, but there could be edge cases!
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @todo Flush page or page directory only if necessary!
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @todo VBOXSTRICTRC
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncVMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Notify the recompiler so it can record this instruction.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync#endif /* !IN_RING3 */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Check for conflicts and pending CR3 monitoring updates.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgConflict);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgSyncMonCR3);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync#endif /* IN_RC */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Call paging mode specific worker.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Check if we have a pending update of the CR3 monitoring.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Inform CSAM about the flush
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Note: This is to check if monitored pages have been changed; when we implement
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * callbacks for virtual handlers, this is no longer required.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync#endif /* IN_RING3 */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* Ignore all irrelevant error codes. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Executes an instruction using the interpreter.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns VBox status code (appropriate for trap handling and GC return).
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM VM handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVCpu VMCPU handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pRegFrame Register frame.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pvFault Fault address.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncVMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync VBOXSTRICTRC rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Gets effective page information (from the VMM page directory).
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns VBox status.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVCpu VMCPU handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param GCPtr Guest Context virtual address of the page.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pfFlags Where to store the flags. These are X86_PTE_*.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pHCPhys Where to store the HC physical address of the page.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * This is page aligned.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @remark You should use PGMMapGetPage() for pages in a mapping.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncVMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Modify page flags for a range of pages in the shadow context.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * The existing flags are ANDed with the fMask and ORed with the fFlags.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns VBox status code.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVCpu VMCPU handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param GCPtr Virtual address of the first page in the range.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param fMask The AND mask - page flags X86_PTE_*.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Be very CAREFUL when ~'ing constants which could be 32-bit!
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @remark You must use PGMMapModifyPage() for pages in a mapping.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncDECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT)));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync GCPtr &= PAGE_BASE_GC_MASK; /** @todo this ain't necessary, right... */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, PAGE_SIZE, fFlags, fMask, fOpFlags);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Changing the page flags for a single page in the shadow page tables so as to
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * make it read-only.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns VBox status code.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVCpu VMCPU handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param GCPtr Virtual address of the first page in the range.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncVMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Changing the page flags for a single page in the shadow page tables so as to
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * make it writable.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * The call must know with 101% certainty that the guest page tables maps this
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * as writable too. This function will deal shared, zero and write monitored
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns VBox status code.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVCpu VMCPU handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param GCPtr Virtual address of the first page in the range.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param fMmio2 Set if it is an MMIO2 page.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncVMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
100b161379af7255c69e27587cc746e5f76ff050vboxsync * Changing the page flags for a single page in the shadow page tables so as to
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * make it not present.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns VBox status code.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param pVCpu VMCPU handle.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param GCPtr Virtual address of the first page in the range.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsyncVMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * Gets the shadow page directory for the specified address, PAE.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @returns Pointer to the shadow PD.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param pVCpu The VMCPU handle.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param GCPtr The address.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param uGstPdpe Guest PDPT entry. Valid.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param ppPD Receives address of page directory
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsyncint pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
100b161379af7255c69e27587cc746e5f76ff050vboxsync /* Allocate page directory if not present. */
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync if (pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu))
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync /* AMD-V nested paging or real/protected mode without paging. */
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync /* PD not present; guest must reload CR3 to change it.
100b161379af7255c69e27587cc746e5f76ff050vboxsync * No need to monitor anything in this case.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync /* Create a reference back to the PDPT by using the index in its shadow page. */
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync /* The PD was cached or created; hook it up now. */
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & (X86_PDPE_P | X86_PDPE_A));
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync# if defined(IN_RC)
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * In 32 bits PAE mode we *must* invalidate the TLB when changing a
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * PDPT entry; the CPU fetches them only during cr3 load, so any
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * non-present PDPT will continue to cause page faults.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * Gets the pointer to the shadow page directory entry for an address, PAE.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @returns Pointer to the PDE.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param pVCpu The current CPU.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param GCPtr The address.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsyncDECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync /* Fetch the pgm pool shadow descriptor. */
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Syncs the SHADOW page directory pointer for the specified address.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Allocates backing pages in case the PDPT or PML4 entry is missing.
100b161379af7255c69e27587cc746e5f76ff050vboxsync * The caller is responsible for making sure the guest has a valid PD before
100b161379af7255c69e27587cc746e5f76ff050vboxsync * calling this function.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns VBox status.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVCpu VMCPU handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param GCPtr The address.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * @param uGstPml4e Guest PML4 entry (valid).
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync * @param uGstPdpe Guest PDPT entry (valid).
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param ppPD Receives address of page directory
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncstatic int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
30f07af559efcbd967e801903746fc21f81ee533vboxsync PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync bool fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync /* Allocate page directory pointer table if not present. */
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync /* AMD-V nested paging or real/protected mode without paging */
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync /* Create a reference back to the PDPT by using the index in its shadow page. */
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync /* The PDPT was cached or created; hook it up now. */
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync pPml4e->u |= pShwPage->Core.Key | (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync /* Allocate page directory if not present. */
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync /* AMD-V nested paging or real/protected mode without paging */
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync /* Create a reference back to the PDPT by using the index in its shadow page. */
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync /* The PD was cached or created; hook it up now. */
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * Gets the SHADOW page directory pointer for the specified address (long mode).
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * @returns VBox status.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * @param pVCpu VMCPU handle.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * @param GCPtr The address.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * @param ppPdpt Receives address of pdpt
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * @param ppPD Receives address of page directory
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsyncDECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
efdc3bd872b77b5ec7d19d77504264de24b0582bvboxsync Log4(("pgmShwGetLongModePDPtr %RGv -> *ppPD=%p PDE=%p/%RX64\n", GCPtr, *ppPD, &(*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * backing pages in case the PDPT or PML4 entry is missing.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * @returns VBox status.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * @param pVCpu VMCPU handle.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * @param GCPtr The address.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * @param ppPdpt Receives address of pdpt
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * @param ppPD Receives address of page directory
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsyncstatic int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync /* Allocate page directory pointer table if not present. */
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync /* The PDPT was cached or created; hook it up now and fill with the default value. */
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync /* Allocate page directory if not present. */
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_EPT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync /* The PD was cached or created; hook it up now and fill with the default value. */
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync#endif /* IN_RC */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Synchronizes a range of nested page table entries.
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync * The caller must own the PGM lock.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pVCpu The current CPU.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param GCPhys Where to start.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param cPages How many pages which entries should be synced.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param enmShwPagingMode The shadow paging mode (PGMMODE_EPT for VT-x,
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * host paging mode for AMD-V).
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncint pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync X86PDE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync AssertMsgFailedReturn(("%d\n", enmShwPagingMode), VERR_INTERNAL_ERROR_5);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync#endif /* IN_RING0 */
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * Gets effective Guest OS page information.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * When GCPtr is in a big page, the function will return as if it was a normal
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * 4KB page. If the need for distinguishing between big and normal page becomes
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * necessary at a later point, a PGMGstGetPage() will be created for that
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * @returns VBox status.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * @param pVCpu The current CPU.
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync * @param GCPtr Guest Context virtual address of the page.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * @param pGCPhys Where to store the GC physical address of the page.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * This is page aligned. The fact that the
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsyncVMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync * Checks if the page is present.
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync * @returns true if the page is present.
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync * @returns false if the page is not present.
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync * @param pVCpu VMCPU handle.
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync * @param GCPtr Address within the page.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsyncVMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Sets (replaces) the page flags for a range of pages in the guest's tables.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @returns VBox status.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pVCpu VMCPU handle.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param GCPtr The address of the first page.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param cb The size of the range in bytes.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsyncVMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Modify page flags for a range of pages in the guest's tables
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * The existing flags are ANDed with the fMask and ORed with the fFlags.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @returns VBox status code.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pVCpu VMCPU handle.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param GCPtr Virtual address of the first page in the range.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param cb Size (in bytes) of the range to apply the modification to.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Be very CAREFUL when ~'ing constants which could be 32-bit!
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncVMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Validate input.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Adjust input.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Call worker.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Performs the lazy mapping of the 32-bit guest PD.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @returns VBox status code.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pVCpu The current CPU.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param ppPd Where to return the pointer to the mapping. This is
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * always set.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsyncint pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAGE_MASK;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Performs the lazy mapping of the PAE guest PDPT.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @returns VBox status code.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pVCpu The current CPU.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param ppPdpt Where to return the pointer to the mapping. This is
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * always set.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsyncint pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt)
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsync pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Performs the lazy mapping / updating of a PAE guest PD.
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsync * @returns Pointer to the mapping.
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsync * @returns VBox status code.
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsync * @param pVCpu The current CPU.
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsync * @param iPdpt Which PD entry to map (0..3).
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsync * @param ppPd Where to return the pointer to the mapping. This is
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsync * always set.
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsyncint pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsync PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsync RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
cf0e96b2c5a08292c6d13e4fdcb2d9518d1983e8vboxsync rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &HCPtr);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync /* Invalid page or some failure, invalidate the entry. */
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Performs the lazy mapping of the 32-bit guest PD.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @returns VBox status code.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pVCpu The current CPU.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param ppPml4 Where to return the pointer to the mapping. This will
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * always be set.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsyncint pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4)
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Gets the specified page directory pointer table entry.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @returns PDP entry
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pVCpu VMCPU handle.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param iPdpt PDPT index
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsyncVMMDECL(int) PGMGstQueryPaePDPtr(PVMCPU pVCpu, unsigned iPdpt, PX86PDPE pPdpe)
30f07af559efcbd967e801903746fc21f81ee533vboxsync * Gets the current CR3 register value for the shadow memory context.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns CR3 value.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pVCpu VMCPU handle.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Gets the current CR3 register value for the nested memory context.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns CR3 value.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVCpu VMCPU handle.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncVMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Gets the current CR3 register value for the HC intermediate memory context.
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync * @returns CR3 value.
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync * @param pVM The VM handle.
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync * Gets the current CR3 register value for the RC intermediate memory context.
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync * @returns CR3 value.
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync * @param pVM The VM handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVCpu VMCPU handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncVMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync return 0; /* not relevant */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * Gets the CR3 register value for the 32-Bit intermediate memory context.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @returns CR3 value.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @param pVM The VM handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Gets the CR3 register value for the PAE intermediate memory context.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns CR3 value.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM The VM handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Gets the CR3 register value for the AMD64 intermediate memory context.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns CR3 value.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM The VM handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Performs and schedules necessary updates following a CR3 load or reload.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * This will normally involve mapping the guest PD or nPDPT
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns VBox status code.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync * safely be ignored and overridden since the FF will be set too then.
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync * @param pVCpu VMCPU handle.
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync * @param cr3 The new cr3.
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync * @param fGlobal Indicates whether this is a global flush or not.
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsyncVMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Always flag the necessary updates; necessary for hardware acceleration
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync /** @todo optimize this, it shouldn't always be necessary. */
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3Global));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Check if we have a pending update of the CR3 monitoring.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3Global));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Performs and schedules necessary updates following a CR3 load or reload when
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * using nested or extended paging.
30f07af559efcbd967e801903746fc21f81ee533vboxsync * This API is an alternative to PDMFlushTLB that avoids actually flushing the
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * TLB and triggering a SyncCR3.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * This will normally involve mapping the guest PD or nPDPT
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @returns VBox status code.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @retval VINF_SUCCESS.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * requires a CR3 sync. This can safely be ignored and overridden since
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync * the FF will be set too then.)
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param pVCpu VMCPU handle.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param cr3 The new cr3.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsyncVMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* We assume we're only called in nested paging mode. */
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync Assert(pVM->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
28a2653de6f80a4b1f000cfc52e1a04492d4c151vboxsync Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
30f07af559efcbd967e801903746fc21f81ee533vboxsync * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * Synchronize the paging structures.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * in several places, most importantly whenever the CR3 is loaded.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns VBox status code.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVCpu VMCPU handle.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param cr0 Guest context CR0 register
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param cr3 Guest context CR3 register
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param cr4 Guest context CR4 register
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param fGlobal Including global page directories or not
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncVMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
9f997e760f610c92e3a365be21ead6972bc46130vboxsync * The pool may have pending stuff and even require a return to ring-3 to
9f997e760f610c92e3a365be21ead6972bc46130vboxsync * clear the whole thing.
9f997e760f610c92e3a365be21ead6972bc46130vboxsync * We might be called when we shouldn't.
9f997e760f610c92e3a365be21ead6972bc46130vboxsync * The mode switching will ensure that the PD is resynced
9f997e760f610c92e3a365be21ead6972bc46130vboxsync * after every mode switch. So, if we find ourselves here
9f997e760f610c92e3a365be21ead6972bc46130vboxsync * when in protected or real mode we can safely disable the
9f997e760f610c92e3a365be21ead6972bc46130vboxsync * FF and return immediately.
9f997e760f610c92e3a365be21ead6972bc46130vboxsync if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
9f997e760f610c92e3a365be21ead6972bc46130vboxsync Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
9f997e760f610c92e3a365be21ead6972bc46130vboxsync Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
9f997e760f610c92e3a365be21ead6972bc46130vboxsync VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
9f997e760f610c92e3a365be21ead6972bc46130vboxsync /* If global pages are not supported, then all flushes are global. */
9f997e760f610c92e3a365be21ead6972bc46130vboxsync LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
9f997e760f610c92e3a365be21ead6972bc46130vboxsync VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * This should be done before SyncCR3.
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
680c2aff33be2ee9340c8763a3cb5c218c352bcfvboxsync Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Let the 'Bth' function do the work and we'll just keep track of the flags.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
90624af27b0e648b68167bd3b332d0e3b1d18ab1vboxsync rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
30f07af559efcbd967e801903746fc21f81ee533vboxsync STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync /* Go back to ring 3 if a pgm pool sync is again pending. */
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * Check if we have a pending update of the CR3 monitoring.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * Now flush the CR3 (guest context).
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * Called whenever CR0 or CR4 in a way which may affect the paging mode.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @returns VBox status code, with the following informational code for
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * VM scheduling.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * (I.e. not in R3.)
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @param pVCpu VMCPU handle.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @param cr0 The new cr0.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @param cr4 The new cr4.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @param efer The new extended feature enable register.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsyncVMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * Calc the new guest mode.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * Did it change?
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync /* Flush the TLB */
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * Gets the current guest paging mode.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @returns The current paging mode.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @param pVCpu VMCPU handle.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * Gets the current shadow paging mode.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @returns The current paging mode.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @param pVCpu VMCPU handle.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * Gets the current host paging mode.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @returns The current paging mode.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @param pVM The VM handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Get mode name.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @returns read-only name string.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param enmMode The mode which name is desired.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsyncVMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync default: return "unknown mode value";
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * Notification from CPUM that the EFER.NXE bit has changed.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param pVCpu The virtual CPU for which EFER changed.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param fNxe The new NXE state.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsyncVMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync Log(("PGMNotifyNxeChanged: fNxe=%RTbool\n", fNxe));
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync /*pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A */
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGst64ShadowedPteMask |= X86_PTE_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGst64ShadowedPdeMask |= X86_PDE_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGst64ShadowedBigPdeMask |= X86_PDE2M_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask |= X86_PDE2M_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask |= X86_PDPE_LM_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask |= X86_PML4E_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstPaeMbzBigPdeMask |= X86_PDE2M_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync /*pVCpu->pgm.s.fGstPaeMbzPdpeMask -N/A */
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64MbzPteMask |= X86_PTE_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64MbzPdeMask |= X86_PDE_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64MbzBigPdeMask |= X86_PDE2M_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64MbzPdpeMask |= X86_PDPE_LM_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask |= X86_PDPE_LM_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64MbzPml4eMask |= X86_PML4E_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGst64ShadowedPteMask &= ~X86_PTE_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGst64ShadowedPdeMask &= ~X86_PDE_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGst64ShadowedBigPdeMask &= ~X86_PDE2M_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask &= ~X86_PDPE_LM_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask &= ~X86_PML4E_NX;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * Check if any pgm pool pages are marked dirty (not monitored)
0d73750f953d8569054777eab62f40ad88a66d88vboxsync * @returns bool locked/not locked
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param pVM The VM to operate on.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * Check if this VCPU currently owns the PGM lock.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @returns bool owner/not owner
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param pVM The VM to operate on.
5b6c1ebab7273734a475e2e3b850b16ccbdf788cvboxsync * Enable or disable large page usage
5b6c1ebab7273734a475e2e3b850b16ccbdf788cvboxsync * @returns VBox status code.
5b6c1ebab7273734a475e2e3b850b16ccbdf788cvboxsync * @param pVM The VM to operate on.
5b6c1ebab7273734a475e2e3b850b16ccbdf788cvboxsync * @param fUseLargePages Use/not use large pages
5b6c1ebab7273734a475e2e3b850b16ccbdf788cvboxsyncVMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages)
5b6c1ebab7273734a475e2e3b850b16ccbdf788cvboxsync VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
30f07af559efcbd967e801903746fc21f81ee533vboxsync * Acquire the PGM lock.
30f07af559efcbd967e801903746fc21f81ee533vboxsync * @returns VBox status code
30f07af559efcbd967e801903746fc21f81ee533vboxsync * @param pVM The VM to operate on.
30f07af559efcbd967e801903746fc21f81ee533vboxsync int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
30f07af559efcbd967e801903746fc21f81ee533vboxsync rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * Release the PGM lock.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @returns VBox status code
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @param pVM The VM to operate on.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * Common worker for pgmRZDynMapGCPageOffInlined and pgmRZDynMapGCPageV2Inlined.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @returns VBox status code.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @param pVM The VM handle.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @param pVCpu The current CPU.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @param GCPhys The guest physical address of the page to map. The
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * offset bits are not ignored.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @param ppv Where to return the address corresponding to @a GCPhys.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsyncint pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL)
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * Convert it to a writable page and it on to the dynamic mapper.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync rc = pgmRZDynMapHCPageInlined(pVCpu, PGM_PAGE_GET_HCPHYS(pPage), &pv RTLOG_COMMA_SRC_POS_ARGS);
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync *ppv = (void *)((uintptr_t)pv | ((uintptr_t)GCPhys & PAGE_OFFSET_MASK));
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync/** Format handler for PGMPAGE.
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * @copydoc FNRTSTRFORMATTYPE */
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsyncstatic DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* The single char state stuff. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE_NA(pPage)];
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* The type. */
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][0];
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][1];
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][2];
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync /* The numbers. */
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS_NA(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS_NA(pPage)];
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX_NA(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync/** Format handler for PGMRAMRANGE.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @copydoc FNRTSTRFORMATTYPE */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncstatic DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
f81115e612ee8fa2bc082db9d4c8879e33babc5avboxsync PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync/** Format type andlers to be registered/deregistered. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncstatic const struct
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#endif /* !IN_R0 || LOG_ENABLED */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Registers the global string format types.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * This should be called at module load time or in some other manner that ensure
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * that it's called exactly one time.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns IPRT status code on RTStrFormatTypeRegister failure.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync unsigned i;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* in case of cleanup failure in ring-0 */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
f81115e612ee8fa2bc082db9d4c8879e33babc5avboxsync rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync while (i-- > 0)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Deregisters the global string format types.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * This should be called at module unload time or in some other manner that
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync * ensure that it's called exactly one time.
f81115e612ee8fa2bc082db9d4c8879e33babc5avboxsync for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
f81115e612ee8fa2bc082db9d4c8879e33babc5avboxsync RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Asserts that there are no mapping conflicts.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns Number of conflicts.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM The VM Handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncVMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync unsigned cErrors = 0;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* Only applies to raw mode -> 1 VPCU */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Check for mapping conflicts.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
f81115e612ee8fa2bc082db9d4c8879e33babc5avboxsync int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
f81115e612ee8fa2bc082db9d4c8879e33babc5avboxsync AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Asserts that everything related to the guest CR3 is correctly shadowed.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * and assert the correctness of the guest CR3 mapping before asserting that the
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * shadow page tables is in sync with the guest page tables.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns Number of conflicts.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM The VM Handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVCpu VMCPU handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param cr3 The current guest CR3 register value.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param cr4 The current guest CR4 register value.
f81115e612ee8fa2bc082db9d4c8879e33babc5avboxsyncVMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
46b9d3cd08a855c5d0e968e4fff0e89dea3fc2dfvboxsync STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync#endif /* VBOX_STRICT */