IOMAllMMIO.cpp revision dd8efff5286a99cf8d9b3a5e8dd62340973f3cc1
2N/A/* $Id$ */
2N/A/** @file
2N/A * IOM - Input / Output Monitor - Guest Context.
2N/A */
2N/A
2N/A/*
2N/A * Copyright (C) 2006-2007 innotek GmbH
2N/A *
2N/A * This file is part of VirtualBox Open Source Edition (OSE), as
2N/A * available from http://www.virtualbox.org. This file is free software;
2N/A * you can redistribute it and/or modify it under the terms of the GNU
2N/A * General Public License (GPL) as published by the Free Software
2N/A * Foundation, in version 2 as it comes in the "COPYING" file of the
2N/A * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
2N/A * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
2N/A */
2N/A
2N/A
2N/A/*******************************************************************************
2N/A* Header Files *
2N/A*******************************************************************************/
2N/A#define LOG_GROUP LOG_GROUP_IOM
2N/A#include <VBox/iom.h>
2N/A#include <VBox/cpum.h>
2N/A#include <VBox/pgm.h>
2N/A#include <VBox/selm.h>
2N/A#include <VBox/mm.h>
2N/A#include <VBox/em.h>
2N/A#include <VBox/pgm.h>
2N/A#include <VBox/trpm.h>
2N/A#include "IOMInternal.h"
2N/A#include <VBox/vm.h>
2N/A
2N/A#include <VBox/dis.h>
2N/A#include <VBox/disopcode.h>
2N/A#include <VBox/param.h>
2N/A#include <VBox/err.h>
2N/A#include <iprt/assert.h>
2N/A#include <VBox/log.h>
2N/A#include <iprt/asm.h>
2N/A#include <iprt/string.h>
2N/A
2N/A/*******************************************************************************
2N/A* Internal Functions *
2N/A*******************************************************************************/
2N/Astatic bool iomGetRegImmData(PDISCPUSTATE pCpu, PCOP_PARAMETER pParam, PCPUMCTXCORE pRegFrame, uint32_t *pu32Data, unsigned *pcbSize);
2N/Astatic bool iomSaveDataToReg(PDISCPUSTATE pCpu, PCOP_PARAMETER pParam, PCPUMCTXCORE pRegFrame, uint32_t u32Data);
2N/A
2N/A
2N/A/*******************************************************************************
2N/A* Global Variables *
2N/A*******************************************************************************/
2N/A/**
2N/A * Array for accessing 32-bit general registers in VMMREGFRAME structure
2N/A * by register's index from disasm.
2N/A */
2N/Astatic unsigned g_aReg32Index[] =
2N/A{
2N/A RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_EAX */
2N/A RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_ECX */
2N/A RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_EDX */
2N/A RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_EBX */
2N/A RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_ESP */
2N/A RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_EBP */
2N/A RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_ESI */
2N/A RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_EDI */
2N/A};
2N/A
2N/A/**
2N/A * Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
2N/A */
2N/A#define ACCESS_REG32(p, idx) (*((uint32_t *)((char *)(p) + g_aReg32Index[idx])))
2N/A
2N/A/**
2N/A * Array for accessing 16-bit general registers in CPUMCTXCORE structure
2N/A * by register's index from disasm.
2N/A */
2N/Astatic unsigned g_aReg16Index[] =
2N/A{
2N/A RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AX */
2N/A RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CX */
2N/A RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DX */
2N/A RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BX */
2N/A RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_SP */
2N/A RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_BP */
2N/A RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_SI */
2N/A RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_DI */
2N/A};
2N/A
2N/A/**
2N/A * Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
2N/A */
2N/A#define ACCESS_REG16(p, idx) (*((uint16_t *)((char *)(p) + g_aReg16Index[idx])))
2N/A
2N/A/**
2N/A * Array for accessing 8-bit general registers in CPUMCTXCORE structure
2N/A * by register's index from disasm.
2N/A */
2N/Astatic unsigned g_aReg8Index[] =
2N/A{
2N/A RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AL */
2N/A RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CL */
2N/A RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DL */
2N/A RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BL */
2N/A RT_OFFSETOF(CPUMCTXCORE, eax) + 1, /* USE_REG_AH */
2N/A RT_OFFSETOF(CPUMCTXCORE, ecx) + 1, /* USE_REG_CH */
2N/A RT_OFFSETOF(CPUMCTXCORE, edx) + 1, /* USE_REG_DH */
2N/A RT_OFFSETOF(CPUMCTXCORE, ebx) + 1 /* USE_REG_BH */
2N/A};
2N/A
2N/A/**
2N/A * Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
2N/A */
2N/A#define ACCESS_REG8(p, idx) (*((uint8_t *)((char *)(p) + g_aReg8Index[idx])))
2N/A
2N/A/**
2N/A * Array for accessing segment registers in CPUMCTXCORE structure
2N/A * by register's index from disasm.
2N/A */
2N/Astatic unsigned g_aRegSegIndex[] =
2N/A{
2N/A RT_OFFSETOF(CPUMCTXCORE, es), /* USE_REG_ES */
2N/A RT_OFFSETOF(CPUMCTXCORE, cs), /* USE_REG_CS */
2N/A RT_OFFSETOF(CPUMCTXCORE, ss), /* USE_REG_SS */
2N/A RT_OFFSETOF(CPUMCTXCORE, ds), /* USE_REG_DS */
2N/A RT_OFFSETOF(CPUMCTXCORE, fs), /* USE_REG_FS */
2N/A RT_OFFSETOF(CPUMCTXCORE, gs) /* USE_REG_GS */
2N/A};
2N/A
2N/A/**
2N/A * Macro for accessing segment registers in CPUMCTXCORE structure.
2N/A */
2N/A#define ACCESS_REGSEG(p, idx) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])))
2N/A
2N/A/**
2N/A * Array for fast recode of the operand size (1/2/4/8 bytes) to bit shift value.
2N/A */
2N/Astatic const unsigned g_aSize2Shift[] =
2N/A{
2N/A ~0, /* 0 - invalid */
2N/A 0, /* *1 == 2^0 */
2N/A 1, /* *2 == 2^1 */
2N/A ~0, /* 3 - invalid */
2N/A 2, /* *4 == 2^2 */
2N/A ~0, /* 5 - invalid */
2N/A ~0, /* 6 - invalid */
2N/A ~0, /* 7 - invalid */
2N/A 3 /* *8 == 2^3 */
2N/A};
2N/A
2N/A/**
2N/A * Macro for fast recode of the operand size (1/2/4/8 bytes) to bit shift value.
2N/A */
2N/A#define SIZE_2_SHIFT(cb) (g_aSize2Shift[cb])
2N/A
2N/A
2N/A/**
2N/A * Wrapper which does the write and updates range statistics when such are enabled.
2N/A * @warning VBOX_SUCCESS(rc=VINF_IOM_HC_MMIO_WRITE) is TRUE!
2N/A */
2N/ADECLINLINE(int) iomMMIODoWrite(PVM pVM, PIOMMMIORANGE pRange, RTGCPHYS GCPhysFault, const void *pvData, unsigned cb)
2N/A{
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhysFault, pRange);
2N/A Assert(pStats);
2N/A#endif
2N/A
2N/A int rc;
2N/A if (RT_LIKELY(pRange->CTXALLSUFF(pfnWriteCallback)))
2N/A rc = pRange->CTXALLSUFF(pfnWriteCallback)(pRange->CTXALLSUFF(pDevIns), pRange->CTXALLSUFF(pvUser), GCPhysFault, (void *)pvData, cb); /* @todo fix const!! */
2N/A else
2N/A rc = VINF_SUCCESS;
2N/A if (rc != VINF_IOM_HC_MMIO_WRITE)
2N/A STAM_COUNTER_INC(&pStats->CTXALLSUFF(Write));
2N/A return rc;
2N/A}
2N/A
2N/A/**
2N/A * Wrapper which does the read and updates range statistics when such are enabled.
2N/A */
2N/ADECLINLINE(int) iomMMIODoRead(PVM pVM, PIOMMMIORANGE pRange, RTGCPHYS GCPhysFault, void *pvData, unsigned cb)
2N/A{
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhysFault, pRange);
2N/A Assert(pStats);
2N/A#endif
2N/A
2N/A int rc;
2N/A if (RT_LIKELY(pRange->CTXALLSUFF(pfnReadCallback)))
2N/A rc = pRange->CTXALLSUFF(pfnReadCallback)(pRange->CTXALLSUFF(pDevIns), pRange->CTXALLSUFF(pvUser), GCPhysFault, pvData, cb);
2N/A else
2N/A {
2N/A switch (cb)
2N/A {
2N/A case 1: *(uint8_t *)pvData = 0; break;
2N/A case 2: *(uint16_t *)pvData = 0; break;
2N/A case 4: *(uint32_t *)pvData = 0; break;
2N/A case 8: *(uint64_t *)pvData = 0; break;
2N/A default:
2N/A memset(pvData, 0, cb);
2N/A break;
2N/A }
2N/A rc = VINF_SUCCESS;
2N/A }
2N/A if (rc != VINF_IOM_HC_MMIO_READ)
2N/A STAM_COUNTER_INC(&pStats->CTXALLSUFF(Read));
2N/A return rc;
2N/A}
2N/A
2N/A
2N/A/**
2N/A * Returns the contents of register or immediate data of instruction's parameter.
2N/A *
2N/A * @returns true on success.
2N/A *
2N/A * @param pCpu Pointer to current disassembler context.
2N/A * @param pParam Pointer to parameter of instruction to proccess.
2N/A * @param pRegFrame Pointer to CPUMCTXCORE guest structure.
2N/A * @param pu32Data Where to store retrieved data.
2N/A * @param pcbSize Where to store the size of data (1, 2, 4).
2N/A */
2N/Astatic bool iomGetRegImmData(PDISCPUSTATE pCpu, PCOP_PARAMETER pParam, PCPUMCTXCORE pRegFrame, uint32_t *pu32Data, unsigned *pcbSize)
2N/A{
2N/A if (pParam->flags & (USE_BASE | USE_INDEX | USE_SCALE | USE_DISPLACEMENT8 | USE_DISPLACEMENT16 | USE_DISPLACEMENT32))
2N/A {
2N/A *pcbSize = 0;
2N/A *pu32Data = 0;
2N/A return false;
2N/A }
2N/A
2N/A if (pParam->flags & USE_REG_GEN32)
2N/A {
2N/A *pcbSize = 4;
2N/A *pu32Data = ACCESS_REG32(pRegFrame, pParam->base.reg_gen32);
2N/A return true;
2N/A }
2N/A
2N/A if (pParam->flags & USE_REG_GEN16)
2N/A {
2N/A *pcbSize = 2;
2N/A *pu32Data = ACCESS_REG16(pRegFrame, pParam->base.reg_gen16);
2N/A return true;
2N/A }
2N/A
2N/A if (pParam->flags & USE_REG_GEN8)
2N/A {
2N/A *pcbSize = 1;
2N/A *pu32Data = ACCESS_REG8(pRegFrame, pParam->base.reg_gen8);
2N/A return true;
2N/A }
2N/A
2N/A if (pParam->flags & (USE_IMMEDIATE32|USE_IMMEDIATE32_SX8))
2N/A {
2N/A *pcbSize = 4;
2N/A *pu32Data = (uint32_t)pParam->parval;
2N/A return true;
2N/A }
2N/A
2N/A if (pParam->flags & (USE_IMMEDIATE16|USE_IMMEDIATE16_SX8))
2N/A {
2N/A *pcbSize = 2;
2N/A *pu32Data = (uint16_t)pParam->parval;
2N/A return true;
2N/A }
2N/A
2N/A if (pParam->flags & USE_IMMEDIATE8)
2N/A {
2N/A *pcbSize = 1;
2N/A *pu32Data = (uint8_t)pParam->parval;
2N/A return true;
2N/A }
2N/A
2N/A if (pParam->flags & USE_REG_SEG)
2N/A {
2N/A *pcbSize = 2;
2N/A *pu32Data = ACCESS_REGSEG(pRegFrame, pParam->base.reg_seg);
2N/A return true;
2N/A } /* Else - error. */
2N/A
2N/A *pcbSize = 0;
2N/A *pu32Data = 0;
2N/A return false;
2N/A}
2N/A
2N/A
2N/A/**
2N/A * Saves data to 8/16/32 general purpose or segment register defined by
2N/A * instruction's parameter.
2N/A *
2N/A * @returns true on success.
2N/A * @param pCpu Pointer to current disassembler context.
2N/A * @param pParam Pointer to parameter of instruction to proccess.
2N/A * @param pRegFrame Pointer to CPUMCTXCORE guest structure.
2N/A * @param u32Data 8/16/32 bit data to store.
2N/A */
2N/Astatic bool iomSaveDataToReg(PDISCPUSTATE pCpu, PCOP_PARAMETER pParam, PCPUMCTXCORE pRegFrame, unsigned u32Data)
2N/A{
2N/A if (pParam->flags & (USE_BASE | USE_INDEX | USE_SCALE | USE_DISPLACEMENT8 | USE_DISPLACEMENT16 | USE_DISPLACEMENT32 | USE_IMMEDIATE8 | USE_IMMEDIATE16 | USE_IMMEDIATE32 | USE_IMMEDIATE32_SX8 | USE_IMMEDIATE16_SX8))
2N/A {
2N/A return false;
2N/A }
2N/A
2N/A if (pParam->flags & USE_REG_GEN32)
2N/A {
2N/A ACCESS_REG32(pRegFrame, pParam->base.reg_gen32) = u32Data;
2N/A return true;
2N/A }
2N/A
2N/A if (pParam->flags & USE_REG_GEN16)
2N/A {
2N/A ACCESS_REG16(pRegFrame, pParam->base.reg_gen16) = (uint16_t)u32Data;
2N/A return true;
2N/A }
2N/A
2N/A if (pParam->flags & USE_REG_GEN8)
2N/A {
2N/A ACCESS_REG8(pRegFrame, pParam->base.reg_gen8) = (uint8_t)u32Data;
2N/A return true;
2N/A }
2N/A
2N/A if (pParam->flags & USE_REG_SEG)
2N/A {
2N/A ACCESS_REGSEG(pRegFrame, pParam->base.reg_seg) = (uint16_t)u32Data;
2N/A return true;
2N/A }
2N/A
2N/A /* Else - error. */
2N/A return false;
2N/A}
2N/A
2N/A
2N/A/*
2N/A * Internal - statistics only.
2N/A */
2N/ADECLINLINE(void) iomMMIOStatLength(PVM pVM, unsigned cb)
2N/A{
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A switch (cb)
2N/A {
2N/A case 1:
2N/A STAM_COUNTER_INC(&pVM->iom.s.StatGCMMIO1Byte);
2N/A break;
2N/A case 2:
2N/A STAM_COUNTER_INC(&pVM->iom.s.StatGCMMIO2Bytes);
2N/A break;
2N/A case 4:
2N/A STAM_COUNTER_INC(&pVM->iom.s.StatGCMMIO4Bytes);
2N/A break;
2N/A default:
2N/A /* No way. */
2N/A AssertMsgFailed(("Invalid data length %d\n", cb));
2N/A break;
2N/A }
2N/A#else
2N/A NOREF(pVM); NOREF(cb);
2N/A#endif
2N/A}
2N/A
2N/A
2N/A/**
2N/A * MOV reg, mem (read)
2N/A * MOVZX reg, mem (read)
2N/A * MOVSX reg, mem (read)
2N/A *
2N/A * @returns VBox status code.
2N/A *
2N/A * @param pVM The virtual machine (GC pointer ofcourse).
2N/A * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
2N/A * @param pCpu Disassembler CPU state.
2N/A * @param pRange Pointer MMIO range.
2N/A * @param GCPhysFault The GC physical address corresponding to pvFault.
2N/A */
2N/Astatic int iomInterpretMOVxXRead(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange, RTGCPHYS GCPhysFault)
2N/A{
2N/A Assert(pRange->CTXALLSUFF(pfnReadCallback) || !pRange->pfnReadCallbackR3);
2N/A
2N/A /*
2N/A * Get the data size from parameter 2,
2N/A * and call the handler function to get the data.
2N/A */
2N/A unsigned cb = DISGetParamSize(pCpu, &pCpu->param2);
2N/A AssertMsg(cb > 0 && cb <= sizeof(uint32_t), ("cb=%d\n", cb));
2N/A
2N/A uint32_t u32Data = 0;
2N/A int rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &u32Data, cb);
2N/A if (rc == VINF_SUCCESS)
2N/A {
2N/A /*
2N/A * Do sign extension for MOVSX.
2N/A */
2N/A /** @todo checkup MOVSX implementation! */
2N/A if (pCpu->pCurInstr->opcode == OP_MOVSX)
2N/A {
2N/A if (cb == 1)
2N/A {
2N/A /* DWORD <- BYTE */
2N/A int32_t iData = (int8_t)u32Data;
2N/A u32Data = (uint32_t)iData;
2N/A }
2N/A else
2N/A {
2N/A /* DWORD <- WORD */
2N/A int32_t iData = (int16_t)u32Data;
2N/A u32Data = (uint32_t)iData;
2N/A }
2N/A }
2N/A
2N/A /*
2N/A * Store the result to register (parameter 1).
2N/A */
2N/A bool fRc = iomSaveDataToReg(pCpu, &pCpu->param1, pRegFrame, u32Data);
2N/A AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
2N/A }
2N/A
2N/A if (rc == VINF_SUCCESS)
2N/A iomMMIOStatLength(pVM, cb);
2N/A return rc;
2N/A}
2N/A
2N/A
2N/A/**
2N/A * MOV mem, reg|imm (write)
2N/A *
2N/A * @returns VBox status code.
2N/A *
2N/A * @param pVM The virtual machine (GC pointer ofcourse).
2N/A * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
2N/A * @param pCpu Disassembler CPU state.
2N/A * @param pRange Pointer MMIO range.
2N/A * @param GCPhysFault The GC physical address corresponding to pvFault.
2N/A */
2N/Astatic int iomInterpretMOVxXWrite(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange, RTGCPHYS GCPhysFault)
2N/A{
2N/A Assert(pRange->CTXALLSUFF(pfnWriteCallback) || !pRange->pfnWriteCallbackR3);
2N/A
2N/A /*
2N/A * Get data to write from second parameter,
2N/A * and call the callback to write it.
2N/A */
2N/A unsigned cb = 0;
2N/A uint32_t u32Data = 0;
2N/A bool fRc = iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &u32Data, &cb);
2N/A AssertMsg(fRc, ("Failed to get reg/imm port number!\n")); NOREF(fRc);
2N/A
2N/A int rc = iomMMIODoWrite(pVM, pRange, GCPhysFault, &u32Data, cb);
2N/A if (rc == VINF_SUCCESS)
2N/A iomMMIOStatLength(pVM, cb);
2N/A return rc;
2N/A}
2N/A
2N/A
2N/A/** Wrapper for reading virtual memory. */
2N/ADECLINLINE(int) iomRamRead(PVM pVM, void *pDest, RTGCPTR GCSrc, uint32_t cb)
2N/A{
2N/A#ifdef IN_GC
2N/A return MMGCRamReadNoTrapHandler(pDest, GCSrc, cb);
2N/A#else
2N/A return PGMPhysReadGCPtrSafe(pVM, pDest, GCSrc, cb);
2N/A#endif
2N/A}
2N/A
2N/A
2N/A/** Wrapper for writing virtual memory. */
2N/ADECLINLINE(int) iomRamWrite(PVM pVM, RTGCPTR GCDest, void *pSrc, uint32_t cb)
2N/A{
2N/A#ifdef IN_GC
2N/A return MMGCRamWriteNoTrapHandler(GCDest, pSrc, cb);
2N/A#else
2N/A return PGMPhysWriteGCPtrSafe(pVM, GCDest, pSrc, cb);
2N/A#endif
2N/A}
2N/A
2N/A
2N/A#ifdef iom_MOVS_SUPPORT
2N/A/**
2N/A * [REP] MOVSB
2N/A * [REP] MOVSW
2N/A * [REP] MOVSD
2N/A *
2N/A * Restricted implementation.
2N/A *
2N/A *
2N/A * @returns VBox status code.
2N/A *
2N/A * @param pVM The virtual machine (GC pointer ofcourse).
2N/A * @param uErrorCode CPU Error code.
2N/A * @param pRegFrame Trap register frame.
2N/A * @param GCPhysFault The GC physical address corresponding to pvFault.
2N/A * @param pCpu Disassembler CPU state.
2N/A * @param pRange Pointer MMIO range.
2N/A */
2N/Astatic int iomInterpretMOVS(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
2N/A{
2N/A /*
2N/A * We do not support segment prefixes or REPNE.
2N/A */
2N/A if (pCpu->prefix & (PREFIX_SEG | PREFIX_REPNE))
2N/A return VINF_IOM_HC_MMIO_READ_WRITE; /** @todo -> interpret whatever. */
2N/A
2N/A
2N/A /*
2N/A * Get bytes/words/dwords count to copy.
2N/A */
2N/A uint32_t cTransfers = 1;
2N/A if (pCpu->prefix & PREFIX_REP)
2N/A {
2N/A cTransfers = pRegFrame->ecx;
2N/A if (!SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
2N/A cTransfers &= 0xffff;
2N/A
2N/A if (!cTransfers)
2N/A return VINF_SUCCESS;
2N/A }
2N/A
2N/A /* Get the current privilege level. */
2N/A uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2N/A
2N/A /*
2N/A * Get data size.
2N/A */
2N/A unsigned cb = DISGetParamSize(pCpu, &pCpu->param1);
2N/A Assert(cb);
2N/A int offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cb : (signed)cb;
2N/A
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A if (pVM->iom.s.cMovsMaxBytes < (cTransfers << SIZE_2_SHIFT(cb)))
2N/A pVM->iom.s.cMovsMaxBytes = cTransfers << SIZE_2_SHIFT(cb);
2N/A#endif
2N/A
2N/A/** @todo re-evaluate on page boundraries. */
2N/A
2N/A RTGCPHYS Phys = GCPhysFault;
2N/A int rc;
2N/A if (uErrorCode & X86_TRAP_PF_RW)
2N/A {
2N/A /*
2N/A * Write operation: [Mem] -> [MMIO]
2N/A * ds:esi (Virt Src) -> es:edi (Phys Dst)
2N/A */
2N/A STAM_PROFILE_START(&pVM->iom.s.StatGCInstMovsToMMIO, a2);
2N/A
2N/A /* Check callback. */
2N/A if (!pRange->CTXALLSUFF(pfnWriteCallback))
2N/A {
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsToMMIO, a2);
2N/A return VINF_IOM_HC_MMIO_WRITE;
2N/A }
2N/A
2N/A /* Convert source address ds:esi. */
2N/A RTGCUINTPTR pu8Virt;
2N/A rc = SELMToFlatEx(pVM, pRegFrame->eflags, pRegFrame->ds, (RTGCPTR)pRegFrame->esi, &pRegFrame->dsHid,
2N/A SELMTOFLAT_FLAGS_HYPER | SELMTOFLAT_FLAGS_NO_PL,
2N/A (PRTGCPTR)&pu8Virt, NULL);
2N/A if (VBOX_SUCCESS(rc))
2N/A {
2N/A
2N/A /* Access verification first; we currently can't recover properly from traps inside this instruction */
2N/A rc = PGMVerifyAccess(pVM, pu8Virt, cTransfers * cb, (cpl == 3) ? X86_PTE_US : 0);
2N/A if (rc != VINF_SUCCESS)
2N/A {
2N/A Log(("MOVS will generate a trap -> recompiler, rc=%d\n", rc));
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsToMMIO, a2);
2N/A return VINF_EM_RAW_EMULATE_INSTR;
2N/A }
2N/A
2N/A#ifdef IN_GC
2N/A MMGCRamRegisterTrapHandler(pVM);
2N/A#endif
2N/A
2N/A /* copy loop. */
2N/A while (cTransfers)
2N/A {
2N/A uint32_t u32Data = 0;
2N/A rc = iomRamRead(pVM, &u32Data, (RTGCPTR)pu8Virt, cb);
2N/A if (rc != VINF_SUCCESS)
2N/A break;
2N/A rc = iomMMIODoWrite(pVM, pRange, Phys, &u32Data, cb);
2N/A if (rc != VINF_SUCCESS)
2N/A break;
2N/A
2N/A pu8Virt += offIncrement;
2N/A Phys += offIncrement;
2N/A pRegFrame->esi += offIncrement;
2N/A pRegFrame->edi += offIncrement;
2N/A cTransfers--;
2N/A }
2N/A#ifdef IN_GC
2N/A MMGCRamDeregisterTrapHandler(pVM);
2N/A#endif
2N/A /* Update ecx. */
2N/A if (pCpu->prefix & PREFIX_REP)
2N/A pRegFrame->ecx = cTransfers;
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsToMMIO, a2);
2N/A }
2N/A else
2N/A rc = VINF_IOM_HC_MMIO_READ_WRITE;
2N/A }
2N/A else
2N/A {
2N/A /*
2N/A * Read operation: [MMIO] -> [mem] or [MMIO] -> [MMIO]
2N/A * ds:[eSI] (Phys Src) -> es:[eDI] (Virt Dst)
2N/A */
2N/A /* Check callback. */
2N/A if (!pRange->pfnReadCallback)
2N/A return VINF_IOM_HC_MMIO_READ;
2N/A
2N/A /* Convert destination address. */
2N/A RTGCUINTPTR pu8Virt;
2N/A rc = SELMToFlatEx(pVM, pRegFrame->eflags, pRegFrame->es, (RTGCPTR)pRegFrame->edi, &pRegFrame->esHid,
2N/A SELMTOFLAT_FLAGS_HYPER | SELMTOFLAT_FLAGS_NO_PL,
2N/A (RTGCPTR *)&pu8Virt, NULL);
2N/A if (VBOX_FAILURE(rc))
2N/A return VINF_EM_RAW_GUEST_TRAP;
2N/A
2N/A /* Check if destination address is MMIO. */
2N/A PIOMMMIORANGE pMMIODst;
2N/A RTGCPHYS PhysDst;
2N/A rc = PGMGstGetPage(pVM, (RTGCPTR)pu8Virt, NULL, &PhysDst);
2N/A PhysDst |= (RTGCUINTPTR)pu8Virt & PAGE_OFFSET_MASK;
2N/A if ( VBOX_SUCCESS(rc)
2N/A && (pMMIODst = iomMMIOGetRange(&pVM->iom.s, PhysDst)))
2N/A {
2N/A /*
2N/A * Extra: [MMIO] -> [MMIO]
2N/A */
2N/A STAM_PROFILE_START(&pVM->iom.s.StatGCInstMovsMMIO, d);
2N/A STAM_PROFILE_START(&pVM->iom.s.StatGCInstMovsFromMMIO, c);
2N/A
2N/A if (!pMMIODst->CTXALLSUFF(pfnWriteCallback) && pMMIODst->pfnWriteCallbackR3)
2N/A {
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsMMIO, d);
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsFromMMIO, c);
2N/A return VINF_IOM_HC_MMIO_READ_WRITE;
2N/A }
2N/A
2N/A /* copy loop. */
2N/A while (cTransfers)
2N/A {
2N/A uint32_t u32Data;
2N/A rc = iomMMIODoRead(pVM, pRange, Phys, &u32Data, cb);
2N/A if (rc != VINF_SUCCESS)
2N/A break;
2N/A rc = iomMMIODoWrite(pVM, pMMIODst, PhysDst, &u32Data, cb);
2N/A if (rc != VINF_SUCCESS)
2N/A break;
2N/A
2N/A Phys += offIncrement;
2N/A PhysDst += offIncrement;
2N/A pRegFrame->esi += offIncrement;
2N/A pRegFrame->edi += offIncrement;
2N/A cTransfers--;
2N/A }
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsMMIO, d);
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsFromMMIO, c);
2N/A }
2N/A else
2N/A {
2N/A /*
2N/A * Normal: [MMIO] -> [Mem]
2N/A */
2N/A STAM_PROFILE_START(&pVM->iom.s.StatGCInstMovsFromMMIO, c);
2N/A
2N/A /* Access verification first; we currently can't recover properly from traps inside this instruction */
2N/A rc = PGMVerifyAccess(pVM, pu8Virt, cTransfers * cb, X86_PTE_RW | ((cpl == 3) ? X86_PTE_US : 0));
2N/A if (rc != VINF_SUCCESS)
2N/A {
2N/A Log(("MOVS will generate a trap -> recompiler, rc=%d\n", rc));
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsFromMMIO, c);
2N/A return VINF_EM_RAW_EMULATE_INSTR;
2N/A }
2N/A
2N/A /* copy loop. */
2N/A#ifdef IN_GC
2N/A MMGCRamRegisterTrapHandler(pVM);
2N/A#endif
2N/A while (cTransfers)
2N/A {
2N/A uint32_t u32Data;
2N/A rc = iomMMIODoRead(pVM, pRange, Phys, &u32Data, cb);
2N/A if (rc != VINF_SUCCESS)
2N/A break;
2N/A rc = iomRamWrite(pVM, (RTGCPTR)pu8Virt, &u32Data, cb);
2N/A if (rc != VINF_SUCCESS)
2N/A {
2N/A Log(("iomRamWrite %08X size=%d failed with %d\n", pu8Virt, cb, rc));
2N/A break;
2N/A }
2N/A
2N/A pu8Virt += offIncrement;
2N/A Phys += offIncrement;
2N/A pRegFrame->esi += offIncrement;
2N/A pRegFrame->edi += offIncrement;
2N/A cTransfers--;
2N/A }
2N/A#ifdef IN_GC
2N/A MMGCRamDeregisterTrapHandler(pVM);
2N/A#endif
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovsFromMMIO, c);
2N/A }
2N/A
2N/A /* Update ecx on exit. */
2N/A if (pCpu->prefix & PREFIX_REP)
2N/A pRegFrame->ecx = cTransfers;
2N/A }
2N/A
2N/A /* work statistics. */
2N/A if (rc == VINF_SUCCESS)
2N/A {
2N/A iomMMIOStatLength(pVM, cb);
2N/A }
2N/A return rc;
2N/A}
2N/A#endif
2N/A
2N/A
2N/A
2N/A/**
2N/A * [REP] STOSB
2N/A * [REP] STOSW
2N/A * [REP] STOSD
2N/A *
2N/A * Restricted implementation.
2N/A *
2N/A *
2N/A * @returns VBox status code.
2N/A *
2N/A * @param pVM The virtual machine (GC pointer ofcourse).
2N/A * @param pRegFrame Trap register frame.
2N/A * @param GCPhysFault The GC physical address corresponding to pvFault.
2N/A * @param pCpu Disassembler CPU state.
2N/A * @param pRange Pointer MMIO range.
2N/A */
2N/Astatic int iomInterpretSTOS(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
2N/A{
2N/A /*
2N/A * We do not support segment prefixes or REPNE..
2N/A */
2N/A if (pCpu->prefix & (PREFIX_SEG | PREFIX_REPNE))
2N/A return VINF_IOM_HC_MMIO_READ_WRITE; /** @todo -> REM instead of HC */
2N/A
2N/A /*
2N/A * Get bytes/words/dwords count to copy.
2N/A */
2N/A uint32_t cTransfers = 1;
2N/A if (pCpu->prefix & PREFIX_REP)
2N/A {
2N/A cTransfers = pRegFrame->ecx;
2N/A if (!SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
2N/A cTransfers &= 0xffff;
2N/A
2N/A if (!cTransfers)
2N/A return VINF_SUCCESS;
2N/A }
2N/A
2N/A /*
2N/A * Get data size.
2N/A */
2N/A unsigned cb = DISGetParamSize(pCpu, &pCpu->param1);
2N/A Assert(cb);
2N/A int offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cb : (signed)cb;
2N/A
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A if (pVM->iom.s.cStosMaxBytes < (cTransfers << SIZE_2_SHIFT(cb)))
2N/A pVM->iom.s.cStosMaxBytes = cTransfers << SIZE_2_SHIFT(cb);
2N/A#endif
2N/A
2N/A
2N/A RTGCPHYS Phys = GCPhysFault;
2N/A uint32_t u32Data = pRegFrame->eax;
2N/A int rc;
2N/A if (pRange->CTXALLSUFF(pfnFillCallback))
2N/A {
2N/A /*
2N/A * Use the fill callback.
2N/A */
2N/A /** @todo pfnFillCallback must return number of bytes successfully written!!! */
2N/A if (offIncrement > 0)
2N/A {
2N/A /* addr++ variant. */
2N/A rc = pRange->CTXALLSUFF(pfnFillCallback)(pRange->CTXALLSUFF(pDevIns), pRange->CTXALLSUFF(pvUser), Phys, u32Data, cb, cTransfers);
2N/A if (rc == VINF_SUCCESS)
2N/A {
2N/A /* Update registers. */
2N/A pRegFrame->edi += cTransfers << SIZE_2_SHIFT(cb);
2N/A if (pCpu->prefix & PREFIX_REP)
2N/A pRegFrame->ecx = 0;
2N/A }
2N/A }
2N/A else
2N/A {
2N/A /* addr-- variant. */
2N/A rc = pRange->CTXALLSUFF(pfnFillCallback)(pRange->CTXALLSUFF(pDevIns), pRange->CTXALLSUFF(pvUser), (Phys - (cTransfers - 1)) << SIZE_2_SHIFT(cb), u32Data, cb, cTransfers);
2N/A if (rc == VINF_SUCCESS)
2N/A {
2N/A /* Update registers. */
2N/A pRegFrame->edi -= cTransfers << SIZE_2_SHIFT(cb);
2N/A if (pCpu->prefix & PREFIX_REP)
2N/A pRegFrame->ecx = 0;
2N/A }
2N/A }
2N/A }
2N/A else
2N/A {
2N/A /*
2N/A * Use the write callback.
2N/A */
2N/A Assert(pRange->CTXALLSUFF(pfnWriteCallback) || !pRange->pfnWriteCallbackR3);
2N/A
2N/A /* fill loop. */
2N/A do
2N/A {
2N/A rc = iomMMIODoWrite(pVM, pRange, Phys, &u32Data, cb);
2N/A if (rc != VINF_SUCCESS)
2N/A break;
2N/A
2N/A Phys += offIncrement;
2N/A pRegFrame->edi += offIncrement;
2N/A cTransfers--;
2N/A } while (cTransfers);
2N/A
2N/A /* Update ecx on exit. */
2N/A if (pCpu->prefix & PREFIX_REP)
2N/A pRegFrame->ecx = cTransfers;
2N/A }
2N/A
2N/A /*
2N/A * Work statistics and return.
2N/A */
2N/A if (rc == VINF_SUCCESS)
2N/A iomMMIOStatLength(pVM, cb);
2N/A return rc;
2N/A}
2N/A
2N/A
2N/A/**
2N/A * [REP] LODSB
2N/A * [REP] LODSW
2N/A * [REP] LODSD
2N/A *
2N/A * Restricted implementation.
2N/A *
2N/A *
2N/A * @returns VBox status code.
2N/A *
2N/A * @param pVM The virtual machine (GC pointer ofcourse).
2N/A * @param pRegFrame Trap register frame.
2N/A * @param GCPhysFault The GC physical address corresponding to pvFault.
2N/A * @param pCpu Disassembler CPU state.
2N/A * @param pRange Pointer MMIO range.
2N/A */
2N/Astatic int iomInterpretLODS(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
2N/A{
2N/A Assert(pRange->CTXALLSUFF(pfnReadCallback) || !pRange->pfnReadCallbackR3);
2N/A
2N/A /*
2N/A * We do not support segment prefixes or REP*.
2N/A */
2N/A if (pCpu->prefix & (PREFIX_SEG | PREFIX_REP | PREFIX_REPNE))
2N/A return VINF_IOM_HC_MMIO_READ_WRITE; /** @todo -> REM instead of HC */
2N/A
2N/A /*
2N/A * Get data size.
2N/A */
2N/A unsigned cb = DISGetParamSize(pCpu, &pCpu->param2);
2N/A Assert(cb);
2N/A int offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cb : (signed)cb;
2N/A
2N/A /*
2N/A * Perform read.
2N/A */
2N/A int rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &pRegFrame->eax, cb);
2N/A if (rc == VINF_SUCCESS)
2N/A pRegFrame->esi += offIncrement;
2N/A
2N/A /*
2N/A * Work statistics and return.
2N/A */
2N/A if (rc == VINF_SUCCESS)
2N/A iomMMIOStatLength(pVM, cb);
2N/A return rc;
2N/A}
2N/A
2N/A
2N/A/**
2N/A * CMP [MMIO], reg|imm
2N/A * CMP reg|imm, [MMIO]
2N/A *
2N/A * Restricted implementation.
2N/A *
2N/A *
2N/A * @returns VBox status code.
2N/A *
2N/A * @param pVM The virtual machine (GC pointer ofcourse).
2N/A * @param pRegFrame Trap register frame.
2N/A * @param GCPhysFault The GC physical address corresponding to pvFault.
2N/A * @param pCpu Disassembler CPU state.
2N/A * @param pRange Pointer MMIO range.
2N/A */
2N/Astatic int iomInterpretCMP(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
2N/A{
2N/A Assert(pRange->CTXALLSUFF(pfnReadCallback) || !pRange->pfnReadCallbackR3);
2N/A
2N/A /*
2N/A * Get the operands.
2N/A */
2N/A unsigned cb = 0;
2N/A uint32_t uData1;
2N/A uint32_t uData2;
2N/A int rc;
2N/A if (iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cb))
2N/A /* cmp reg, [MMIO]. */
2N/A rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cb);
2N/A else if (iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cb))
2N/A /* cmp [MMIO], reg|imm. */
2N/A rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cb);
2N/A else
2N/A {
2N/A AssertMsgFailed(("Disassember CMP problem..\n"));
2N/A rc = VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
2N/A }
2N/A
2N/A if (rc == VINF_SUCCESS)
2N/A {
2N/A /* Emulate CMP and update guest flags. */
2N/A uint32_t eflags = EMEmulateCmp(uData1, uData2, cb);
2N/A pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
2N/A | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
2N/A iomMMIOStatLength(pVM, cb);
2N/A }
2N/A
2N/A return rc;
2N/A}
2N/A
2N/A
2N/A/**
2N/A * AND [MMIO], reg|imm
2N/A * AND reg, [MMIO]
2N/A *
2N/A * Restricted implementation.
2N/A *
2N/A *
2N/A * @returns VBox status code.
2N/A *
2N/A * @param pVM The virtual machine (GC pointer ofcourse).
2N/A * @param pRegFrame Trap register frame.
2N/A * @param GCPhysFault The GC physical address corresponding to pvFault.
2N/A * @param pCpu Disassembler CPU state.
2N/A * @param pRange Pointer MMIO range.
2N/A */
2N/Astatic int iomInterpretAND(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
2N/A{
2N/A unsigned cb = 0;
2N/A uint32_t uData1;
2N/A uint32_t uData2;
2N/A bool fAndWrite;
2N/A int rc;
2N/A if (iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cb))
2N/A {
2N/A /* and reg, [MMIO]. */
2N/A Assert(pRange->CTXALLSUFF(pfnReadCallback) || !pRange->pfnReadCallbackR3);
2N/A fAndWrite = false;
2N/A rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cb);
2N/A }
2N/A else if (iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cb))
2N/A {
2N/A /* and [MMIO], reg|imm. */
2N/A fAndWrite = true;
2N/A if ( (pRange->CTXALLSUFF(pfnReadCallback) || !pRange->pfnReadCallbackR3)
2N/A && (pRange->CTXALLSUFF(pfnWriteCallback) || !pRange->pfnWriteCallbackR3))
2N/A rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cb);
2N/A else
2N/A rc = VINF_IOM_HC_MMIO_READ_WRITE;
2N/A }
2N/A else
2N/A {
2N/A AssertMsgFailed(("Disassember AND problem..\n"));
2N/A return VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
2N/A }
2N/A
2N/A if (rc == VINF_SUCCESS)
2N/A {
2N/A /* Emulate AND and update guest flags. */
2N/A uint32_t eflags = EMEmulateAnd(&uData1, uData2, cb);
2N/A if (fAndWrite)
2N/A /* Store result to MMIO. */
2N/A rc = iomMMIODoWrite(pVM, pRange, GCPhysFault, &uData1, cb);
2N/A else
2N/A {
2N/A /* Store result to register. */
2N/A bool fRc = iomSaveDataToReg(pCpu, &pCpu->param1, pRegFrame, uData1);
2N/A AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
2N/A }
2N/A if (rc == VINF_SUCCESS)
2N/A {
2N/A /* Update guest's eflags and finish. */
2N/A pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
2N/A | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
2N/A iomMMIOStatLength(pVM, cb);
2N/A }
2N/A }
2N/A
2N/A return rc;
2N/A}
2N/A
2N/A
2N/A
2N/A/**
2N/A * TEST [MMIO], reg|imm
2N/A * TEST reg, [MMIO]
2N/A *
2N/A * Restricted implementation.
2N/A *
2N/A *
2N/A * @returns VBox status code.
2N/A *
2N/A * @param pVM The virtual machine (GC pointer ofcourse).
2N/A * @param pRegFrame Trap register frame.
2N/A * @param GCPhysFault The GC physical address corresponding to pvFault.
2N/A * @param pCpu Disassembler CPU state.
2N/A * @param pRange Pointer MMIO range.
2N/A */
2N/Astatic int iomInterpretTEST(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
2N/A{
2N/A Assert(pRange->CTXALLSUFF(pfnReadCallback) || !pRange->pfnReadCallbackR3);
2N/A
2N/A unsigned cb = 0;
2N/A uint32_t uData1;
2N/A uint32_t uData2;
2N/A int rc;
2N/A
2N/A if (iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cb))
2N/A {
2N/A /* and test, [MMIO]. */
2N/A rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cb);
2N/A }
2N/A else if (iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cb))
2N/A {
2N/A /* test [MMIO], reg|imm. */
2N/A rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cb);
2N/A }
2N/A else
2N/A {
2N/A AssertMsgFailed(("Disassember TEST problem..\n"));
2N/A return VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
2N/A }
2N/A
2N/A if (rc == VINF_SUCCESS)
2N/A {
2N/A /* Emulate TEST (=AND without write back) and update guest EFLAGS. */
2N/A uint32_t eflags = EMEmulateAnd(&uData1, uData2, cb);
2N/A pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
2N/A | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
2N/A iomMMIOStatLength(pVM, cb);
2N/A }
2N/A
2N/A return rc;
2N/A}
2N/A
2N/A/**
2N/A * XCHG [MMIO], reg
2N/A * XCHG reg, [MMIO]
2N/A *
2N/A * Restricted implementation.
2N/A *
2N/A *
2N/A * @returns VBox status code.
2N/A *
2N/A * @param pVM The virtual machine (GC pointer ofcourse).
2N/A * @param pRegFrame Trap register frame.
2N/A * @param GCPhysFault The GC physical address corresponding to pvFault.
2N/A * @param pCpu Disassembler CPU state.
2N/A * @param pRange Pointer MMIO range.
2N/A */
2N/Astatic int iomInterpretXCHG(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, PDISCPUSTATE pCpu, PIOMMMIORANGE pRange)
2N/A{
2N/A /* Check for read & write handlers since IOMMMIOHandler doesn't cover this. */
2N/A if ( (!pRange->CTXALLSUFF(pfnReadCallback) && pRange->pfnReadCallbackR3)
2N/A || (!pRange->CTXALLSUFF(pfnWriteCallback) && pRange->pfnWriteCallbackR3))
2N/A return VINF_IOM_HC_MMIO_READ_WRITE;
2N/A
2N/A int rc;
2N/A unsigned cb = 0;
2N/A uint32_t uData1;
2N/A uint32_t uData2;
2N/A if (iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &uData1, &cb))
2N/A {
2N/A /* xchg reg, [MMIO]. */
2N/A rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData2, cb);
2N/A if (rc == VINF_SUCCESS)
2N/A {
2N/A /* Store result to MMIO. */
2N/A rc = iomMMIODoWrite(pVM, pRange, GCPhysFault, &uData1, cb);
2N/A
2N/A if (rc == VINF_SUCCESS)
2N/A {
2N/A /* Store result to register. */
2N/A bool fRc = iomSaveDataToReg(pCpu, &pCpu->param1, pRegFrame, uData2);
2N/A AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
2N/A }
2N/A else
2N/A Assert(rc == VINF_IOM_HC_MMIO_WRITE || rc == VINF_PATM_HC_MMIO_PATCH_WRITE);
2N/A }
2N/A else
2N/A Assert(rc == VINF_IOM_HC_MMIO_READ || rc == VINF_PATM_HC_MMIO_PATCH_READ);
2N/A }
2N/A else if (iomGetRegImmData(pCpu, &pCpu->param2, pRegFrame, &uData2, &cb))
2N/A {
2N/A /* xchg [MMIO], reg. */
2N/A rc = iomMMIODoRead(pVM, pRange, GCPhysFault, &uData1, cb);
2N/A if (rc == VINF_SUCCESS)
2N/A {
2N/A /* Store result to MMIO. */
2N/A rc = iomMMIODoWrite(pVM, pRange, GCPhysFault, &uData2, cb);
2N/A if (rc == VINF_SUCCESS)
2N/A {
2N/A /* Store result to register. */
2N/A bool fRc = iomSaveDataToReg(pCpu, &pCpu->param2, pRegFrame, uData1);
2N/A AssertMsg(fRc, ("Failed to store register value!\n")); NOREF(fRc);
2N/A }
2N/A else
2N/A Assert(rc == VINF_IOM_HC_MMIO_WRITE || rc == VINF_PATM_HC_MMIO_PATCH_WRITE);
2N/A }
2N/A else
2N/A Assert(rc == VINF_IOM_HC_MMIO_READ || rc == VINF_PATM_HC_MMIO_PATCH_READ);
2N/A }
2N/A else
2N/A {
2N/A AssertMsgFailed(("Disassember XCHG problem..\n"));
2N/A rc = VERR_IOM_MMIO_HANDLER_DISASM_ERROR;
2N/A }
2N/A return rc;
2N/A}
2N/A
2N/A
2N/A/**
2N/A * \#PF Handler callback for MMIO ranges.
2N/A * Note: we are on ring0 in Hypervisor and interrupts are disabled.
2N/A *
2N/A * @returns VBox status code (appropriate for GC return).
2N/A * @param pVM VM Handle.
2N/A * @param uErrorCode CPU Error code.
2N/A * @param pCtxCore Trap register frame.
2N/A * @param pvFault The fault address (cr2).
2N/A * @param GCPhysFault The GC physical address corresponding to pvFault.
2N/A * @param pvUser Pointer to the MMIO ring-3 range entry.
2N/A */
2N/AIOMDECL(int) IOMMMIOHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pCtxCore, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser)
2N/A{
2N/A STAM_PROFILE_START(&pVM->iom.s.StatGCMMIOHandler, a);
2N/A Log3(("IOMMMIOHandler: GCPhys=%RGp uErr=%#x pvFault=%p eip=%RGv\n",
2N/A GCPhysFault, uErrorCode, pvFault, pCtxCore->eip));
2N/A
2N/A PIOMMMIORANGE pRange = (PIOMMMIORANGE)pvUser;
2N/A Assert(pRange);
2N/A Assert(pRange == iomMMIOGetRange(&pVM->iom.s, GCPhysFault));
2N/A
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A /*
2N/A * Locate the statistics, if > PAGE_SIZE we'll use the first byte for everything.
2N/A */
2N/A PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhysFault, pRange);
2N/A if (!pStats)
2N/A {
2N/A# ifdef IN_RING3
2N/A return VERR_NO_MEMORY;
2N/A# else
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCMMIOHandler, a);
2N/A STAM_COUNTER_INC(&pVM->iom.s.StatGCMMIOFailures);
2N/A return uErrorCode & X86_TRAP_PF_RW ? VINF_IOM_HC_MMIO_WRITE : VINF_IOM_HC_MMIO_READ;
2N/A# endif
2N/A }
2N/A#endif
2N/A
2N/A#ifndef IN_RING3
2N/A /*
2N/A * Should we defer the request right away?
2N/A */
2N/A if (uErrorCode & X86_TRAP_PF_RW
2N/A ? !pRange->CTXALLSUFF(pfnWriteCallback) && !pRange->pfnWriteCallbackR3
2N/A : !pRange->CTXALLSUFF(pfnReadCallback) && !pRange->pfnReadCallbackR3)
2N/A {
2N/A# ifdef VBOX_WITH_STATISTICS
2N/A if (uErrorCode & X86_TRAP_PF_RW)
2N/A STAM_COUNTER_INC(&pStats->CTXALLMID(Write,ToR3));
2N/A else
2N/A STAM_COUNTER_INC(&pStats->CTXALLMID(Read,ToR3));
2N/A# endif
2N/A
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCMMIOHandler, a);
2N/A STAM_COUNTER_INC(&pVM->iom.s.StatGCMMIOFailures);
2N/A return uErrorCode & X86_TRAP_PF_RW ? VINF_IOM_HC_MMIO_WRITE : VINF_IOM_HC_MMIO_READ;
2N/A }
2N/A#endif /* !IN_RING3 */
2N/A
2N/A /*
2N/A * Disassemble the instruction and interprete it.
2N/A */
2N/A DISCPUSTATE Cpu;
2N/A unsigned cbOp;
2N/A int rc = EMInterpretDisasOne(pVM, pCtxCore, &Cpu, &cbOp);
2N/A AssertRCReturn(rc, rc);
2N/A switch (Cpu.pCurInstr->opcode)
2N/A {
2N/A case OP_MOV:
2N/A case OP_MOVZX:
2N/A case OP_MOVSX:
2N/A {
2N/A STAM_PROFILE_START(&pVM->iom.s.StatGCInstMov, b);
2N/A if (uErrorCode & X86_TRAP_PF_RW)
2N/A rc = iomInterpretMOVxXWrite(pVM, pCtxCore, &Cpu, pRange, GCPhysFault);
2N/A else
2N/A rc = iomInterpretMOVxXRead(pVM, pCtxCore, &Cpu, pRange, GCPhysFault);
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMov, b);
2N/A break;
2N/A }
2N/A
2N/A
2N/A#ifdef iom_MOVS_SUPPORT
2N/A case OP_MOVSB:
2N/A case OP_MOVSWD:
2N/A STAM_PROFILE_START(&pVM->iom.s.StatGCInstMovs, c);
2N/A rc = iomInterpretMOVS(pVM, uErrorCode, pCtxCore, GCPhysFault, &Cpu, pRange);
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstMovs, c);
2N/A break;
2N/A#endif
2N/A
2N/A case OP_STOSB:
2N/A case OP_STOSWD:
2N/A Assert(uErrorCode & X86_TRAP_PF_RW);
2N/A STAM_PROFILE_START(&pVM->iom.s.StatGCInstStos, d);
2N/A rc = iomInterpretSTOS(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstStos, d);
2N/A break;
2N/A
2N/A case OP_LODSB:
2N/A case OP_LODSWD:
2N/A Assert(!(uErrorCode & X86_TRAP_PF_RW));
2N/A STAM_PROFILE_START(&pVM->iom.s.StatGCInstLods, e);
2N/A rc = iomInterpretLODS(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstLods, e);
2N/A break;
2N/A
2N/A case OP_CMP:
2N/A Assert(!(uErrorCode & X86_TRAP_PF_RW));
2N/A STAM_PROFILE_START(&pVM->iom.s.StatGCInstCmp, f);
2N/A rc = iomInterpretCMP(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstCmp, f);
2N/A break;
2N/A
2N/A case OP_AND:
2N/A STAM_PROFILE_START(&pVM->iom.s.StatGCInstAnd, g);
2N/A rc = iomInterpretAND(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstAnd, g);
2N/A break;
2N/A
2N/A case OP_TEST:
2N/A Assert(!(uErrorCode & X86_TRAP_PF_RW));
2N/A STAM_PROFILE_START(&pVM->iom.s.StatGCInstTest, h);
2N/A rc = iomInterpretTEST(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstTest, h);
2N/A break;
2N/A
2N/A case OP_XCHG:
2N/A STAM_PROFILE_START(&pVM->iom.s.StatGCInstXchg, i);
2N/A rc = iomInterpretXCHG(pVM, pCtxCore, GCPhysFault, &Cpu, pRange);
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCInstXchg, i);
2N/A break;
2N/A
2N/A
2N/A /*
2N/A * The instruction isn't supported. Hand it on to ring-3.
2N/A */
2N/A default:
2N/A STAM_COUNTER_INC(&pVM->iom.s.StatGCInstOther);
2N/A rc = (uErrorCode & X86_TRAP_PF_RW) ? VINF_IOM_HC_MMIO_WRITE : VINF_IOM_HC_MMIO_READ;
2N/A break;
2N/A }
2N/A
2N/A /*
2N/A * On success advance EIP.
2N/A */
2N/A if (rc == VINF_SUCCESS)
2N/A pCtxCore->eip += cbOp;
2N/A else
2N/A {
2N/A STAM_COUNTER_INC(&pVM->iom.s.StatGCMMIOFailures);
2N/A#if defined(VBOX_WITH_STATISTICS) && !defined(IN_RING3)
2N/A switch (rc)
2N/A {
2N/A case VINF_IOM_HC_MMIO_READ:
2N/A case VINF_IOM_HC_MMIO_READ_WRITE:
2N/A STAM_COUNTER_INC(&pStats->CTXALLMID(Read,ToR3));
2N/A break;
2N/A case VINF_IOM_HC_MMIO_WRITE:
2N/A STAM_COUNTER_INC(&pStats->CTXALLMID(Write,ToR3));
2N/A break;
2N/A }
2N/A#endif
2N/A }
2N/A
2N/A STAM_PROFILE_STOP(&pVM->iom.s.StatGCMMIOHandler, a);
2N/A return rc;
2N/A}
2N/A
2N/A
2N/A/**
2N/A * Reads a MMIO register.
2N/A *
2N/A * @returns VBox status code.
2N/A *
2N/A * @param pVM VM handle.
2N/A * @param GCPhys The physical address to read.
2N/A * @param pu32Value Where to store the value read.
2N/A * @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes.
2N/A */
2N/AIOMDECL(int) IOMMMIORead(PVM pVM, RTGCPHYS GCPhys, uint32_t *pu32Value, size_t cbValue)
2N/A{
2N/A /*
2N/A * Lookup the current context range node and statistics.
2N/A */
2N/A PIOMMMIORANGE pRange = iomMMIOGetRange(&pVM->iom.s, GCPhys);
2N/A AssertMsgReturn(pRange,
2N/A ("Handlers and page tables are out of sync or something! GCPhys=%VGp cbValue=%d\n", GCPhys, cbValue),
2N/A VERR_INTERNAL_ERROR);
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhys, pRange);
2N/A if (!pStats)
2N/A# ifdef IN_RING3
2N/A return VERR_NO_MEMORY;
2N/A# else
2N/A return VINF_IOM_HC_MMIO_READ;
2N/A# endif
2N/A#endif /* VBOX_WITH_STATISTICS */
2N/A if (pRange->CTXALLSUFF(pfnReadCallback))
2N/A {
2N/A /*
2N/A * Perform the read and deal with the result.
2N/A */
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A if (pStats)
2N/A STAM_PROFILE_ADV_START(&pStats->CTXALLSUFF(ProfRead), a);
2N/A#endif
2N/A int rc = pRange->CTXALLSUFF(pfnReadCallback)(pRange->CTXALLSUFF(pDevIns), pRange->CTXALLSUFF(pvUser), GCPhys, pu32Value, cbValue);
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A if (pStats)
2N/A STAM_PROFILE_ADV_STOP(&pStats->CTXALLSUFF(ProfRead), a);
2N/A if (pStats && rc != VINF_IOM_HC_MMIO_READ)
2N/A STAM_COUNTER_INC(&pStats->CTXALLSUFF(Read));
2N/A#endif
2N/A switch (rc)
2N/A {
2N/A case VINF_SUCCESS:
2N/A default:
2N/A Log4(("IOMMMIORead: GCPhys=%RGp *pu32=%08RX32 cb=%d rc=%Vrc\n", GCPhys, *pu32Value, cbValue, rc));
2N/A return rc;
2N/A
2N/A case VINF_IOM_MMIO_UNUSED_00:
2N/A switch (cbValue)
2N/A {
2N/A case 1: *(uint8_t *)pu32Value = 0x00; break;
2N/A case 2: *(uint16_t *)pu32Value = 0x0000; break;
2N/A case 4: *(uint32_t *)pu32Value = 0x00000000; break;
2N/A default: AssertReleaseMsgFailed(("cbValue=%d GCPhys=%VGp\n", cbValue, GCPhys)); break;
2N/A }
2N/A Log4(("IOMMMIORead: GCPhys=%RGp *pu32=%08RX32 cb=%d rc=%Vrc\n", GCPhys, *pu32Value, cbValue, rc));
2N/A return VINF_SUCCESS;
2N/A
2N/A case VINF_IOM_MMIO_UNUSED_FF:
2N/A switch (cbValue)
2N/A {
2N/A case 1: *(uint8_t *)pu32Value = 0xff; break;
2N/A case 2: *(uint16_t *)pu32Value = 0xffff; break;
2N/A case 4: *(uint32_t *)pu32Value = 0xffffffff; break;
2N/A default: AssertReleaseMsgFailed(("cbValue=%d GCPhys=%VGp\n", cbValue, GCPhys)); break;
2N/A }
2N/A Log4(("IOMMMIORead: GCPhys=%RGp *pu32=%08RX32 cb=%d rc=%Vrc\n", GCPhys, *pu32Value, cbValue, rc));
2N/A return VINF_SUCCESS;
2N/A }
2N/A }
2N/A#ifndef IN_RING3
2N/A if (pRange->pfnReadCallbackR3)
2N/A {
2N/A STAM_COUNTER_INC(&pStats->CTXALLMID(Read,ToR3));
2N/A return VINF_IOM_HC_MMIO_READ;
2N/A }
2N/A#endif
2N/A
2N/A /*
2N/A * Lookup the ring-3 range.
2N/A */
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A if (pStats)
2N/A STAM_COUNTER_INC(&pStats->CTXALLSUFF(Read));
2N/A#endif
2N/A *pu32Value = 0;
2N/A Log4(("IOMMMIORead: GCPhys=%RGp *pu32=%08RX32 cb=%d rc=VINF_SUCCESS\n", GCPhys, *pu32Value, cbValue));
2N/A return VINF_SUCCESS;
2N/A}
2N/A
2N/A
2N/A/**
2N/A * Writes to a MMIO register.
2N/A *
2N/A * @returns VBox status code.
2N/A *
2N/A * @param pVM VM handle.
2N/A * @param GCPhys The physical address to write to.
2N/A * @param u32Value The value to write.
2N/A * @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes.
2N/A */
2N/AIOMDECL(int) IOMMMIOWrite(PVM pVM, RTGCPHYS GCPhys, uint32_t u32Value, size_t cbValue)
2N/A{
2N/A /*
2N/A * Lookup the current context range node.
2N/A */
2N/A PIOMMMIORANGE pRange = iomMMIOGetRange(&pVM->iom.s, GCPhys);
2N/A AssertMsgReturn(pRange,
2N/A ("Handlers and page tables are out of sync or something! GCPhys=%VGp cbValue=%d\n", GCPhys, cbValue),
2N/A VERR_INTERNAL_ERROR);
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A PIOMMMIOSTATS pStats = iomMMIOGetStats(&pVM->iom.s, GCPhys, pRange);
2N/A if (!pStats)
2N/A# ifdef IN_RING3
2N/A return VERR_NO_MEMORY;
2N/A# else
2N/A return VINF_IOM_HC_MMIO_WRITE;
2N/A# endif
2N/A#endif /* VBOX_WITH_STATISTICS */
2N/A
2N/A /*
2N/A * Perform the write if there's a write handler. R0/GC may have
2N/A * to defer it to ring-3.
2N/A */
2N/A if (pRange->CTXALLSUFF(pfnWriteCallback))
2N/A {
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A if (pStats)
2N/A STAM_PROFILE_ADV_START(&pStats->CTXALLSUFF(ProfWrite), a);
2N/A#endif
2N/A int rc = pRange->CTXALLSUFF(pfnWriteCallback)(pRange->CTXALLSUFF(pDevIns), pRange->CTXALLSUFF(pvUser), GCPhys, &u32Value, cbValue);
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A if (pStats)
2N/A STAM_PROFILE_ADV_STOP(&pStats->CTXALLSUFF(ProfWrite), a);
2N/A if (pStats && rc != VINF_IOM_HC_MMIO_WRITE)
2N/A STAM_COUNTER_INC(&pStats->CTXALLSUFF(Write));
2N/A#endif
2N/A Log4(("IOMMMIOWrite: GCPhys=%RGp u32=%08RX32 cb=%d rc=%Vrc\n", GCPhys, u32Value, cbValue, rc));
2N/A return rc;
2N/A }
2N/A#ifndef IN_RING3
2N/A if (pRange->pfnWriteCallbackR3)
2N/A {
2N/A STAM_COUNTER_INC(&pStats->CTXALLMID(Write,ToR3));
2N/A return VINF_IOM_HC_MMIO_WRITE;
2N/A }
2N/A#endif
2N/A
2N/A /*
2N/A * No write handler, nothing to do.
2N/A */
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A if (pStats)
2N/A STAM_COUNTER_INC(&pStats->CTXALLSUFF(Write));
2N/A#endif
2N/A Log4(("IOMMMIOWrite: GCPhys=%RGp u32=%08RX32 cb=%d rc=%Vrc\n", GCPhys, u32Value, cbValue, VINF_SUCCESS));
2N/A return VINF_SUCCESS;
2N/A}
2N/A
2N/A
2N/A/**
2N/A * [REP*] INSB/INSW/INSD
2N/A * ES:EDI,DX[,ECX]
2N/A *
2N/A * @remark Assumes caller checked the access privileges (IOMInterpretCheckPortIOAccess)
2N/A *
2N/A * @returns Strict VBox status code. Informational status codes other than the one documented
2N/A * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2N/A * @retval VINF_SUCCESS Success.
2N/A * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2N/A * status code must be passed on to EM.
2N/A * @retval VINF_IOM_HC_IOPORT_READ Defer the read to ring-3. (R0/GC only)
2N/A * @retval VINF_EM_RAW_EMULATE_INSTR Defer the read to the REM.
2N/A * @retval VINF_EM_RAW_GUEST_TRAP The exception was left pending. (TRPMRaiseXcptErr)
2N/A * @retval VINF_TRPM_XCPT_DISPATCHED The exception was raised and dispatched for raw-mode execution. (TRPMRaiseXcptErr)
2N/A * @retval VINF_EM_RESCHEDULE_REM The exception was dispatched and cannot be executed in raw-mode. (TRPMRaiseXcptErr)
2N/A *
2N/A * @param pVM The virtual machine (GC pointer ofcourse).
2N/A * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
2N/A * @param uPort IO Port
2N/A * @param uPrefix IO instruction prefix
2N/A * @param cbTransfer Size of transfer unit
2N/A */
2N/AIOMDECL(int) IOMInterpretINSEx(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, uint32_t cbTransfer)
2N/A{
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A STAM_COUNTER_INC(&pVM->iom.s.StatGCInstIns);
2N/A#endif
2N/A
2N/A /*
2N/A * We do not support REPNE or decrementing destination
2N/A * pointer. Segment prefixes are deliberately ignored, as per the instruction specification.
2N/A */
2N/A if ( (uPrefix & PREFIX_REPNE)
2N/A || pRegFrame->eflags.Bits.u1DF)
2N/A return VINF_EM_RAW_EMULATE_INSTR;
2N/A
2N/A /*
2N/A * Get bytes/words/dwords count to transfer.
2N/A */
2N/A RTGCUINTREG cTransfers = 1;
2N/A if (uPrefix & PREFIX_REP)
2N/A {
2N/A cTransfers = pRegFrame->ecx;
2N/A
2N/A if (!SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
2N/A cTransfers &= 0xffff;
2N/A
2N/A if (!cTransfers)
2N/A return VINF_SUCCESS;
2N/A }
2N/A
2N/A /* Convert destination address es:edi. */
2N/A RTGCPTR GCPtrDst;
2N/A int rc = SELMToFlatEx(pVM, pRegFrame->eflags, pRegFrame->es, (RTGCPTR)pRegFrame->edi, &pRegFrame->esHid,
2N/A SELMTOFLAT_FLAGS_HYPER | SELMTOFLAT_FLAGS_NO_PL,
2N/A &GCPtrDst, NULL);
2N/A if (VBOX_FAILURE(rc))
2N/A {
2N/A Log(("INS destination address conversion failed -> fallback, rc=%d\n", rc));
2N/A return VINF_EM_RAW_EMULATE_INSTR;
2N/A }
2N/A
2N/A /* Access verification first; we can't recover from traps inside this instruction, as the port read cannot be repeated. */
2N/A uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2N/A
2N/A rc = PGMVerifyAccess(pVM, (RTGCUINTPTR)GCPtrDst, cTransfers * cbTransfer,
2N/A X86_PTE_RW | ((cpl == 3) ? X86_PTE_US : 0));
2N/A if (rc != VINF_SUCCESS)
2N/A {
2N/A Log(("INS will generate a trap -> fallback, rc=%d\n", rc));
2N/A return VINF_EM_RAW_EMULATE_INSTR;
2N/A }
2N/A
2N/A Log(("IOM: rep ins%d port %#x count %d\n", cbTransfer * 8, uPort, cTransfers));
2N/A if (cTransfers > 1)
2N/A {
2N/A /* If the device supports string transfers, ask it to do as
2N/A * much as it wants. The rest is done with single-word transfers. */
2N/A const RTGCUINTREG cTransfersOrg = cTransfers;
2N/A rc = IOMIOPortReadString(pVM, uPort, &GCPtrDst, &cTransfers, cbTransfer);
2N/A AssertRC(rc); Assert(cTransfers <= cTransfersOrg);
2N/A pRegFrame->edi += (cTransfersOrg - cTransfers) * cbTransfer;
2N/A }
2N/A
2N/A#ifdef IN_GC
2N/A MMGCRamRegisterTrapHandler(pVM);
2N/A#endif
2N/A
2N/A while (cTransfers && rc == VINF_SUCCESS)
2N/A {
2N/A uint32_t u32Value;
2N/A rc = IOMIOPortRead(pVM, uPort, &u32Value, cbTransfer);
2N/A if (!IOM_SUCCESS(rc))
2N/A break;
2N/A int rc2 = iomRamWrite(pVM, GCPtrDst, &u32Value, cbTransfer);
2N/A Assert(rc2 == VINF_SUCCESS); NOREF(rc2);
2N/A GCPtrDst = (RTGCPTR)((RTGCUINTPTR)GCPtrDst + cbTransfer);
2N/A pRegFrame->edi += cbTransfer;
2N/A cTransfers--;
2N/A }
2N/A#ifdef IN_GC
2N/A MMGCRamDeregisterTrapHandler(pVM);
2N/A#endif
2N/A
2N/A /* Update ecx on exit. */
2N/A if (uPrefix & PREFIX_REP)
2N/A pRegFrame->ecx = cTransfers;
2N/A
2N/A AssertMsg(rc == VINF_SUCCESS || rc == VINF_IOM_HC_IOPORT_READ || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST) || VBOX_FAILURE(rc), ("%Vrc\n", rc));
2N/A return rc;
2N/A}
2N/A
2N/A
2N/A/**
2N/A * [REP*] INSB/INSW/INSD
2N/A * ES:EDI,DX[,ECX]
2N/A *
2N/A * @returns Strict VBox status code. Informational status codes other than the one documented
2N/A * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2N/A * @retval VINF_SUCCESS Success.
2N/A * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2N/A * status code must be passed on to EM.
2N/A * @retval VINF_IOM_HC_IOPORT_READ Defer the read to ring-3. (R0/GC only)
2N/A * @retval VINF_EM_RAW_EMULATE_INSTR Defer the read to the REM.
2N/A * @retval VINF_EM_RAW_GUEST_TRAP The exception was left pending. (TRPMRaiseXcptErr)
2N/A * @retval VINF_TRPM_XCPT_DISPATCHED The exception was raised and dispatched for raw-mode execution. (TRPMRaiseXcptErr)
2N/A * @retval VINF_EM_RESCHEDULE_REM The exception was dispatched and cannot be executed in raw-mode. (TRPMRaiseXcptErr)
2N/A *
2N/A * @param pVM The virtual machine (GC pointer ofcourse).
2N/A * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
2N/A * @param pCpu Disassembler CPU state.
2N/A */
2N/AIOMDECL(int) IOMInterpretINS(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu)
2N/A{
2N/A /*
2N/A * Get port number directly from the register (no need to bother the
2N/A * disassembler). And get the I/O register size from the opcode / prefix.
2N/A */
2N/A RTIOPORT Port = pRegFrame->edx & 0xffff;
2N/A unsigned cb = 0;
2N/A if (pCpu->pCurInstr->opcode == OP_INSB)
2N/A cb = 1;
2N/A else
2N/A cb = pCpu->opmode == CPUMODE_32BIT ? 4 : 2;
2N/A
2N/A int rc = IOMInterpretCheckPortIOAccess(pVM, pRegFrame, Port, cb);
2N/A if (RT_UNLIKELY(rc != VINF_SUCCESS))
2N/A {
2N/A AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED || rc == VINF_TRPM_XCPT_DISPATCHED || VBOX_FAILURE(rc), ("%Vrc\n", rc));
2N/A return rc;
2N/A }
2N/A
2N/A return IOMInterpretINSEx(pVM, pRegFrame, Port, pCpu->prefix, cb);
2N/A}
2N/A
2N/A
2N/A/**
2N/A * [REP*] OUTSB/OUTSW/OUTSD
2N/A * DS:ESI,DX[,ECX]
2N/A *
2N/A * @remark Assumes caller checked the access privileges (IOMInterpretCheckPortIOAccess)
2N/A *
2N/A * @returns Strict VBox status code. Informational status codes other than the one documented
2N/A * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2N/A * @retval VINF_SUCCESS Success.
2N/A * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2N/A * status code must be passed on to EM.
2N/A * @retval VINF_IOM_HC_IOPORT_WRITE Defer the write to ring-3. (R0/GC only)
2N/A * @retval VINF_EM_RAW_GUEST_TRAP The exception was left pending. (TRPMRaiseXcptErr)
2N/A * @retval VINF_TRPM_XCPT_DISPATCHED The exception was raised and dispatched for raw-mode execution. (TRPMRaiseXcptErr)
2N/A * @retval VINF_EM_RESCHEDULE_REM The exception was dispatched and cannot be executed in raw-mode. (TRPMRaiseXcptErr)
2N/A *
2N/A * @param pVM The virtual machine (GC pointer ofcourse).
2N/A * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
2N/A * @param uPort IO Port
2N/A * @param uPrefix IO instruction prefix
2N/A * @param cbTransfer Size of transfer unit
2N/A */
2N/AIOMDECL(int) IOMInterpretOUTSEx(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uPort, uint32_t uPrefix, uint32_t cbTransfer)
2N/A{
2N/A#ifdef VBOX_WITH_STATISTICS
2N/A STAM_COUNTER_INC(&pVM->iom.s.StatGCInstOuts);
2N/A#endif
2N/A
2N/A /*
2N/A * We do not support segment prefixes, REPNE or
2N/A * decrementing source pointer.
2N/A */
2N/A if ( (uPrefix & (PREFIX_SEG | PREFIX_REPNE))
2N/A || pRegFrame->eflags.Bits.u1DF)
2N/A return VINF_EM_RAW_EMULATE_INSTR;
2N/A
2N/A /*
2N/A * Get bytes/words/dwords count to transfer.
2N/A */
2N/A RTGCUINTREG cTransfers = 1;
2N/A if (uPrefix & PREFIX_REP)
2N/A {
2N/A cTransfers = pRegFrame->ecx;
2N/A if (!SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
2N/A cTransfers &= 0xffff;
2N/A
2N/A if (!cTransfers)
2N/A return VINF_SUCCESS;
2N/A }
2N/A
2N/A /* Convert source address ds:esi. */
2N/A RTGCPTR GCPtrSrc;
2N/A int rc = SELMToFlatEx(pVM, pRegFrame->eflags, pRegFrame->ds, (RTGCPTR)pRegFrame->esi, &pRegFrame->dsHid,
2N/A SELMTOFLAT_FLAGS_HYPER | SELMTOFLAT_FLAGS_NO_PL,
2N/A &GCPtrSrc, NULL);
2N/A if (VBOX_FAILURE(rc))
2N/A {
2N/A Log(("OUTS source address conversion failed -> fallback, rc=%Vrc\n", rc));
2N/A return VINF_EM_RAW_EMULATE_INSTR;
2N/A }
2N/A
2N/A /* Access verification first; we currently can't recover properly from traps inside this instruction */
2N/A uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2N/A rc = PGMVerifyAccess(pVM, (RTGCUINTPTR)GCPtrSrc, cTransfers * cbTransfer,
2N/A (cpl == 3) ? X86_PTE_US : 0);
2N/A if (rc != VINF_SUCCESS)
2N/A {
2N/A Log(("OUTS will generate a trap -> fallback, rc=%Vrc\n", rc));
2N/A return VINF_EM_RAW_EMULATE_INSTR;
2N/A }
2N/A
2N/A Log(("IOM: rep outs%d port %#x count %d\n", cbTransfer * 8, uPort, cTransfers));
2N/A if (cTransfers > 1)
2N/A {
2N/A /*
2N/A * If the device supports string transfers, ask it to do as
2N/A * much as it wants. The rest is done with single-word transfers.
2N/A */
2N/A const RTGCUINTREG cTransfersOrg = cTransfers;
2N/A rc = IOMIOPortWriteString(pVM, uPort, &GCPtrSrc, &cTransfers, cbTransfer);
2N/A AssertRC(rc); Assert(cTransfers <= cTransfersOrg);
2N/A pRegFrame->esi += (cTransfersOrg - cTransfers) * cbTransfer;
2N/A }
2N/A
2N/A#ifdef IN_GC
2N/A MMGCRamRegisterTrapHandler(pVM);
2N/A#endif
2N/A
2N/A while (cTransfers && rc == VINF_SUCCESS)
2N/A {
2N/A uint32_t u32Value;
2N/A rc = iomRamRead(pVM, &u32Value, GCPtrSrc, cbTransfer);
2N/A if (rc != VINF_SUCCESS)
2N/A break;
2N/A rc = IOMIOPortWrite(pVM, uPort, u32Value, cbTransfer);
2N/A if (!IOM_SUCCESS(rc))
2N/A break;
2N/A GCPtrSrc = (RTGCPTR)((RTUINTPTR)GCPtrSrc + cbTransfer);
2N/A pRegFrame->esi += cbTransfer;
2N/A cTransfers--;
2N/A }
2N/A
2N/A#ifdef IN_GC
2N/A MMGCRamDeregisterTrapHandler(pVM);
2N/A#endif
2N/A
2N/A /* Update ecx on exit. */
2N/A if (uPrefix & PREFIX_REP)
2N/A pRegFrame->ecx = cTransfers;
2N/A
2N/A AssertMsg(rc == VINF_SUCCESS || rc == VINF_IOM_HC_IOPORT_WRITE || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST) || VBOX_FAILURE(rc), ("%Vrc\n", rc));
2N/A return rc;
2N/A}
2N/A
2N/A
2N/A/**
2N/A * [REP*] OUTSB/OUTSW/OUTSD
2N/A * DS:ESI,DX[,ECX]
2N/A *
2N/A * @returns Strict VBox status code. Informational status codes other than the one documented
2N/A * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2N/A * @retval VINF_SUCCESS Success.
2N/A * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2N/A * status code must be passed on to EM.
2N/A * @retval VINF_IOM_HC_IOPORT_WRITE Defer the write to ring-3. (R0/GC only)
2N/A * @retval VINF_EM_RAW_EMULATE_INSTR Defer the write to the REM.
2N/A * @retval VINF_EM_RAW_GUEST_TRAP The exception was left pending. (TRPMRaiseXcptErr)
2N/A * @retval VINF_TRPM_XCPT_DISPATCHED The exception was raised and dispatched for raw-mode execution. (TRPMRaiseXcptErr)
2N/A * @retval VINF_EM_RESCHEDULE_REM The exception was dispatched and cannot be executed in raw-mode. (TRPMRaiseXcptErr)
2N/A *
2N/A * @param pVM The virtual machine (GC pointer ofcourse).
2N/A * @param pRegFrame Pointer to CPUMCTXCORE guest registers structure.
2N/A * @param pCpu Disassembler CPU state.
2N/A */
2N/AIOMDECL(int) IOMInterpretOUTS(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu)
2N/A{
2N/A /*
2N/A * Get port number from the first parameter.
2N/A * And get the I/O register size from the opcode / prefix.
2N/A */
2N/A uint32_t Port = 0;
2N/A unsigned cb = 0;
2N/A bool fRc = iomGetRegImmData(pCpu, &pCpu->param1, pRegFrame, &Port, &cb);
2N/A AssertMsg(fRc, ("Failed to get reg/imm port number!\n")); NOREF(fRc);
2N/A if (pCpu->pCurInstr->opcode == OP_OUTSB)
2N/A cb = 1;
2N/A else
2N/A cb = (pCpu->opmode == CPUMODE_32BIT) ? 4 : 2;
2N/A
2N/A int rc = IOMInterpretCheckPortIOAccess(pVM, pRegFrame, Port, cb);
2N/A if (RT_UNLIKELY(rc != VINF_SUCCESS))
2N/A {
2N/A AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED || rc == VINF_TRPM_XCPT_DISPATCHED || VBOX_FAILURE(rc), ("%Vrc\n", rc));
2N/A return rc;
2N/A }
2N/A
2N/A return IOMInterpretOUTSEx(pVM, pRegFrame, Port, pCpu->prefix, cb);
2N/A}
2N/A
2N/A