2N/A; IEM - Instruction Implementation in Assembly.
2N/A; Copyright (C) 2011-2012 Oracle Corporation
2N/A; This file is part of VirtualBox Open Source Edition (OSE), as
2N/A; you can redistribute it
and/or modify it under the terms of the GNU
2N/A; General Public License (GPL) as published by the Free Software
2N/A; Foundation, in version 2 as it comes in the "COPYING" file of the
2N/A; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
2N/A; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
2N/A;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2N/A;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2N/A;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2N/A; Defined Constants And Macros ;
2N/A;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2N/A; RET XX / RET wrapper for fastcall.
2N/A%macro RET_FASTCALL 1
2N/A %ifdef RT_OS_WINDOWS
2N/A; NAME for fastcall functions.
2N/A;; @todo 'global @fastcall@12' is still broken in yasm and requires dollar
2N/A; escaping (or whatever the dollar is good for here). Thus the ugly
2N/A%define NAME_FASTCALL(a_Name, a_cbArgs, a_Prefix) NAME(a_Name)
2N/A %ifdef RT_OS_WINDOWS
2N/A %undef NAME_FASTCALL
2N/A %define NAME_FASTCALL(a_Name, a_cbArgs, a_Prefix) a_Prefix %+ a_Name %+ @ %+ a_cbArgs
2N/A; BEGINPROC for fastcall functions.
2N/A; @param 1 The function name (C).
2N/A; @param 2 The argument size on x86.
2N/A%macro BEGINPROC_FASTCALL 2
2N/A %ifdef ASM_FORMAT_PE
2N/A export %1=NAME_FASTCALL(%1,%2,$@)
2N/A %ifdef ASM_FORMAT_OMF
2N/A export NAME(%1) NAME_FASTCALL(%1,%2,$@)
2N/A %ifndef ASM_FORMAT_BIN
2N/A global NAME_FASTCALL(%1,%2,$@)
2N/ANAME_FASTCALL(%1,%2,@):
2N/A; We employ some macro assembly here to hid the calling convention differences.
2N/A %macro PROLOGUE_1_ARGS 0
2N/A %macro EPILOGUE_1_ARGS 0
2N/A %macro EPILOGUE_1_ARGS_EX 0
2N/A %macro PROLOGUE_2_ARGS 0
2N/A %macro EPILOGUE_2_ARGS 0
2N/A %macro EPILOGUE_2_ARGS_EX 1
2N/A %macro PROLOGUE_3_ARGS 0
2N/A %macro EPILOGUE_3_ARGS 0
2N/A %macro EPILOGUE_3_ARGS_EX 1
2N/A %macro PROLOGUE_4_ARGS 0
2N/A %macro EPILOGUE_4_ARGS 0
2N/A %macro EPILOGUE_4_ARGS_EX 1
2N/A %ifdef ASM_CALL64_GCC
%macro EPILOGUE_1_ARGS_EX 1
%macro EPILOGUE_2_ARGS_EX 1
%macro EPILOGUE_3_ARGS_EX 1
%error "With three args, at least 4 bytes must be remove from the stack upon return (32-bit)."
mov ebx, [esp + 12 + 4 + 0]
mov esi, [esp + 12 + 4 + 4]
%macro EPILOGUE_4_ARGS_EX 1
%error "With four args, at least 8 bytes must be remove from the stack upon return (32-bit)."
; Load the relevant flags from [%1] if there are undefined flags (%3).
; @remarks Clobbers T0, stack. Changes EFLAGS.
; @param A2 The register pointing to the flags.
; @param 1 The parameter (
A0..A3) pointing to the eflags.
; @param 2 The set of modified flags.
; @param 3 The set of undefined flags.
%macro IEM_MAYBE_LOAD_FLAGS 3
pushf ; store current flags
mov T0_32, [%1] ; load the guest flags
and dword [xSP], ~(%2 | %3) ; mask out the modified and undefined flags
and T0_32, (%2 | %3) ; select the modified and undefined flags.
or [xSP], T0 ; merge guest flags with host flags.
popf ; load the mixed flags.
; @remarks Clobbers T0, T1, stack.
; @param 1 The register pointing to the EFLAGS.
; @param 2 The mask of modified flags to save.
; @param 3 The mask of undefined flags to (maybe) save.
and T0_32, ~(%2 | %3) ; clear the modified & undefined flags.
and T1_32, (%2 | %3) ; select the modified and undefined flags.
or T0_32, T1_32 ; combine the flags.
mov [%1], T0_32 ; save the flags.
; Macro for implementing a binary operator.
; This will generate code for the 8, 16, 32 and 64 bit accesses with locked
; variants, except on 32-bit system where the 64-bit accesses requires hand
; All the functions takes a pointer to the destination memory operand in A0,
; the source register operand in A1 and a pointer to eflags in A2.
; @param 1 The instruction mnemonic.
; @param 2 Non-zero if there should be a locked version.
; @param 3 The modified flags.
; @param 4 The undefined flags.
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8, 12
IEM_MAYBE_LOAD_FLAGS A2, %3, %4
IEM_SAVE_FLAGS A2, %3, %4
ENDPROC iemAImpl_ %+ %1 %+ _u8
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
IEM_MAYBE_LOAD_FLAGS A2, %3, %4
IEM_SAVE_FLAGS A2, %3, %4
ENDPROC iemAImpl_ %+ %1 %+ _u16
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
IEM_MAYBE_LOAD_FLAGS A2, %3, %4
IEM_SAVE_FLAGS A2, %3, %4
ENDPROC iemAImpl_ %+ %1 %+ _u32
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
IEM_MAYBE_LOAD_FLAGS A2, %3, %4
IEM_SAVE_FLAGS A2, %3, %4
ENDPROC iemAImpl_ %+ %1 %+ _u64
%else ; stub it for now - later, replace with hand coded stuff.
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
ENDPROC iemAImpl_ %+ %1 %+ _u64
%if %2 != 0 ; locked versions requested?
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8_locked, 12
IEM_MAYBE_LOAD_FLAGS A2, %3, %4
IEM_SAVE_FLAGS A2, %3, %4
ENDPROC iemAImpl_ %+ %1 %+ _u8_locked
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16_locked, 12
IEM_MAYBE_LOAD_FLAGS A2, %3, %4
IEM_SAVE_FLAGS A2, %3, %4
ENDPROC iemAImpl_ %+ %1 %+ _u16_locked
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32_locked, 12
IEM_MAYBE_LOAD_FLAGS A2, %3, %4
lock %1 dword [A0], A1_32
IEM_SAVE_FLAGS A2, %3, %4
ENDPROC iemAImpl_ %+ %1 %+ _u32_locked
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 16
IEM_MAYBE_LOAD_FLAGS A2, %3, %4
IEM_SAVE_FLAGS A2, %3, %4
ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
%else ; stub it for now - later, replace with hand coded stuff.
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 16
ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
; instr,lock,modified-flags.
IEMIMPL_BIN_OP add, 1, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEMIMPL_BIN_OP adc, 1, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEMIMPL_BIN_OP sub, 1, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEMIMPL_BIN_OP sbb, 1, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEMIMPL_BIN_OP or, 1, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), X86_EFL_AF,
IEMIMPL_BIN_OP xor, 1, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), X86_EFL_AF,
IEMIMPL_BIN_OP and, 1, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), X86_EFL_AF,
IEMIMPL_BIN_OP cmp, 0, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEMIMPL_BIN_OP test, 0, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), X86_EFL_AF,
; Macro for implementing a bit operator.
; This will generate code for the 16, 32 and 64 bit accesses with locked
; variants, except on 32-bit system where the 64-bit accesses requires hand
; All the functions takes a pointer to the destination memory operand in A0,
; the source register operand in A1 and a pointer to eflags in A2.
; @param 1 The instruction mnemonic.
; @param 2 Non-zero if there should be a locked version.
; @param 3 The modified flags.
; @param 4 The undefined flags.
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
IEM_MAYBE_LOAD_FLAGS A2, %3, %4
IEM_SAVE_FLAGS A2, %3, %4
ENDPROC iemAImpl_ %+ %1 %+ _u16
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
IEM_MAYBE_LOAD_FLAGS A2, %3, %4
IEM_SAVE_FLAGS A2, %3, %4
ENDPROC iemAImpl_ %+ %1 %+ _u32
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
IEM_MAYBE_LOAD_FLAGS A2, %3, %4
IEM_SAVE_FLAGS A2, %3, %4
ENDPROC iemAImpl_ %+ %1 %+ _u64
%else ; stub it for now - later, replace with hand coded stuff.
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
ENDPROC iemAImpl_ %+ %1 %+ _u64
%if %2 != 0 ; locked versions requested?
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16_locked, 12
IEM_MAYBE_LOAD_FLAGS A2, %3, %4
IEM_SAVE_FLAGS A2, %3, %4
ENDPROC iemAImpl_ %+ %1 %+ _u16_locked
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32_locked, 12
IEM_MAYBE_LOAD_FLAGS A2, %3, %4
lock %1 dword [A0], A1_32
IEM_SAVE_FLAGS A2, %3, %4
ENDPROC iemAImpl_ %+ %1 %+ _u32_locked
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 16
IEM_MAYBE_LOAD_FLAGS A2, %3, %4
IEM_SAVE_FLAGS A2, %3, %4
ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
%else ; stub it for now - later, replace with hand coded stuff.
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 16
ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
IEMIMPL_BIT_OP bt, 0, (X86_EFL_CF), (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
IEMIMPL_BIT_OP btc, 1, (X86_EFL_CF), (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
IEMIMPL_BIT_OP bts, 1, (X86_EFL_CF), (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
IEMIMPL_BIT_OP btr, 1, (X86_EFL_CF), (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
; Macro for implementing a bit search operator.
; This will generate code for the 16, 32 and 64 bit accesses, except on 32-bit
; system where the 64-bit accesses requires hand coding.
; All the functions takes a pointer to the destination memory operand in A0,
; the source register operand in A1 and a pointer to eflags in A2.
; @param 1 The instruction mnemonic.
; @param 2 The modified flags.
; @param 3 The undefined flags.
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
IEM_MAYBE_LOAD_FLAGS A2, %2, %3
IEM_SAVE_FLAGS A2, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u16
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
IEM_MAYBE_LOAD_FLAGS A2, %2, %3
IEM_SAVE_FLAGS A2, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u32
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
IEM_MAYBE_LOAD_FLAGS A2, %2, %3
IEM_SAVE_FLAGS A2, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u64
%else ; stub it for now - later, replace with hand coded stuff.
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
ENDPROC iemAImpl_ %+ %1 %+ _u64
IEMIMPL_BIT_OP bsf, (X86_EFL_ZF), (X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF)
IEMIMPL_BIT_OP bsr, (X86_EFL_ZF), (X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF)
; IMUL is also a similar but yet different case (no lock, no mem dst).
; The rDX:rAX variant of imul is handled together with mul further down.
BEGINPROC_FASTCALL iemAImpl_imul_two_u16, 12
IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
ENDPROC iemAImpl_imul_two_u16
BEGINPROC_FASTCALL iemAImpl_imul_two_u32, 12
IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
ENDPROC iemAImpl_imul_two_u32
BEGINPROC_FASTCALL iemAImpl_imul_two_u64, 16
IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
int3 ;; @todo implement me
ENDPROC iemAImpl_imul_two_u64
; XCHG for memory operands. This implies locking. No flag changes.
; Each function takes two arguments, first the pointer to the memory,
; then the pointer to the register. They all return void.
BEGINPROC_FASTCALL iemAImpl_xchg_u8, 8
BEGINPROC_FASTCALL iemAImpl_xchg_u16, 8
ENDPROC iemAImpl_xchg_u16
BEGINPROC_FASTCALL iemAImpl_xchg_u32, 8
ENDPROC iemAImpl_xchg_u32
BEGINPROC_FASTCALL iemAImpl_xchg_u64, 8
ENDPROC iemAImpl_xchg_u64
; XADD for memory operands.
; Each function takes three arguments, first the pointer to the
;
memory/register, then the pointer to the register, and finally a pointer to
; eflags. They all return void.
BEGINPROC_FASTCALL iemAImpl_xadd_u8, 12
IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
BEGINPROC_FASTCALL iemAImpl_xadd_u16, 12
IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
ENDPROC iemAImpl_xadd_u16
BEGINPROC_FASTCALL iemAImpl_xadd_u32, 12
IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
ENDPROC iemAImpl_xadd_u32
BEGINPROC_FASTCALL iemAImpl_xadd_u64, 12
IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
ENDPROC iemAImpl_xadd_u64
BEGINPROC_FASTCALL iemAImpl_xadd_u8_locked, 12
IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
ENDPROC iemAImpl_xadd_u8_locked
BEGINPROC_FASTCALL iemAImpl_xadd_u16_locked, 12
IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
ENDPROC iemAImpl_xadd_u16_locked
BEGINPROC_FASTCALL iemAImpl_xadd_u32_locked, 12
IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
ENDPROC iemAImpl_xadd_u32_locked
BEGINPROC_FASTCALL iemAImpl_xadd_u64_locked, 12
IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
ENDPROC iemAImpl_xadd_u64_locked
; These are tricky register wise, so the code is duplicated for each calling
; WARNING! This code make ASSUMPTIONS about which registers T1 and T0 are mapped to!
; IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
BEGINPROC_FASTCALL iemAImpl_cmpxchg8b, 16
mov r11, rdx ; pu64EaxEdx (is also T1)
IEM_MAYBE_LOAD_FLAGS r9, (X86_EFL_ZF), 0 ; clobbers T0 (eax)
IEM_SAVE_FLAGS r9, (X86_EFL_ZF), 0 ; clobbers T0+T1 (eax, r11)
mov r11, rdx ; pu64EbxEcx (is also T1)
IEM_MAYBE_LOAD_FLAGS r10, (X86_EFL_ZF), 0 ; clobbers T0 (eax)
IEM_SAVE_FLAGS r10, (X86_EFL_ZF), 0 ; clobbers T0+T1 (eax, r11)
mov esi, edx ; pu64EaxEdx
mov ecx, [esp + 16 + 4 + 0] ; pu64EbxEcx
mov ebp, [esp + 16 + 4 + 4] ; pEFlags
IEM_MAYBE_LOAD_FLAGS ebp, (X86_EFL_ZF), 0 ; clobbers T0 (eax)
IEM_SAVE_FLAGS ebp, (X86_EFL_ZF), 0 ; clobbers T0+T1 (eax, edi)
ENDPROC iemAImpl_cmpxchg8b
BEGINPROC_FASTCALL iemAImpl_cmpxchg8b_locked, 16
; Lazy bird always lock prefixes cmpxchg8b.
jmp NAME_FASTCALL(iemAImpl_cmpxchg8b,16,$@)
ENDPROC iemAImpl_cmpxchg8b_locked
; WARNING! This code make ASSUMPTIONS about which registers T1 and T0 are mapped to!
; IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg,(uintX_t *puXDst, uintX_t puEax, uintX_t uReg, uint32_t *pEFlags));
BEGINPROC_FASTCALL iemAImpl_cmpxchg_u8 %+ %2, 16
IEM_MAYBE_LOAD_FLAGS A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0 ; clobbers T0 (eax)
IEM_SAVE_FLAGS A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0 ; clobbers T0+T1 (eax,
r11/edi)
ENDPROC iemAImpl_cmpxchg_u8 %+ %2
BEGINPROC_FASTCALL iemAImpl_cmpxchg_u16 %+ %2, 16
IEM_MAYBE_LOAD_FLAGS A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0 ; clobbers T0 (eax)
IEM_SAVE_FLAGS A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0 ; clobbers T0+T1 (eax,
r11/edi)
ENDPROC iemAImpl_cmpxchg_u16 %+ %2
BEGINPROC_FASTCALL iemAImpl_cmpxchg_u32 %+ %2, 16
IEM_MAYBE_LOAD_FLAGS A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0 ; clobbers T0 (eax)
IEM_SAVE_FLAGS A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0 ; clobbers T0+T1 (eax,
r11/edi)
ENDPROC iemAImpl_cmpxchg_u32 %+ %2
BEGINPROC_FASTCALL iemAImpl_cmpxchg_u64 %+ %2, 16
IEM_MAYBE_LOAD_FLAGS A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0 ; clobbers T0 (eax)
IEM_SAVE_FLAGS A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0 ; clobbers T0+T1 (eax,
r11/edi)
; Must use cmpxchg8b here. See also iemAImpl_cmpxchg8b.
mov ecx, [esp + 16 + 4 + 0] ; pu64Reg - Note! Pointer on 32-bit hosts!
mov ebp, [esp + 16 + 4 + 4] ; pEFlags
IEM_MAYBE_LOAD_FLAGS ebp, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0 ; clobbers T0 (eax)
; cmpxchg8b doesn't set CF, PF, AF, SF and OF, so we have to do that.
cmp eax, eax ; just set the other flags.
IEM_SAVE_FLAGS ebp, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0 ; clobbers T0+T1 (eax, edi)
cmp [esi + 4], edx ;; @todo FIXME - verify 64-bit compare implementation
ENDPROC iemAImpl_cmpxchg_u64 %+ %2
%endmacro ; IEMIMPL_CMPXCHG
IEMIMPL_CMPXCHG lock, _locked
; Macro for implementing a unary operator.
; This will generate code for the 8, 16, 32 and 64 bit accesses with locked
; variants, except on 32-bit system where the 64-bit accesses requires hand
; All the functions takes a pointer to the destination memory operand in A0,
; the source register operand in A1 and a pointer to eflags in A2.
; @param 1 The instruction mnemonic.
; @param 2 The modified flags.
; @param 3 The undefined flags.
%macro IEMIMPL_UNARY_OP 3
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8, 8
IEM_MAYBE_LOAD_FLAGS A1, %2, %3
IEM_SAVE_FLAGS A1, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u8
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8_locked, 8
IEM_MAYBE_LOAD_FLAGS A1, %2, %3
IEM_SAVE_FLAGS A1, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u8_locked
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 8
IEM_MAYBE_LOAD_FLAGS A1, %2, %3
IEM_SAVE_FLAGS A1, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u16
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16_locked, 8
IEM_MAYBE_LOAD_FLAGS A1, %2, %3
IEM_SAVE_FLAGS A1, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u16_locked
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 8
IEM_MAYBE_LOAD_FLAGS A1, %2, %3
IEM_SAVE_FLAGS A1, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u32
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32_locked, 8
IEM_MAYBE_LOAD_FLAGS A1, %2, %3
IEM_SAVE_FLAGS A1, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u32_locked
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 8
IEM_MAYBE_LOAD_FLAGS A1, %2, %3
IEM_SAVE_FLAGS A1, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u64
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 8
IEM_MAYBE_LOAD_FLAGS A1, %2, %3
IEM_SAVE_FLAGS A1, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 8
ENDPROC iemAImpl_ %+ %1 %+ _u64
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 8
ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
IEMIMPL_UNARY_OP inc, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF), 0
IEMIMPL_UNARY_OP dec, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF), 0
IEMIMPL_UNARY_OP neg, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEMIMPL_UNARY_OP not, 0, 0
; Macro for implementing memory fence operation.
; No return value, no operands or anything.
; @param 1 The instruction.
%macro IEMIMPL_MEM_FENCE 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1, 0
; Alternative for non-SSE2 host.
BEGINPROC_FASTCALL iemAImpl_alt_mem_fence, 0
ENDPROC iemAImpl_alt_mem_fence
; Macro for implementing a shift operation.
; This will generate code for the 8, 16, 32 and 64 bit accesses, except on
; 32-bit system where the 64-bit accesses requires hand coding.
; All the functions takes a pointer to the destination memory operand in A0,
; the shift count in A1 and a pointer to eflags in A2.
; @param 1 The instruction mnemonic.
; @param 2 The modified flags.
; @param 3 The undefined flags.
; Makes ASSUMPTIONS about A0, A1 and A2 assignments.
%macro IEMIMPL_SHIFT_OP 3
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8, 12
IEM_MAYBE_LOAD_FLAGS A2, %2, %3
IEM_SAVE_FLAGS A2, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u8
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
IEM_MAYBE_LOAD_FLAGS A2, %2, %3
IEM_SAVE_FLAGS A2, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u16
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
IEM_MAYBE_LOAD_FLAGS A2, %2, %3
IEM_SAVE_FLAGS A2, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u32
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 12
IEM_MAYBE_LOAD_FLAGS A2, %2, %3
IEM_SAVE_FLAGS A2, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u64
%else ; stub it for now - later, replace with hand coded stuff.
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 12
ENDPROC iemAImpl_ %+ %1 %+ _u64
IEMIMPL_SHIFT_OP rol, (X86_EFL_OF | X86_EFL_CF), 0
IEMIMPL_SHIFT_OP ror, (X86_EFL_OF | X86_EFL_CF), 0
IEMIMPL_SHIFT_OP rcl, (X86_EFL_OF | X86_EFL_CF), 0
IEMIMPL_SHIFT_OP rcr, (X86_EFL_OF | X86_EFL_CF), 0
IEMIMPL_SHIFT_OP shl, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), (X86_EFL_AF)
IEMIMPL_SHIFT_OP shr, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), (X86_EFL_AF)
IEMIMPL_SHIFT_OP sar, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), (X86_EFL_AF)
; Macro for implementing a double precision shift operation.
; This will generate code for the 16, 32 and 64 bit accesses, except on
; 32-bit system where the 64-bit accesses requires hand coding.
; The functions takes the destination operand (r/m) in A0, the source (reg) in
; @param 1 The instruction mnemonic.
; @param 2 The modified flags.
; @param 3 The undefined flags.
; Makes ASSUMPTIONS about A0, A1, A2 and A3 assignments.
%macro IEMIMPL_SHIFT_DBL_OP 3
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 16
IEM_MAYBE_LOAD_FLAGS A3, %2, %3
IEM_SAVE_FLAGS A3, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u16
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 16
IEM_MAYBE_LOAD_FLAGS A3, %2, %3
IEM_SAVE_FLAGS A3, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u32
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 20
IEM_MAYBE_LOAD_FLAGS A3, %2, %3
IEM_SAVE_FLAGS A3, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u64
%else ; stub it for now - later, replace with hand coded stuff.
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 20
ENDPROC iemAImpl_ %+ %1 %+ _u64
IEMIMPL_SHIFT_DBL_OP shld, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), (X86_EFL_AF)
IEMIMPL_SHIFT_DBL_OP shrd, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), (X86_EFL_AF)
; Macro for implementing a multiplication operations.
; This will generate code for the 8, 16, 32 and 64 bit accesses, except on
; 32-bit system where the 64-bit accesses requires hand coding.
; The 8-bit function only operates on AX, so it takes no DX pointer. The other
; functions takes a pointer to rAX in A0, rDX in A1, the operand in A2 and a
; pointer to eflags in A3.
; The functions all return 0 so the caller can be used for
div/idiv as well as
; @param 1 The instruction mnemonic.
; @param 2 The modified flags.
; @param 3 The undefined flags.
; Makes ASSUMPTIONS about A0, A1, A2, A3, T0 and T1 assignments.
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8, 12
IEM_MAYBE_LOAD_FLAGS A2, %2, %3
IEM_SAVE_FLAGS A2, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u8
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 16
IEM_MAYBE_LOAD_FLAGS A3, %2, %3
IEM_SAVE_FLAGS A3, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u16
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 16
IEM_MAYBE_LOAD_FLAGS A3, %2, %3
IEM_SAVE_FLAGS A3, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u32
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 20
IEM_MAYBE_LOAD_FLAGS A3, %2, %3
IEM_SAVE_FLAGS A3, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u64
IEMIMPL_MUL_OP mul, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
IEMIMPL_MUL_OP imul, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
; Worker function for negating a 32-bit number in T1:T0
iemAImpl_negate_T0_T1_u32:
; Worker function for negating a 64-bit number in T1:T0
iemAImpl_negate_T0_T1_u64:
; Macro for implementing a division operations.
; This will generate code for the 8, 16, 32 and 64 bit accesses, except on
; 32-bit system where the 64-bit accesses requires hand coding.
; The 8-bit function only operates on AX, so it takes no DX pointer. The other
; functions takes a pointer to rAX in A0, rDX in A1, the operand in A2 and a
; pointer to eflags in A3.
; The functions all return 0 on success and -1 if a divide error should be
; @param 1 The instruction mnemonic.
; @param 2 The modified flags.
; @param 3 The undefined flags.
; @param 4 1 if signed, 0 if unsigned.
; Makes ASSUMPTIONS about A0, A1, A2, A3, T0 and T1 assignments.
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8, 12
; Overflow check - unsigned division is simple to verify, haven't
; found a simple way to check signed division yet unfortunately.
mov T0_16, [A0] ; T0 = dividend
mov T1, A1 ; T1 = saved divisor (because of missing T1_8 in 32-bit)
.one_of_each: ; OK range is 2^(result-with - 1) + (divisor - 1).
push T0 ; Start off like unsigned below.
and T0_8, 0x7f ; Special case for covering (divisor - 1).
.both_positive: ; Same as unsigned shifted by sign indicator bit.
mov A1, T1 ; restore divisor
IEM_MAYBE_LOAD_FLAGS A2, %2, %3
IEM_SAVE_FLAGS A2, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u8
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 16
; Overflow check - unsigned division is simple to verify, haven't
; found a simple way to check signed division yet unfortunately.
mov T0_16, [A0] ; T0 = dividend
mov T1, A2 ; T1 = divisor
.one_of_each: ; OK range is 2^(result-with - 1) + (divisor - 1).
push T0 ; Start off like unsigned below.
and T0_16, 0x7fff ; Special case for covering (divisor - 1).
.both_positive: ; Same as unsigned shifted by sign indicator bit.
IEM_MAYBE_LOAD_FLAGS A3, %2, %3
IEM_SAVE_FLAGS A3, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u16
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 16
; Overflow check - unsigned division is simple to verify, haven't
; found a simple way to check signed division yet unfortunately.
push A2 ; save A2 so we modify it (we out of regs on x86).
mov T0_32, [A0] ; T0 = dividend low
mov T1_32, [A1] ; T1 = dividend high
call iemAImpl_negate_T0_T1_u32
.one_of_each: ; OK range is 2^(result-with - 1) + (divisor - 1).
push T0 ; Start off like unsigned below.
and T0_32, 0x7fffffff ; Special case for covering (divisor - 1).
call iemAImpl_negate_T0_T1_u32
.both_positive: ; Same as unsigned shifted by sign indicator bit.
IEM_MAYBE_LOAD_FLAGS A3, %2, %3
IEM_SAVE_FLAGS A3, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u32
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 20
push A2 ; save A2 so we modify it (we out of regs on x86).
mov T0, [A0] ; T0 = dividend low
mov T1, [A1] ; T1 = dividend high
call iemAImpl_negate_T0_T1_u64
.one_of_each: ; OK range is 2^(result-with - 1) + (divisor - 1).
push T0 ; Start off like unsigned below.
mov T1, 0x7fffffffffffffff
and T0, T1 ; Special case for covering (divisor - 1).
call iemAImpl_negate_T0_T1_u64
.both_positive: ; Same as unsigned shifted by sign indicator bit.
IEM_MAYBE_LOAD_FLAGS A3, %2, %3
IEM_SAVE_FLAGS A3, %2, %3
ENDPROC iemAImpl_ %+ %1 %+ _u64
IEMIMPL_DIV_OP div, 0, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
IEMIMPL_DIV_OP idiv, 0, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 1
; BSWAP. No flag changes.
; Each function takes one argument, pointer to the value to bswap
BEGINPROC_FASTCALL iemAImpl_bswap_u16, 4
mov T0_32, [A0] ; just in case any of the upper bits are used.
ENDPROC iemAImpl_bswap_u16
BEGINPROC_FASTCALL iemAImpl_bswap_u32, 4
ENDPROC iemAImpl_bswap_u32
BEGINPROC_FASTCALL iemAImpl_bswap_u64, 4
ENDPROC iemAImpl_bswap_u64
; Initialize the FPU for the actual instruction being emulated, this means
; loading parts of the guest's control word and status word.
; @uses 24 bytes of stack.
; @param 1 Expression giving the address of the FXSTATE of the guest.
%macro FPU_LD_FXSTATE_FCW_AND_SAFE_FSW 1
; FCW - for exception, precision and rounding control.
and T0, X86_FCW_MASK_ALL | X86_FCW_PC_MASK | X86_FCW_RC_MASK
; FSW - for undefined C0, C1, C2, and C3.
; Need to move this as well somewhere better?
; Need to move this as well somewhere better?
;---------------------- 16-bit signed integer operations ----------------------
; Converts a 16-bit floating point value to a 80-bit one (fpu register).
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULT for the output.
; @param A2 Pointer to the 16-bit floating point value to convert.
BEGINPROC_FASTCALL iemAImpl_fild_i16_to_r80, 12
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fild_i16_to_r80
; Store a 80-bit floating point value (register) as a 16-bit signed integer (memory).
; @param A0 FPU context (fxsave).
; @param A1 Where to return the output FSW.
; @param A2 Where to store the 16-bit signed integer value.
; @param A3 Pointer to the 80-bit value.
BEGINPROC_FASTCALL iemAImpl_fist_r80_to_i16, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fist_r80_to_i16
; Store a 80-bit floating point value (register) as a 16-bit signed integer
; (memory) with truncation.
; @param A0 FPU context (fxsave).
; @param A1 Where to return the output FSW.
; @param A2 Where to store the 16-bit signed integer value.
; @param A3 Pointer to the 80-bit value.
BEGINPROC_FASTCALL iemAImpl_fistt_r80_to_i16, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fistt_r80_to_i16
; FPU instruction working on one 80-bit and one 16-bit signed integer value.
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULT for the output.
; @param A2 Pointer to the 80-bit value.
; @param A3 Pointer to the 16-bit value.
%macro IEMIMPL_FPU_R80_BY_I16 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_i16, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80_by_i16
IEMIMPL_FPU_R80_BY_I16 fiadd
IEMIMPL_FPU_R80_BY_I16 fimul
IEMIMPL_FPU_R80_BY_I16 fisub
IEMIMPL_FPU_R80_BY_I16 fisubr
IEMIMPL_FPU_R80_BY_I16 fidiv
IEMIMPL_FPU_R80_BY_I16 fidivr
; FPU instruction working on one 80-bit and one 16-bit signed integer value,
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Where to store the output FSW.
; @param A2 Pointer to the 80-bit value.
; @param A3 Pointer to the 64-bit value.
%macro IEMIMPL_FPU_R80_BY_I16_FSW 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_i16, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80_by_i16
IEMIMPL_FPU_R80_BY_I16_FSW ficom
;---------------------- 32-bit signed integer operations ----------------------
; Converts a 32-bit floating point value to a 80-bit one (fpu register).
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULT for the output.
; @param A2 Pointer to the 32-bit floating point value to convert.
BEGINPROC_FASTCALL iemAImpl_fild_i32_to_r80, 12
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fild_i32_to_r80
; Store a 80-bit floating point value (register) as a 32-bit signed integer (memory).
; @param A0 FPU context (fxsave).
; @param A1 Where to return the output FSW.
; @param A2 Where to store the 32-bit signed integer value.
; @param A3 Pointer to the 80-bit value.
BEGINPROC_FASTCALL iemAImpl_fist_r80_to_i32, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fist_r80_to_i32
; Store a 80-bit floating point value (register) as a 32-bit signed integer
; (memory) with truncation.
; @param A0 FPU context (fxsave).
; @param A1 Where to return the output FSW.
; @param A2 Where to store the 32-bit signed integer value.
; @param A3 Pointer to the 80-bit value.
BEGINPROC_FASTCALL iemAImpl_fistt_r80_to_i32, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fistt_r80_to_i32
; FPU instruction working on one 80-bit and one 32-bit signed integer value.
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULT for the output.
; @param A2 Pointer to the 80-bit value.
; @param A3 Pointer to the 32-bit value.
%macro IEMIMPL_FPU_R80_BY_I32 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_i32, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80_by_i32
IEMIMPL_FPU_R80_BY_I32 fiadd
IEMIMPL_FPU_R80_BY_I32 fimul
IEMIMPL_FPU_R80_BY_I32 fisub
IEMIMPL_FPU_R80_BY_I32 fisubr
IEMIMPL_FPU_R80_BY_I32 fidiv
IEMIMPL_FPU_R80_BY_I32 fidivr
; FPU instruction working on one 80-bit and one 32-bit signed integer value,
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Where to store the output FSW.
; @param A2 Pointer to the 80-bit value.
; @param A3 Pointer to the 64-bit value.
%macro IEMIMPL_FPU_R80_BY_I32_FSW 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_i32, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80_by_i32
IEMIMPL_FPU_R80_BY_I32_FSW ficom
;---------------------- 64-bit signed integer operations ----------------------
; Converts a 64-bit floating point value to a 80-bit one (fpu register).
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULT for the output.
; @param A2 Pointer to the 64-bit floating point value to convert.
BEGINPROC_FASTCALL iemAImpl_fild_i64_to_r80, 12
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fild_i64_to_r80
; Store a 80-bit floating point value (register) as a 64-bit signed integer (memory).
; @param A0 FPU context (fxsave).
; @param A1 Where to return the output FSW.
; @param A2 Where to store the 64-bit signed integer value.
; @param A3 Pointer to the 80-bit value.
BEGINPROC_FASTCALL iemAImpl_fist_r80_to_i64, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fist_r80_to_i64
; Store a 80-bit floating point value (register) as a 64-bit signed integer
; (memory) with truncation.
; @param A0 FPU context (fxsave).
; @param A1 Where to return the output FSW.
; @param A2 Where to store the 64-bit signed integer value.
; @param A3 Pointer to the 80-bit value.
BEGINPROC_FASTCALL iemAImpl_fistt_r80_to_i64, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fistt_r80_to_i64
;---------------------- 32-bit floating point operations ----------------------
; Converts a 32-bit floating point value to a 80-bit one (fpu register).
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULT for the output.
; @param A2 Pointer to the 32-bit floating point value to convert.
BEGINPROC_FASTCALL iemAImpl_fld_r32_to_r80, 12
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fld_r32_to_r80
; Store a 80-bit floating point value (register) as a 32-bit one (memory).
; @param A0 FPU context (fxsave).
; @param A1 Where to return the output FSW.
; @param A2 Where to store the 32-bit value.
; @param A3 Pointer to the 80-bit value.
BEGINPROC_FASTCALL iemAImpl_fst_r80_to_r32, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fst_r80_to_r32
; FPU instruction working on one 80-bit and one 32-bit floating point value.
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULT for the output.
; @param A2 Pointer to the 80-bit value.
; @param A3 Pointer to the 32-bit value.
%macro IEMIMPL_FPU_R80_BY_R32 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r32, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80_by_r32
IEMIMPL_FPU_R80_BY_R32 fadd
IEMIMPL_FPU_R80_BY_R32 fmul
IEMIMPL_FPU_R80_BY_R32 fsub
IEMIMPL_FPU_R80_BY_R32 fsubr
IEMIMPL_FPU_R80_BY_R32 fdiv
IEMIMPL_FPU_R80_BY_R32 fdivr
; FPU instruction working on one 80-bit and one 32-bit floating point value,
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Where to store the output FSW.
; @param A2 Pointer to the 80-bit value.
; @param A3 Pointer to the 64-bit value.
%macro IEMIMPL_FPU_R80_BY_R32_FSW 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r32, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80_by_r32
IEMIMPL_FPU_R80_BY_R32_FSW fcom
;---------------------- 64-bit floating point operations ----------------------
; Converts a 64-bit floating point value to a 80-bit one (fpu register).
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULT for the output.
; @param A2 Pointer to the 64-bit floating point value to convert.
BEGINPROC_FASTCALL iemAImpl_fld_r64_to_r80, 12
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fld_r64_to_r80
; Store a 80-bit floating point value (register) as a 64-bit one (memory).
; @param A0 FPU context (fxsave).
; @param A1 Where to return the output FSW.
; @param A2 Where to store the 64-bit value.
; @param A3 Pointer to the 80-bit value.
BEGINPROC_FASTCALL iemAImpl_fst_r80_to_r64, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fst_r80_to_r64
; FPU instruction working on one 80-bit and one 64-bit floating point value.
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULT for the output.
; @param A2 Pointer to the 80-bit value.
; @param A3 Pointer to the 64-bit value.
%macro IEMIMPL_FPU_R80_BY_R64 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r64, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80_by_r64
IEMIMPL_FPU_R80_BY_R64 fadd
IEMIMPL_FPU_R80_BY_R64 fmul
IEMIMPL_FPU_R80_BY_R64 fsub
IEMIMPL_FPU_R80_BY_R64 fsubr
IEMIMPL_FPU_R80_BY_R64 fdiv
IEMIMPL_FPU_R80_BY_R64 fdivr
; FPU instruction working on one 80-bit and one 64-bit floating point value,
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Where to store the output FSW.
; @param A2 Pointer to the 80-bit value.
; @param A3 Pointer to the 64-bit value.
%macro IEMIMPL_FPU_R80_BY_R64_FSW 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r64, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80_by_r64
IEMIMPL_FPU_R80_BY_R64_FSW fcom
;---------------------- 80-bit floating point operations ----------------------
; Loads a 80-bit floating point register value from memory.
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULT for the output.
; @param A2 Pointer to the 80-bit floating point value to load.
BEGINPROC_FASTCALL iemAImpl_fld_r80_from_r80, 12
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fld_r80_from_r80
; Store a 80-bit floating point register to memory
; @param A0 FPU context (fxsave).
; @param A1 Where to return the output FSW.
; @param A2 Where to store the 80-bit value.
; @param A3 Pointer to the 80-bit register value.
BEGINPROC_FASTCALL iemAImpl_fst_r80_to_r80, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_fst_r80_to_r80
; FPU instruction working on two 80-bit floating point values.
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULT for the output.
; @param A2 Pointer to the first 80-bit value (ST0)
; @param A3 Pointer to the second 80-bit value (STn).
%macro IEMIMPL_FPU_R80_BY_R80 2
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r80, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80_by_r80
IEMIMPL_FPU_R80_BY_R80 fadd, {st0, st1}
IEMIMPL_FPU_R80_BY_R80 fmul, {st0, st1}
IEMIMPL_FPU_R80_BY_R80 fsub, {st0, st1}
IEMIMPL_FPU_R80_BY_R80 fsubr, {st0, st1}
IEMIMPL_FPU_R80_BY_R80 fdiv, {st0, st1}
IEMIMPL_FPU_R80_BY_R80 fdivr, {st0, st1}
IEMIMPL_FPU_R80_BY_R80 fprem, {}
IEMIMPL_FPU_R80_BY_R80 fprem1, {}
IEMIMPL_FPU_R80_BY_R80 fscale, {}
; FPU instruction working on two 80-bit floating point values, ST1 and ST0,
; storing the result in ST1 and popping the stack.
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULT for the output.
; @param A2 Pointer to the first 80-bit value (ST1).
; @param A3 Pointer to the second 80-bit value (ST0).
%macro IEMIMPL_FPU_R80_BY_R80_ST1_ST0_POP 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r80, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80_by_r80
IEMIMPL_FPU_R80_BY_R80_ST1_ST0_POP fpatan
IEMIMPL_FPU_R80_BY_R80_ST1_ST0_POP fyl2xp1
; FPU instruction working on two 80-bit floating point values, only
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a uint16_t for the resulting FSW.
; @param A2 Pointer to the first 80-bit value.
; @param A3 Pointer to the second 80-bit value.
%macro IEMIMPL_FPU_R80_BY_R80_FSW 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r80, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80_by_r80
IEMIMPL_FPU_R80_BY_R80_FSW fcom
IEMIMPL_FPU_R80_BY_R80_FSW fucom
; FPU instruction working on two 80-bit floating point values,
; returning FSW and EFLAGS (eax).
; @param 1 The instruction
; @returns EFLAGS in EAX.
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a uint16_t for the resulting FSW.
; @param A2 Pointer to the first 80-bit value.
; @param A3 Pointer to the second 80-bit value.
%macro IEMIMPL_FPU_R80_BY_R80_EFL 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r80, 16
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80_by_r80
IEMIMPL_FPU_R80_BY_R80_EFL fcomi
IEMIMPL_FPU_R80_BY_R80_EFL fucomi
; FPU instruction working on one 80-bit floating point value.
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULT for the output.
; @param A2 Pointer to the 80-bit value.
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80, 12
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80
; FPU instruction working on one 80-bit floating point value, only
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a uint16_t for the resulting FSW.
; @param A2 Pointer to the 80-bit value.
%macro IEMIMPL_FPU_R80_FSW 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80, 12
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80
; FPU instruction loading a 80-bit floating point constant.
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULT for the output.
%macro IEMIMPL_FPU_R80_CONST 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1, 8
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+
IEMIMPL_FPU_R80_CONST fld1
IEMIMPL_FPU_R80_CONST fldl2t
IEMIMPL_FPU_R80_CONST fldl2e
IEMIMPL_FPU_R80_CONST fldpi
IEMIMPL_FPU_R80_CONST fldlg2
IEMIMPL_FPU_R80_CONST fldln2
IEMIMPL_FPU_R80_CONST fldz
; FPU instruction working on one 80-bit floating point value, outputing two.
; @param 1 The instruction
; @param A0 FPU context (fxsave).
; @param A1 Pointer to a IEMFPURESULTTWO for the output.
; @param A2 Pointer to the 80-bit value.
%macro IEMIMPL_FPU_R80_R80 1
BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_r80, 12
FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ENDPROC iemAImpl_ %+ %1 %+ _r80_r80
IEMIMPL_FPU_R80_R80 fptan
IEMIMPL_FPU_R80_R80 fxtract
IEMIMPL_FPU_R80_R80 fsincos