IEMAllAImpl.asm revision 4edc278439db2c83a5a59a104ec85e379d4c07df
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; IEM - Instruction Implementation in Assembly.
b3eb676cebf5407921b8f535095ca7655edb9db3vboxsync; Copyright (C) 2011-2012 Oracle Corporation
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; This file is part of VirtualBox Open Source Edition (OSE), as
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; available from http://www.virtualbox.org. This file is free software;
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; you can redistribute it and/or modify it under the terms of the GNU
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; General Public License (GPL) as published by the Free Software
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; Foundation, in version 2 as it comes in the "COPYING" file of the
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; Header Files ;
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; Defined Constants And Macros ;
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
032703cba22135d6032705fc2d67dd1294a6491avboxsync; RET XX / RET wrapper for fastcall.
032703cba22135d6032705fc2d67dd1294a6491avboxsync%macro RET_FASTCALL 1
315f68b04971772d94ba6c4408eaa19559a77cedvboxsync%ifdef RT_ARCH_X86
315f68b04971772d94ba6c4408eaa19559a77cedvboxsync %ifdef RT_OS_WINDOWS
032703cba22135d6032705fc2d67dd1294a6491avboxsync; NAME for fastcall functions.
315f68b04971772d94ba6c4408eaa19559a77cedvboxsync;; @todo 'global @fastcall@12' is still broken in yasm and requires dollar
032703cba22135d6032705fc2d67dd1294a6491avboxsync; escaping (or whatever the dollar is good for here). Thus the ugly
032703cba22135d6032705fc2d67dd1294a6491avboxsync; prefix argument.
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync%define NAME_FASTCALL(a_Name, a_cbArgs, a_Prefix) NAME(a_Name)
032703cba22135d6032705fc2d67dd1294a6491avboxsync%ifdef RT_ARCH_X86
315f68b04971772d94ba6c4408eaa19559a77cedvboxsync %ifdef RT_OS_WINDOWS
032703cba22135d6032705fc2d67dd1294a6491avboxsync %undef NAME_FASTCALL
032703cba22135d6032705fc2d67dd1294a6491avboxsync %define NAME_FASTCALL(a_Name, a_cbArgs, a_Prefix) a_Prefix %+ a_Name %+ @ %+ a_cbArgs
032703cba22135d6032705fc2d67dd1294a6491avboxsync; BEGINPROC for fastcall functions.
032703cba22135d6032705fc2d67dd1294a6491avboxsync; @param 1 The function name (C).
032703cba22135d6032705fc2d67dd1294a6491avboxsync; @param 2 The argument size on x86.
032703cba22135d6032705fc2d67dd1294a6491avboxsync%macro BEGINPROC_FASTCALL 2
032703cba22135d6032705fc2d67dd1294a6491avboxsync %ifdef ASM_FORMAT_PE
032703cba22135d6032705fc2d67dd1294a6491avboxsync export %1=NAME_FASTCALL(%1,%2,$@)
032703cba22135d6032705fc2d67dd1294a6491avboxsync %ifdef __NASM__
032703cba22135d6032705fc2d67dd1294a6491avboxsync %ifdef ASM_FORMAT_OMF
032703cba22135d6032705fc2d67dd1294a6491avboxsync export NAME(%1) NAME_FASTCALL(%1,%2,$@)
032703cba22135d6032705fc2d67dd1294a6491avboxsync %ifndef ASM_FORMAT_BIN
032703cba22135d6032705fc2d67dd1294a6491avboxsync global NAME_FASTCALL(%1,%2,$@)
032703cba22135d6032705fc2d67dd1294a6491avboxsyncNAME_FASTCALL(%1,%2,@):
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; We employ some macro assembly here to hid the calling convention differences.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync%ifdef RT_ARCH_AMD64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %macro PROLOGUE_1_ARGS 0
315f68b04971772d94ba6c4408eaa19559a77cedvboxsync %macro EPILOGUE_1_ARGS 1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %macro PROLOGUE_2_ARGS 0
315f68b04971772d94ba6c4408eaa19559a77cedvboxsync %macro EPILOGUE_2_ARGS 1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %macro PROLOGUE_3_ARGS 0
315f68b04971772d94ba6c4408eaa19559a77cedvboxsync %macro EPILOGUE_3_ARGS 1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %macro PROLOGUE_4_ARGS 0
315f68b04971772d94ba6c4408eaa19559a77cedvboxsync %macro EPILOGUE_4_ARGS 1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef ASM_CALL64_GCC
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A0 rdi
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A0_32 edi
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A0_16 di
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A0_8 dil
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A1 rsi
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A1_32 esi
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A1_16 si
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A1_8 sil
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A2 rdx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A2_32 edx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A2_16 dx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A2_8 dl
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A3 rcx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A3_32 ecx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A3_16 cx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef ASM_CALL64_MSC
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A0 rcx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A0_32 ecx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A0_16 cx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A0_8 cl
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A1 rdx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A1_32 edx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A1_16 dx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A1_8 dl
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A2 r8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A2_32 r8d
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A2_16 r8w
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A2_8 r8b
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A3 r9
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A3_32 r9d
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A3_16 r9w
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T0 rax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T0_32 eax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T0_16 ax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T0_8 al
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T1 r11
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T1_32 r11d
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T1_16 r11w
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T1_8 r11b
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %macro PROLOGUE_1_ARGS 0
032703cba22135d6032705fc2d67dd1294a6491avboxsync %macro EPILOGUE_1_ARGS 1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %macro PROLOGUE_2_ARGS 0
032703cba22135d6032705fc2d67dd1294a6491avboxsync %macro EPILOGUE_2_ARGS 1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %macro PROLOGUE_3_ARGS 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov ebx, [esp + 4 + 4]
032703cba22135d6032705fc2d67dd1294a6491avboxsync %macro EPILOGUE_3_ARGS 1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %macro PROLOGUE_4_ARGS 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov ebx, [esp + 12 + 4 + 0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov esi, [esp + 12 + 4 + 4]
032703cba22135d6032705fc2d67dd1294a6491avboxsync %macro EPILOGUE_4_ARGS 1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A0 ecx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A0_32 ecx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A0_16 cx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A0_8 cl
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A1 edx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A1_32 edx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A1_16 dx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A1_8 dl
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A2 ebx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A2_32 ebx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A2_16 bx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A2_8 bl
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A3 esi
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A3_32 esi
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define A3_16 si
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T0 eax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T0_32 eax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T0_16 ax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T0_8 al
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T1 edi
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T1_32 edi
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %define T1_16 di
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; Load the relevant flags from [%1] if there are undefined flags (%3).
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @remarks Clobbers T0, stack. Changes EFLAGS.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param A2 The register pointing to the flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 1 The parameter (A0..A3) pointing to the eflags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 2 The set of modified flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 3 The set of undefined flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync%macro IEM_MAYBE_LOAD_FLAGS 3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync ;%if (%3) != 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync pushf ; store current flags
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov T0_32, [%1] ; load the guest flags
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync and dword [xSP], ~(%2 | %3) ; mask out the modified and undefined flags
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync and T0_32, (%2 | %3) ; select the modified and undefined flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync or [xSP], T0 ; merge guest flags with host flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync popf ; load the mixed flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; Update the flag.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @remarks Clobbers T0, T1, stack.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 1 The register pointing to the EFLAGS.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 2 The mask of modified flags to save.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 3 The mask of undefined flags to (maybe) save.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync%macro IEM_SAVE_FLAGS 3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %if (%2 | %3) != 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov T0_32, [%1] ; flags
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync and T0_32, ~(%2 | %3) ; clear the modified & undefined flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync and T1_32, (%2 | %3) ; select the modified and undefined flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync or T0_32, T1_32 ; combine the flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [%1], T0_32 ; save the flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; Macro for implementing a binary operator.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; This will generate code for the 8, 16, 32 and 64 bit accesses with locked
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; variants, except on 32-bit system where the 64-bit accesses requires hand
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; All the functions takes a pointer to the destination memory operand in A0,
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; the source register operand in A1 and a pointer to eflags in A2.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 1 The instruction mnemonic.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 2 Non-zero if there should be a locked version.
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; @param 3 The modified flags.
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; @param 4 The undefined flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync%macro IEMIMPL_BIN_OP 4
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, %3, %4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 byte [A0], A1_8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, %3, %4
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u8
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, %3, %4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 word [A0], A1_16
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, %3, %4
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u16
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, %3, %4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 dword [A0], A1_32
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, %3, %4
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u32
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef RT_ARCH_AMD64
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, %3, %4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 qword [A0], A1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, %3, %4
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %else ; stub it for now - later, replace with hand coded stuff.
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %endif ; !RT_ARCH_AMD64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %if %2 != 0 ; locked versions requested?
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8_locked, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, %3, %4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync lock %1 byte [A0], A1_8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, %3, %4
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u8_locked
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16_locked, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, %3, %4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync lock %1 word [A0], A1_16
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, %3, %4
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u16_locked
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32_locked, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, %3, %4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync lock %1 dword [A0], A1_32
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, %3, %4
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u32_locked
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef RT_ARCH_AMD64
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 16
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, %3, %4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync lock %1 qword [A0], A1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, %3, %4
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64_locked
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %else ; stub it for now - later, replace with hand coded stuff.
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 16
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64_locked
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %endif ; !RT_ARCH_AMD64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %endif ; locked
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; instr,lock,modified-flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_BIN_OP add, 1, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_BIN_OP adc, 1, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_BIN_OP sub, 1, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_BIN_OP sbb, 1, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncIEMIMPL_BIN_OP or, 1, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), X86_EFL_AF,
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncIEMIMPL_BIN_OP xor, 1, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), X86_EFL_AF,
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncIEMIMPL_BIN_OP and, 1, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), X86_EFL_AF,
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_BIN_OP cmp, 0, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncIEMIMPL_BIN_OP test, 0, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), X86_EFL_AF,
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; Macro for implementing a bit operator.
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; This will generate code for the 16, 32 and 64 bit accesses with locked
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; variants, except on 32-bit system where the 64-bit accesses requires hand
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; All the functions takes a pointer to the destination memory operand in A0,
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; the source register operand in A1 and a pointer to eflags in A2.
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; @param 1 The instruction mnemonic.
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; @param 2 Non-zero if there should be a locked version.
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; @param 3 The modified flags.
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; @param 4 The undefined flags.
b64efece437bfca8872b81be9d0568ba90389d91vboxsync%macro IEMIMPL_BIT_OP 4
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
b64efece437bfca8872b81be9d0568ba90389d91vboxsync PROLOGUE_3_ARGS
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_MAYBE_LOAD_FLAGS A2, %3, %4
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %1 word [A0], A1_16
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_SAVE_FLAGS A2, %3, %4
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u16
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
b64efece437bfca8872b81be9d0568ba90389d91vboxsync PROLOGUE_3_ARGS
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_MAYBE_LOAD_FLAGS A2, %3, %4
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %1 dword [A0], A1_32
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_SAVE_FLAGS A2, %3, %4
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u32
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %ifdef RT_ARCH_AMD64
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
b64efece437bfca8872b81be9d0568ba90389d91vboxsync PROLOGUE_3_ARGS
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_MAYBE_LOAD_FLAGS A2, %3, %4
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %1 qword [A0], A1
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_SAVE_FLAGS A2, %3, %4
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 8
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %else ; stub it for now - later, replace with hand coded stuff.
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %endif ; !RT_ARCH_AMD64
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %if %2 != 0 ; locked versions requested?
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16_locked, 12
b64efece437bfca8872b81be9d0568ba90389d91vboxsync PROLOGUE_3_ARGS
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_MAYBE_LOAD_FLAGS A2, %3, %4
b64efece437bfca8872b81be9d0568ba90389d91vboxsync lock %1 word [A0], A1_16
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_SAVE_FLAGS A2, %3, %4
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u16_locked
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32_locked, 12
b64efece437bfca8872b81be9d0568ba90389d91vboxsync PROLOGUE_3_ARGS
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_MAYBE_LOAD_FLAGS A2, %3, %4
b64efece437bfca8872b81be9d0568ba90389d91vboxsync lock %1 dword [A0], A1_32
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_SAVE_FLAGS A2, %3, %4
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u32_locked
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %ifdef RT_ARCH_AMD64
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 16
b64efece437bfca8872b81be9d0568ba90389d91vboxsync PROLOGUE_3_ARGS
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_MAYBE_LOAD_FLAGS A2, %3, %4
b64efece437bfca8872b81be9d0568ba90389d91vboxsync lock %1 qword [A0], A1
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_SAVE_FLAGS A2, %3, %4
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 8
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64_locked
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %else ; stub it for now - later, replace with hand coded stuff.
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 16
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64_locked
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %endif ; !RT_ARCH_AMD64
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %endif ; locked
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncIEMIMPL_BIT_OP bt, 0, (X86_EFL_CF), (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncIEMIMPL_BIT_OP btc, 1, (X86_EFL_CF), (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncIEMIMPL_BIT_OP bts, 1, (X86_EFL_CF), (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncIEMIMPL_BIT_OP btr, 1, (X86_EFL_CF), (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; Macro for implementing a bit search operator.
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; This will generate code for the 16, 32 and 64 bit accesses, except on 32-bit
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; system where the 64-bit accesses requires hand coding.
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; All the functions takes a pointer to the destination memory operand in A0,
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; the source register operand in A1 and a pointer to eflags in A2.
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; @param 1 The instruction mnemonic.
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; @param 2 The modified flags.
b64efece437bfca8872b81be9d0568ba90389d91vboxsync; @param 3 The undefined flags.
b64efece437bfca8872b81be9d0568ba90389d91vboxsync%macro IEMIMPL_BIT_OP 3
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
b64efece437bfca8872b81be9d0568ba90389d91vboxsync PROLOGUE_3_ARGS
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_MAYBE_LOAD_FLAGS A2, %2, %3
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %1 T0_16, A1_16
b64efece437bfca8872b81be9d0568ba90389d91vboxsync mov [A0], T0_16
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_SAVE_FLAGS A2, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u16
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
b64efece437bfca8872b81be9d0568ba90389d91vboxsync PROLOGUE_3_ARGS
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_MAYBE_LOAD_FLAGS A2, %2, %3
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %1 T0_32, A1_32
b64efece437bfca8872b81be9d0568ba90389d91vboxsync mov [A0], T0_32
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_SAVE_FLAGS A2, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u32
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %ifdef RT_ARCH_AMD64
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
b64efece437bfca8872b81be9d0568ba90389d91vboxsync PROLOGUE_3_ARGS
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_MAYBE_LOAD_FLAGS A2, %2, %3
b64efece437bfca8872b81be9d0568ba90389d91vboxsync mov [A0], T0
b64efece437bfca8872b81be9d0568ba90389d91vboxsync IEM_SAVE_FLAGS A2, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 8
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %else ; stub it for now - later, replace with hand coded stuff.
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
b64efece437bfca8872b81be9d0568ba90389d91vboxsync %endif ; !RT_ARCH_AMD64
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncIEMIMPL_BIT_OP bsf, (X86_EFL_ZF), (X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF)
b64efece437bfca8872b81be9d0568ba90389d91vboxsyncIEMIMPL_BIT_OP bsr, (X86_EFL_ZF), (X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF)
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; IMUL is also a similar but yet different case (no lock, no mem dst).
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; The rDX:rAX variant of imul is handled together with mul further down.
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_imul_two_u16, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync imul A1_16, word [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], A1_16
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_imul_two_u16
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_imul_two_u32, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync imul A1_32, dword [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], A1_32
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_imul_two_u32
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_imul_two_u64, 16
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync%ifdef RT_ARCH_AMD64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync imul A1, qword [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], A1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync int3 ;; @todo implement me
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_imul_two_u64
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync; XCHG for memory operands. This implies locking. No flag changes.
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync; Each function takes two arguments, first the pointer to the memory,
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync; then the pointer to the register. They all return void.
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_xchg_u8, 8
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync PROLOGUE_2_ARGS
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync mov T0_8, [A1]
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync xchg [A0], T0_8
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync mov [A1], T0_8
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_2_ARGS 0
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsyncENDPROC iemAImpl_xchg_u8
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_xchg_u16, 8
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync PROLOGUE_2_ARGS
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync mov T0_16, [A1]
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync xchg [A0], T0_16
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync mov [A1], T0_16
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_2_ARGS 0
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsyncENDPROC iemAImpl_xchg_u16
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_xchg_u32, 8
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync PROLOGUE_2_ARGS
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync mov T0_32, [A1]
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync xchg [A0], T0_32
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync mov [A1], T0_32
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_2_ARGS 0
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsyncENDPROC iemAImpl_xchg_u32
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_xchg_u64, 8
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync%ifdef RT_ARCH_AMD64
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync PROLOGUE_2_ARGS
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync mov T0, [A1]
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync xchg [A0], T0
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsync mov [A1], T0
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_2_ARGS 0
4c46bb28a73dee292c3657d2945574a1c267b89dvboxsyncENDPROC iemAImpl_xchg_u64
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync; XADD for memory operands.
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync; Each function takes three arguments, first the pointer to the
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync; memory/register, then the pointer to the register, and finally a pointer to
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync; eflags. They all return void.
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_xadd_u8, 12
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync PROLOGUE_3_ARGS
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov T0_8, [A1]
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync xadd [A0], T0_8
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov [A1], T0_8
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsyncENDPROC iemAImpl_xadd_u8
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_xadd_u16, 12
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync PROLOGUE_3_ARGS
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov T0_16, [A1]
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync xadd [A0], T0_16
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov [A1], T0_16
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsyncENDPROC iemAImpl_xadd_u16
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_xadd_u32, 12
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync PROLOGUE_3_ARGS
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov T0_32, [A1]
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync xadd [A0], T0_32
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov [A1], T0_32
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsyncENDPROC iemAImpl_xadd_u32
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_xadd_u64, 12
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync%ifdef RT_ARCH_AMD64
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync PROLOGUE_3_ARGS
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov T0, [A1]
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync xadd [A0], T0
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov [A1], T0
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsyncENDPROC iemAImpl_xadd_u64
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_xadd_u8_locked, 12
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync PROLOGUE_3_ARGS
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov T0_8, [A1]
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync lock xadd [A0], T0_8
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov [A1], T0_8
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsyncENDPROC iemAImpl_xadd_u8_locked
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_xadd_u16_locked, 12
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync PROLOGUE_3_ARGS
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov T0_16, [A1]
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync lock xadd [A0], T0_16
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov [A1], T0_16
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsyncENDPROC iemAImpl_xadd_u16_locked
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_xadd_u32_locked, 12
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync PROLOGUE_3_ARGS
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov T0_32, [A1]
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync lock xadd [A0], T0_32
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov [A1], T0_32
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsyncENDPROC iemAImpl_xadd_u32_locked
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_xadd_u64_locked, 12
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync%ifdef RT_ARCH_AMD64
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync PROLOGUE_3_ARGS
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov T0, [A1]
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync lock xadd [A0], T0
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync mov [A1], T0
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsync IEM_SAVE_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
1afc174efd532be60bfaaf42a70bc3db4ec1b675vboxsyncENDPROC iemAImpl_xadd_u64_locked
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync; CMPXCHG8B.
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync; These are tricky register wise, so the code is duplicated for each calling
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync; convention.
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync; WARNING! This code make ASSUMPTIONS about which registers T1 and T0 are mapped to!
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync; IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync; uint32_t *pEFlags));
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsyncBEGINPROC_FASTCALL iemAImpl_cmpxchg8b, 16
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync%ifdef RT_ARCH_AMD64
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync %ifdef ASM_CALL64_MSC
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov r11, rdx ; pu64EaxEdx (is also T1)
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov r10, rcx ; pu64Dst
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov ebx, [r8]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov ecx, [r8 + 4]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync IEM_MAYBE_LOAD_FLAGS r9, (X86_EFL_ZF), 0 ; clobbers T0 (eax)
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov eax, [r11]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov edx, [r11 + 4]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync lock cmpxchg8b [r10]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov [r11], eax
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov [r11 + 4], edx
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync IEM_SAVE_FLAGS r9, (X86_EFL_ZF), 0 ; clobbers T0+T1 (eax, r11)
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov r10, rcx ; pEFlags
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov r11, rdx ; pu64EbxEcx (is also T1)
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov ebx, [r11]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov ecx, [r11 + 4]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync IEM_MAYBE_LOAD_FLAGS r10, (X86_EFL_ZF), 0 ; clobbers T0 (eax)
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov eax, [rsi]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov edx, [rsi + 4]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync lock cmpxchg8b [rdi]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov [rsi], eax
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov [rsi + 4], edx
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync IEM_SAVE_FLAGS r10, (X86_EFL_ZF), 0 ; clobbers T0+T1 (eax, r11)
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov edi, ecx ; pu64Dst
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov esi, edx ; pu64EaxEdx
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov ecx, [esp + 16 + 4 + 0] ; pu64EbxEcx
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov ebp, [esp + 16 + 4 + 4] ; pEFlags
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov ebx, [ecx]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov ecx, [ecx + 4]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync IEM_MAYBE_LOAD_FLAGS rbp, (X86_EFL_ZF), 0 ; clobbers T0 (eax)
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov eax, [esi]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov edx, [esi + 4]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync lock cmpxchg8b [edi]
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov [rsi], eax
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync mov [rsi + 4], edx
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync IEM_SAVE_FLAGS rbp, (X86_EFL_ZF), 0 ; clobbers T0+T1 (eax, edi)
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsyncENDPROC iemAImpl_cmpxchg8b
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsyncBEGINPROC_FASTCALL iemAImpl_cmpxchg8b_locked, 16
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync ; Lazy bird always lock prefixes cmpxchg8b.
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsync jmp NAME_FASTCALL(iemAImpl_cmpxchg8b,16,$@)
4edc278439db2c83a5a59a104ec85e379d4c07dfvboxsyncENDPROC iemAImpl_cmpxchg8b_locked
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; Macro for implementing a unary operator.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; This will generate code for the 8, 16, 32 and 64 bit accesses with locked
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; variants, except on 32-bit system where the 64-bit accesses requires hand
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; All the functions takes a pointer to the destination memory operand in A0,
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; the source register operand in A1 and a pointer to eflags in A2.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 1 The instruction mnemonic.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 2 The modified flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 3 The undefined flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync%macro IEMIMPL_UNARY_OP 3
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8, 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_2_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A1, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 byte [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A1, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_2_ARGS 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u8
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8_locked, 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_2_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A1, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync lock %1 byte [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A1, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_2_ARGS 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u8_locked
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_2_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A1, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 word [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A1, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_2_ARGS 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u16
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16_locked, 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_2_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A1, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync lock %1 word [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A1, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_2_ARGS 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u16_locked
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_2_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A1, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 dword [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A1, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_2_ARGS 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u32
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32_locked, 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_2_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A1, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync lock %1 dword [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A1, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_2_ARGS 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u32_locked
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef RT_ARCH_AMD64
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_2_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A1, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 qword [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A1, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_2_ARGS 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_2_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A1, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync lock %1 qword [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A1, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_2_ARGS 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64_locked
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync ; stub them for now.
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64_locked
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_UNARY_OP inc, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF), 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_UNARY_OP dec, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF), 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_UNARY_OP neg, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_UNARY_OP not, 0, 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; Macro for implementing a shift operation.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; This will generate code for the 8, 16, 32 and 64 bit accesses, except on
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; 32-bit system where the 64-bit accesses requires hand coding.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; All the functions takes a pointer to the destination memory operand in A0,
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; the shift count in A1 and a pointer to eflags in A2.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 1 The instruction mnemonic.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 2 The modified flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 3 The undefined flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; Makes ASSUMPTIONS about A0, A1 and A2 assignments.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync%macro IEMIMPL_SHIFT_OP 3
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef ASM_CALL64_GCC
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov cl, A1_8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 byte [A0], cl
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync xchg A1, A0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 byte [A1], cl
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u8
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef ASM_CALL64_GCC
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov cl, A1_8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 word [A0], cl
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync xchg A1, A0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 word [A1], cl
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u16
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef ASM_CALL64_GCC
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov cl, A1_8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 dword [A0], cl
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync xchg A1, A0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 dword [A1], cl
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u32
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef RT_ARCH_AMD64
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef ASM_CALL64_GCC
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov cl, A1_8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 qword [A0], cl
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync xchg A1, A0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %1 qword [A1], cl
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %else ; stub it for now - later, replace with hand coded stuff.
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %endif ; !RT_ARCH_AMD64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_SHIFT_OP rol, (X86_EFL_OF | X86_EFL_CF), 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_SHIFT_OP ror, (X86_EFL_OF | X86_EFL_CF), 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_SHIFT_OP rcl, (X86_EFL_OF | X86_EFL_CF), 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_SHIFT_OP rcr, (X86_EFL_OF | X86_EFL_CF), 0
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_SHIFT_OP shl, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), (X86_EFL_AF)
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_SHIFT_OP shr, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), (X86_EFL_AF)
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_SHIFT_OP sar, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), (X86_EFL_AF)
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsync; Macro for implementing a double precision shift operation.
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync; This will generate code for the 16, 32 and 64 bit accesses, except on
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync; 32-bit system where the 64-bit accesses requires hand coding.
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync; The functions takes the destination operand (r/m) in A0, the source (reg) in
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync; A1, the shift count in A2 and a pointer to the eflags variable/register in A3.
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync; @param 1 The instruction mnemonic.
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync; @param 2 The modified flags.
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync; @param 3 The undefined flags.
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync; Makes ASSUMPTIONS about A0, A1, A2 and A3 assignments.
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync%macro IEMIMPL_SHIFT_DBL_OP 3
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 16
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync PROLOGUE_4_ARGS
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync IEM_MAYBE_LOAD_FLAGS A3, %2, %3
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync %ifdef ASM_CALL64_GCC
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync xchg A3, A2
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync %1 [A0], A1_16, cl
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync xchg A3, A2
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync xchg A0, A2
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync %1 [A2], A1_16, cl
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync IEM_SAVE_FLAGS A3, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_4_ARGS 8
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u16
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 16
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync PROLOGUE_4_ARGS
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync IEM_MAYBE_LOAD_FLAGS A3, %2, %3
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync %ifdef ASM_CALL64_GCC
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync xchg A3, A2
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync %1 [A0], A1_32, cl
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync xchg A3, A2
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync xchg A0, A2
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync %1 [A2], A1_32, cl
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync IEM_SAVE_FLAGS A3, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_4_ARGS 8
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u32
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync %ifdef RT_ARCH_AMD64
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 20
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync PROLOGUE_4_ARGS
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync IEM_MAYBE_LOAD_FLAGS A3, %2, %3
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync %ifdef ASM_CALL64_GCC
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync xchg A3, A2
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync %1 [A0], A1, cl
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync xchg A3, A2
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync xchg A0, A2
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync %1 [A2], A1, cl
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync IEM_SAVE_FLAGS A3, %2, %3
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_4_ARGS 12
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync %else ; stub it for now - later, replace with hand coded stuff.
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 20
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync %endif ; !RT_ARCH_AMD64
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsyncIEMIMPL_SHIFT_DBL_OP shld, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), (X86_EFL_AF)
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsyncIEMIMPL_SHIFT_DBL_OP shrd, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF), (X86_EFL_AF)
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync; Macro for implementing a multiplication operations.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; This will generate code for the 8, 16, 32 and 64 bit accesses, except on
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; 32-bit system where the 64-bit accesses requires hand coding.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; The 8-bit function only operates on AX, so it takes no DX pointer. The other
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; functions takes a pointer to rAX in A0, rDX in A1, the operand in A2 and a
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; pointer to eflags in A3.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; The functions all return 0 so the caller can be used for div/idiv as well as
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; for the mul/imul implementation.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 1 The instruction mnemonic.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 2 The modified flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 3 The undefined flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; Makes ASSUMPTIONS about A0, A1, A2, A3, T0 and T1 assignments.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync%macro IEMIMPL_MUL_OP 3
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov al, [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], ax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync xor eax, eax
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u8
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 16
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_4_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A3, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov ax, [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef ASM_CALL64_GCC
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], ax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A1], dx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], ax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [T1], dx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A3, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync xor eax, eax
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_4_ARGS 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u16
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 16
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_4_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A3, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov eax, [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef ASM_CALL64_GCC
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], eax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A1], edx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], eax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [T1], edx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A3, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync xor eax, eax
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_4_ARGS 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u32
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef RT_ARCH_AMD64
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 20
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_4_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A3, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov rax, [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef ASM_CALL64_GCC
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], rax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A1], rdx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], rax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [T1], rdx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A3, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync xor eax, eax
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_4_ARGS 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %else ; stub it for now - later, replace with hand coded stuff.
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 20
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %endif ; !RT_ARCH_AMD64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_MUL_OP mul, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_MUL_OP imul, (X86_EFL_OF | X86_EFL_CF), (X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)
2a69254c6b802ee414e54fe0c1202d67dac90ce8vboxsync; Macro for implementing a division operations.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; This will generate code for the 8, 16, 32 and 64 bit accesses, except on
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; 32-bit system where the 64-bit accesses requires hand coding.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; The 8-bit function only operates on AX, so it takes no DX pointer. The other
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; functions takes a pointer to rAX in A0, rDX in A1, the operand in A2 and a
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; pointer to eflags in A3.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; The functions all return 0 on success and -1 if a divide error should be
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; raised by the caller.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 1 The instruction mnemonic.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 2 The modified flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; @param 3 The undefined flags.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync; Makes ASSUMPTIONS about A0, A1, A2, A3, T0 and T1 assignments.
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync%macro IEMIMPL_DIV_OP 3
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8, 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_3_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync test A1_8, A1_8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync jz .div_zero
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync ;; @todo test for overflow
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A2, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov ax, [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], ax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A2, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync xor eax, eax
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_3_ARGS 4
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov eax, -1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync jmp .return
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u8
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 16
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_4_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync test A1_16, A1_16
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync jz .div_zero
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync ;; @todo test for overflow
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A3, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef ASM_CALL64_GCC
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov ax, [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov dx, [A1]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], ax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A1], dx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov ax, [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov dx, [T1]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], ax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [T1], dx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A3, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync xor eax, eax
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_4_ARGS 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov eax, -1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync jmp .return
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u16
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 16
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_4_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync test A1_32, A1_32
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync jz .div_zero
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync ;; @todo test for overflow
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A3, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov eax, [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef ASM_CALL64_GCC
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov eax, [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov edx, [A1]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], eax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A1], edx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov eax, [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov edx, [T1]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], eax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [T1], edx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A3, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync xor eax, eax
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_4_ARGS 8
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov eax, -1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync jmp .return
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u32
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef RT_ARCH_AMD64
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 20
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync PROLOGUE_4_ARGS
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync test A1, A1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync jz .div_zero
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync ;; @todo test for overflow
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_MAYBE_LOAD_FLAGS A3, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov rax, [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %ifdef ASM_CALL64_GCC
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov rax, [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov rdx, [A1]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], rax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A1], rdx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov rax, [A0]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov rdx, [T1]
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [A0], rax
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov [T1], rdx
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync IEM_SAVE_FLAGS A3, %2, %3
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync xor eax, eax
032703cba22135d6032705fc2d67dd1294a6491avboxsync EPILOGUE_4_ARGS 12
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync mov eax, -1
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync jmp .return
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %else ; stub it for now - later, replace with hand coded stuff.
3755e2bacafa2dd718108ad1a18661dcd9566bd8vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 20
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncENDPROC iemAImpl_ %+ %1 %+ _u64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsync %endif ; !RT_ARCH_AMD64
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_DIV_OP div, 0, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF)
65c72795ab90d3daefa759b716fbb5c6352c7a56vboxsyncIEMIMPL_DIV_OP idiv, 0, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF)
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync; BSWAP. No flag changes.
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync; Each function takes one argument, pointer to the value to bswap
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync; (input/output). They all return void.
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsyncBEGINPROC_FASTCALL iemAImpl_bswap_u16, 4
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync PROLOGUE_1_ARGS
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync mov T0_32, [A0] ; just in case any of the upper bits are used.
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync bswap T0_32
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync mov [A0], T0_32
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync EPILOGUE_1_ARGS 0
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsyncENDPROC iemAImpl_bswap_u16
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsyncBEGINPROC_FASTCALL iemAImpl_bswap_u32, 4
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync PROLOGUE_1_ARGS
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync mov T0_32, [A0]
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync bswap T0_32
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync mov [A0], T0_32
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync EPILOGUE_1_ARGS 0
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsyncENDPROC iemAImpl_bswap_u32
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsyncBEGINPROC_FASTCALL iemAImpl_bswap_u64, 4
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync%ifdef RT_ARCH_AMD64
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync PROLOGUE_1_ARGS
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync mov T0, [A0]
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync mov [A0], T0
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync EPILOGUE_1_ARGS 0
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync PROLOGUE_1_ARGS
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync mov T0, [A0]
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync mov T1, [A0 + 4]
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync mov [A0 + 4], T0
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync mov [A0], T1
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsync EPILOGUE_1_ARGS 0
869b801c85bf466f1f7c9d183e336e60dd5a1da7vboxsyncENDPROC iemAImpl_bswap_u64
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync; Initialize the FPU for the actual instruction being emulated, this means
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync; loading parts of the guest's control word and status word.
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync; @uses 24 bytes of stack.
532262d2bfcb0d1b5e981972cf8ef2733ed63ddcvboxsync; @param 1 Expression giving the address of the FXSTATE of the guest.
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync%macro FPU_LD_FXSTATE_FCW_AND_SAFE_FSW 1
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync fnstenv [xSP]
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync ; FCW - for exception, precision and rounding control.
532262d2bfcb0d1b5e981972cf8ef2733ed63ddcvboxsync movzx T0, word [%1 + X86FXSTATE.FCW]
532262d2bfcb0d1b5e981972cf8ef2733ed63ddcvboxsync and T0, X86_FCW_MASK_ALL | X86_FCW_PC_MASK | X86_FCW_RC_MASK
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync mov [xSP + X86FSTENV32P.FCW], T0_16
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync ; FSW - for undefined C0, C1, C2, and C3.
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync movzx T1, word [%1 + X86FXSTATE.FSW]
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync and T1, X86_FSW_C_MASK
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync movzx T0, word [xSP + X86FSTENV32P.FSW]
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync and T0, X86_FSW_TOP_MASK
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync mov [xSP + X86FSTENV32P.FSW], T0_16
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync fldenv [xSP]
bf9b125dff66b86d319a4f4254e2288110675679vboxsync; Need to move this as well somewhere better?
bf9b125dff66b86d319a4f4254e2288110675679vboxsyncstruc IEMFPURESULT
bf9b125dff66b86d319a4f4254e2288110675679vboxsync .r80Result resw 5
bf9b125dff66b86d319a4f4254e2288110675679vboxsync .FSW resw 1
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync; Need to move this as well somewhere better?
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsyncstruc IEMFPURESULTTWO
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync .r80Result1 resw 5
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync .FSW resw 1
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync .r80Result2 resw 5
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync;---------------------- 16-bit signed integer operations ----------------------
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; Converts a 16-bit floating point value to a 80-bit one (fpu register).
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A0 FPU context (fxsave).
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A1 Pointer to a IEMFPURESULT for the output.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A2 Pointer to the 16-bit floating point value to convert.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsyncBEGINPROC_FASTCALL iemAImpl_fild_i16_to_r80, 12
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync PROLOGUE_3_ARGS
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync sub xSP, 20h
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fild word [A2]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fnstsw word [A1 + IEMFPURESULT.FSW]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fstp tword [A1 + IEMFPURESULT.r80Result]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync add xSP, 20h
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync EPILOGUE_3_ARGS 0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsyncENDPROC iemAImpl_fild_i16_to_r80
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; Store a 80-bit floating point value (register) as a 16-bit signed integer (memory).
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A0 FPU context (fxsave).
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A1 Where to return the output FSW.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A2 Where to store the 16-bit signed integer value.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A3 Pointer to the 80-bit value.
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsyncBEGINPROC_FASTCALL iemAImpl_fist_r80_to_i16, 16
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync PROLOGUE_4_ARGS
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync sub xSP, 20h
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fld tword [A3]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fistp word [A2]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fnstsw word [A1]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync add xSP, 20h
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync EPILOGUE_4_ARGS 0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsyncENDPROC iemAImpl_fist_r80_to_i16
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; Store a 80-bit floating point value (register) as a 16-bit signed integer
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; (memory) with truncation.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A0 FPU context (fxsave).
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A1 Where to return the output FSW.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A2 Where to store the 16-bit signed integer value.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A3 Pointer to the 80-bit value.
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsyncBEGINPROC_FASTCALL iemAImpl_fistt_r80_to_i16, 16
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync PROLOGUE_4_ARGS
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync sub xSP, 20h
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fld tword [A3]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fisttp dword [A2]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fnstsw word [A1]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync add xSP, 20h
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync EPILOGUE_4_ARGS 0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsyncENDPROC iemAImpl_fistt_r80_to_i16
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync; FPU instruction working on one 80-bit and one 16-bit signed integer value.
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync; @param 1 The instruction
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync; @param A0 FPU context (fxsave).
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync; @param A1 Pointer to a IEMFPURESULT for the output.
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync; @param A2 Pointer to the 80-bit value.
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync; @param A3 Pointer to the 16-bit value.
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync%macro IEMIMPL_FPU_R80_BY_I16 1
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_i16, 16
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync PROLOGUE_4_ARGS
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync sub xSP, 20h
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync fld tword [A2]
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync %1 word [A3]
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync fnstsw word [A1 + IEMFPURESULT.FSW]
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync fstp tword [A1 + IEMFPURESULT.r80Result]
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync add xSP, 20h
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync EPILOGUE_4_ARGS 8
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80_by_i16
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsyncIEMIMPL_FPU_R80_BY_I16 fiadd
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsyncIEMIMPL_FPU_R80_BY_I16 fimul
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsyncIEMIMPL_FPU_R80_BY_I16 fisub
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsyncIEMIMPL_FPU_R80_BY_I16 fisubr
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsyncIEMIMPL_FPU_R80_BY_I16 fidiv
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsyncIEMIMPL_FPU_R80_BY_I16 fidivr
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync; FPU instruction working on one 80-bit and one 16-bit signed integer value,
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync; only returning FSW.
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync; @param 1 The instruction
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync; @param A0 FPU context (fxsave).
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync; @param A1 Where to store the output FSW.
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync; @param A2 Pointer to the 80-bit value.
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync; @param A3 Pointer to the 64-bit value.
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync%macro IEMIMPL_FPU_R80_BY_I16_FSW 1
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_i16, 16
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync PROLOGUE_4_ARGS
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync sub xSP, 20h
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync fld tword [A2]
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync %1 word [A3]
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync fnstsw word [A1]
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync add xSP, 20h
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsync EPILOGUE_4_ARGS 8
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80_by_i16
9f2a126861374bb11fb9e70265f8a4b6260ccb77vboxsyncIEMIMPL_FPU_R80_BY_I16_FSW ficom
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync;---------------------- 32-bit signed integer operations ----------------------
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; Converts a 32-bit floating point value to a 80-bit one (fpu register).
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A0 FPU context (fxsave).
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A1 Pointer to a IEMFPURESULT for the output.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A2 Pointer to the 32-bit floating point value to convert.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsyncBEGINPROC_FASTCALL iemAImpl_fild_i32_to_r80, 12
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync PROLOGUE_3_ARGS
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync sub xSP, 20h
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fild dword [A2]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fnstsw word [A1 + IEMFPURESULT.FSW]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fstp tword [A1 + IEMFPURESULT.r80Result]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync add xSP, 20h
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync EPILOGUE_3_ARGS 0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsyncENDPROC iemAImpl_fild_i32_to_r80
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; Store a 80-bit floating point value (register) as a 32-bit signed integer (memory).
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; @param A0 FPU context (fxsave).
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; @param A1 Where to return the output FSW.
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; @param A2 Where to store the 32-bit signed integer value.
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; @param A3 Pointer to the 80-bit value.
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsyncBEGINPROC_FASTCALL iemAImpl_fist_r80_to_i32, 16
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync PROLOGUE_4_ARGS
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync sub xSP, 20h
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync fld tword [A3]
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fistp dword [A2]
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync fnstsw word [A1]
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync add xSP, 20h
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync EPILOGUE_4_ARGS 0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsyncENDPROC iemAImpl_fist_r80_to_i32
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; Store a 80-bit floating point value (register) as a 32-bit signed integer
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; (memory) with truncation.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A0 FPU context (fxsave).
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A1 Where to return the output FSW.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A2 Where to store the 32-bit signed integer value.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A3 Pointer to the 80-bit value.
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsyncBEGINPROC_FASTCALL iemAImpl_fistt_r80_to_i32, 16
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync PROLOGUE_4_ARGS
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync sub xSP, 20h
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fld tword [A3]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fisttp dword [A2]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fnstsw word [A1]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync add xSP, 20h
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync EPILOGUE_4_ARGS 0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsyncENDPROC iemAImpl_fistt_r80_to_i32
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; FPU instruction working on one 80-bit and one 32-bit signed integer value.
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; @param 1 The instruction
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; @param A0 FPU context (fxsave).
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; @param A1 Pointer to a IEMFPURESULT for the output.
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; @param A2 Pointer to the 80-bit value.
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; @param A3 Pointer to the 32-bit value.
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync%macro IEMIMPL_FPU_R80_BY_I32 1
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_i32, 16
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync PROLOGUE_4_ARGS
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync sub xSP, 20h
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync fld tword [A2]
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync %1 dword [A3]
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync fnstsw word [A1 + IEMFPURESULT.FSW]
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync fstp tword [A1 + IEMFPURESULT.r80Result]
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync add xSP, 20h
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync EPILOGUE_4_ARGS 8
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80_by_i32
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsyncIEMIMPL_FPU_R80_BY_I32 fiadd
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsyncIEMIMPL_FPU_R80_BY_I32 fimul
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsyncIEMIMPL_FPU_R80_BY_I32 fisub
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsyncIEMIMPL_FPU_R80_BY_I32 fisubr
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsyncIEMIMPL_FPU_R80_BY_I32 fidiv
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsyncIEMIMPL_FPU_R80_BY_I32 fidivr
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; FPU instruction working on one 80-bit and one 32-bit signed integer value,
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; only returning FSW.
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; @param 1 The instruction
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; @param A0 FPU context (fxsave).
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; @param A1 Where to store the output FSW.
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; @param A2 Pointer to the 80-bit value.
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; @param A3 Pointer to the 64-bit value.
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync%macro IEMIMPL_FPU_R80_BY_I32_FSW 1
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_i32, 16
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync PROLOGUE_4_ARGS
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync sub xSP, 20h
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync fld tword [A2]
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync %1 dword [A3]
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync fnstsw word [A1]
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync add xSP, 20h
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync EPILOGUE_4_ARGS 8
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80_by_i32
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsyncIEMIMPL_FPU_R80_BY_I32_FSW ficom
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync;---------------------- 64-bit signed integer operations ----------------------
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; Converts a 64-bit floating point value to a 80-bit one (fpu register).
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A0 FPU context (fxsave).
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A1 Pointer to a IEMFPURESULT for the output.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A2 Pointer to the 64-bit floating point value to convert.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsyncBEGINPROC_FASTCALL iemAImpl_fild_i64_to_r80, 12
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync PROLOGUE_3_ARGS
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync sub xSP, 20h
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fild qword [A2]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fnstsw word [A1 + IEMFPURESULT.FSW]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fstp tword [A1 + IEMFPURESULT.r80Result]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync add xSP, 20h
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync EPILOGUE_3_ARGS 0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsyncENDPROC iemAImpl_fild_i64_to_r80
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; Store a 80-bit floating point value (register) as a 64-bit signed integer (memory).
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A0 FPU context (fxsave).
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A1 Where to return the output FSW.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A2 Where to store the 64-bit signed integer value.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A3 Pointer to the 80-bit value.
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsyncBEGINPROC_FASTCALL iemAImpl_fist_r80_to_i64, 16
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync PROLOGUE_4_ARGS
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync sub xSP, 20h
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fld tword [A3]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fistp qword [A2]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fnstsw word [A1]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync add xSP, 20h
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync EPILOGUE_4_ARGS 0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsyncENDPROC iemAImpl_fist_r80_to_i64
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; Store a 80-bit floating point value (register) as a 64-bit signed integer
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; (memory) with truncation.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A0 FPU context (fxsave).
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A1 Where to return the output FSW.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A2 Where to store the 64-bit signed integer value.
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync; @param A3 Pointer to the 80-bit value.
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsyncBEGINPROC_FASTCALL iemAImpl_fistt_r80_to_i64, 16
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync PROLOGUE_4_ARGS
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync sub xSP, 20h
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fld tword [A3]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fisttp qword [A2]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync fnstsw word [A1]
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsync add xSP, 20h
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync EPILOGUE_4_ARGS 0
d280ee7a17fc630c6a421724d49e1cd28edcac10vboxsyncENDPROC iemAImpl_fistt_r80_to_i64
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync;---------------------- 32-bit floating point operations ----------------------
bf9b125dff66b86d319a4f4254e2288110675679vboxsync; Converts a 32-bit floating point value to a 80-bit one (fpu register).
bf9b125dff66b86d319a4f4254e2288110675679vboxsync; @param A0 FPU context (fxsave).
bf9b125dff66b86d319a4f4254e2288110675679vboxsync; @param A1 Pointer to a IEMFPURESULT for the output.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A2 Pointer to the 32-bit floating point value to convert.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncBEGINPROC_FASTCALL iemAImpl_fld_r32_to_r80, 12
bf9b125dff66b86d319a4f4254e2288110675679vboxsync PROLOGUE_3_ARGS
bf9b125dff66b86d319a4f4254e2288110675679vboxsync sub xSP, 20h
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fld dword [A2]
bf9b125dff66b86d319a4f4254e2288110675679vboxsync fnstsw word [A1 + IEMFPURESULT.FSW]
bf9b125dff66b86d319a4f4254e2288110675679vboxsync fstp tword [A1 + IEMFPURESULT.r80Result]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync add xSP, 20h
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync EPILOGUE_3_ARGS 0
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncENDPROC iemAImpl_fld_r32_to_r80
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; Store a 80-bit floating point value (register) as a 32-bit one (memory).
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A0 FPU context (fxsave).
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A1 Where to return the output FSW.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A2 Where to store the 32-bit value.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A3 Pointer to the 80-bit value.
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsyncBEGINPROC_FASTCALL iemAImpl_fst_r80_to_r32, 16
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync PROLOGUE_4_ARGS
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync sub xSP, 20h
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fld tword [A3]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fst dword [A2]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fnstsw word [A1]
bf9b125dff66b86d319a4f4254e2288110675679vboxsync add xSP, 20h
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync EPILOGUE_4_ARGS 0
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncENDPROC iemAImpl_fst_r80_to_r32
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; FPU instruction working on one 80-bit and one 32-bit floating point value.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param 1 The instruction
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A0 FPU context (fxsave).
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A1 Pointer to a IEMFPURESULT for the output.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A2 Pointer to the 80-bit value.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A3 Pointer to the 32-bit value.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync%macro IEMIMPL_FPU_R80_BY_R32 1
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r32, 16
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync PROLOGUE_4_ARGS
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync sub xSP, 20h
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fld tword [A2]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync %1 dword [A3]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fnstsw word [A1 + IEMFPURESULT.FSW]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fstp tword [A1 + IEMFPURESULT.r80Result]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync add xSP, 20h
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync EPILOGUE_4_ARGS 8
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80_by_r32
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncIEMIMPL_FPU_R80_BY_R32 fadd
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncIEMIMPL_FPU_R80_BY_R32 fmul
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncIEMIMPL_FPU_R80_BY_R32 fsub
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncIEMIMPL_FPU_R80_BY_R32 fsubr
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncIEMIMPL_FPU_R80_BY_R32 fdiv
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncIEMIMPL_FPU_R80_BY_R32 fdivr
7a38fa5bae2ea027a2fcc3f05ac15f91a2716ddbvboxsync; FPU instruction working on one 80-bit and one 32-bit floating point value,
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; only returning FSW.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param 1 The instruction
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A0 FPU context (fxsave).
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A1 Where to store the output FSW.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A2 Pointer to the 80-bit value.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A3 Pointer to the 64-bit value.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync%macro IEMIMPL_FPU_R80_BY_R32_FSW 1
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r32, 16
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync PROLOGUE_4_ARGS
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync sub xSP, 20h
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fld tword [A2]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync %1 dword [A3]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fnstsw word [A1]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync add xSP, 20h
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync EPILOGUE_4_ARGS 8
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80_by_r32
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncIEMIMPL_FPU_R80_BY_R32_FSW fcom
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync;---------------------- 64-bit floating point operations ----------------------
58b7ab82f43487a8a838dbeb96387c0d27b527f1vboxsync; Converts a 64-bit floating point value to a 80-bit one (fpu register).
58b7ab82f43487a8a838dbeb96387c0d27b527f1vboxsync; @param A0 FPU context (fxsave).
58b7ab82f43487a8a838dbeb96387c0d27b527f1vboxsync; @param A1 Pointer to a IEMFPURESULT for the output.
532262d2bfcb0d1b5e981972cf8ef2733ed63ddcvboxsync; @param A2 Pointer to the 64-bit floating point value to convert.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncBEGINPROC_FASTCALL iemAImpl_fld_r64_to_r80, 12
58b7ab82f43487a8a838dbeb96387c0d27b527f1vboxsync PROLOGUE_3_ARGS
58b7ab82f43487a8a838dbeb96387c0d27b527f1vboxsync sub xSP, 20h
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
58b7ab82f43487a8a838dbeb96387c0d27b527f1vboxsync fld qword [A2]
58b7ab82f43487a8a838dbeb96387c0d27b527f1vboxsync fnstsw word [A1 + IEMFPURESULT.FSW]
58b7ab82f43487a8a838dbeb96387c0d27b527f1vboxsync fstp tword [A1 + IEMFPURESULT.r80Result]
58b7ab82f43487a8a838dbeb96387c0d27b527f1vboxsync add xSP, 20h
58b7ab82f43487a8a838dbeb96387c0d27b527f1vboxsync EPILOGUE_3_ARGS 0
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncENDPROC iemAImpl_fld_r64_to_r80
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; Store a 80-bit floating point value (register) as a 64-bit one (memory).
cf1cd415fa1ad3b465ef4580e89341f556b63b9fvboxsync; @param A0 FPU context (fxsave).
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A1 Where to return the output FSW.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A2 Where to store the 64-bit value.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A3 Pointer to the 80-bit value.
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsyncBEGINPROC_FASTCALL iemAImpl_fst_r80_to_r64, 16
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync PROLOGUE_4_ARGS
cf1cd415fa1ad3b465ef4580e89341f556b63b9fvboxsync sub xSP, 20h
cf1cd415fa1ad3b465ef4580e89341f556b63b9fvboxsync fld tword [A3]
cf1cd415fa1ad3b465ef4580e89341f556b63b9fvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fst qword [A2]
cf1cd415fa1ad3b465ef4580e89341f556b63b9fvboxsync fnstsw word [A1]
cf1cd415fa1ad3b465ef4580e89341f556b63b9fvboxsync add xSP, 20h
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync EPILOGUE_4_ARGS 0
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncENDPROC iemAImpl_fst_r80_to_r64
53e42b967136278d8a79d9b0eec8c0ff70c390aavboxsync; FPU instruction working on one 80-bit and one 64-bit floating point value.
53e42b967136278d8a79d9b0eec8c0ff70c390aavboxsync; @param 1 The instruction
532262d2bfcb0d1b5e981972cf8ef2733ed63ddcvboxsync; @param A0 FPU context (fxsave).
532262d2bfcb0d1b5e981972cf8ef2733ed63ddcvboxsync; @param A1 Pointer to a IEMFPURESULT for the output.
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync; @param A2 Pointer to the 80-bit value.
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync; @param A3 Pointer to the 64-bit value.
53e42b967136278d8a79d9b0eec8c0ff70c390aavboxsync%macro IEMIMPL_FPU_R80_BY_R64 1
53e42b967136278d8a79d9b0eec8c0ff70c390aavboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r64, 16
532262d2bfcb0d1b5e981972cf8ef2733ed63ddcvboxsync PROLOGUE_4_ARGS
532262d2bfcb0d1b5e981972cf8ef2733ed63ddcvboxsync sub xSP, 20h
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync fld tword [A2]
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
53e42b967136278d8a79d9b0eec8c0ff70c390aavboxsync %1 qword [A3]
532262d2bfcb0d1b5e981972cf8ef2733ed63ddcvboxsync fnstsw word [A1 + IEMFPURESULT.FSW]
532262d2bfcb0d1b5e981972cf8ef2733ed63ddcvboxsync fstp tword [A1 + IEMFPURESULT.r80Result]
532262d2bfcb0d1b5e981972cf8ef2733ed63ddcvboxsync add xSP, 20h
532262d2bfcb0d1b5e981972cf8ef2733ed63ddcvboxsync EPILOGUE_4_ARGS 8
53e42b967136278d8a79d9b0eec8c0ff70c390aavboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80_by_r64
53e42b967136278d8a79d9b0eec8c0ff70c390aavboxsyncIEMIMPL_FPU_R80_BY_R64 fadd
53e42b967136278d8a79d9b0eec8c0ff70c390aavboxsyncIEMIMPL_FPU_R80_BY_R64 fmul
53e42b967136278d8a79d9b0eec8c0ff70c390aavboxsyncIEMIMPL_FPU_R80_BY_R64 fsub
53e42b967136278d8a79d9b0eec8c0ff70c390aavboxsyncIEMIMPL_FPU_R80_BY_R64 fsubr
53e42b967136278d8a79d9b0eec8c0ff70c390aavboxsyncIEMIMPL_FPU_R80_BY_R64 fdiv
53e42b967136278d8a79d9b0eec8c0ff70c390aavboxsyncIEMIMPL_FPU_R80_BY_R64 fdivr
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; FPU instruction working on one 80-bit and one 64-bit floating point value,
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; only returning FSW.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param 1 The instruction
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A0 FPU context (fxsave).
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A1 Where to store the output FSW.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A2 Pointer to the 80-bit value.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A3 Pointer to the 64-bit value.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync%macro IEMIMPL_FPU_R80_BY_R64_FSW 1
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r64, 16
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync PROLOGUE_4_ARGS
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync sub xSP, 20h
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fld tword [A2]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync %1 qword [A3]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fnstsw word [A1]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync add xSP, 20h
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync EPILOGUE_4_ARGS 8
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80_by_r64
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncIEMIMPL_FPU_R80_BY_R64_FSW fcom
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync;---------------------- 80-bit floating point operations ----------------------
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync; Loads a 80-bit floating point register value from memory.
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync; @param A0 FPU context (fxsave).
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync; @param A1 Pointer to a IEMFPURESULT for the output.
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync; @param A2 Pointer to the 80-bit floating point value to load.
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsyncBEGINPROC_FASTCALL iemAImpl_fld_r80_from_r80, 12
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync PROLOGUE_3_ARGS
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync sub xSP, 20h
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync fld tword [A2]
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync fnstsw word [A1 + IEMFPURESULT.FSW]
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync fstp tword [A1 + IEMFPURESULT.r80Result]
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync add xSP, 20h
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync EPILOGUE_3_ARGS 0
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsyncENDPROC iemAImpl_fld_r80_from_r80
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync; Store a 80-bit floating point register to memory
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync; @param A0 FPU context (fxsave).
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync; @param A1 Where to return the output FSW.
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync; @param A2 Where to store the 80-bit value.
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync; @param A3 Pointer to the 80-bit register value.
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsyncBEGINPROC_FASTCALL iemAImpl_fst_r80_to_r80, 16
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync PROLOGUE_4_ARGS
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync sub xSP, 20h
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync fld tword [A3]
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync fstp tword [A2]
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync fnstsw word [A1]
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsync add xSP, 20h
dd36ce0dc9d66ba9d471a63a33b6085260d54063vboxsync EPILOGUE_4_ARGS 0
7e0800bfa4bab140ca8d74f5764720fd136522afvboxsyncENDPROC iemAImpl_fst_r80_to_r80
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync; FPU instruction working on two 80-bit floating point values.
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync; @param 1 The instruction
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync; @param A0 FPU context (fxsave).
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync; @param A1 Pointer to a IEMFPURESULT for the output.
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync; @param A2 Pointer to the first 80-bit value (ST0)
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync; @param A3 Pointer to the second 80-bit value (STn).
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync%macro IEMIMPL_FPU_R80_BY_R80 2
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r80, 16
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync PROLOGUE_4_ARGS
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync sub xSP, 20h
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync fld tword [A3]
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync fld tword [A2]
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync fnstsw word [A1 + IEMFPURESULT.FSW]
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync fstp tword [A1 + IEMFPURESULT.r80Result]
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync add xSP, 20h
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsync EPILOGUE_4_ARGS 8
ce1318f291ab810c19aa03ce38d6a87679ba3af7vboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80_by_r80
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80_BY_R80 fadd, {st0, st1}
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80_BY_R80 fmul, {st0, st1}
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80_BY_R80 fsub, {st0, st1}
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80_BY_R80 fsubr, {st0, st1}
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80_BY_R80 fdiv, {st0, st1}
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80_BY_R80 fdivr, {st0, st1}
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80_BY_R80 fprem, {}
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80_BY_R80 fprem1, {}
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80_BY_R80 fscale, {}
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync; FPU instruction working on two 80-bit floating point values, ST1 and ST0,
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync; storing the result in ST1 and popping the stack.
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync; @param 1 The instruction
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync; @param A0 FPU context (fxsave).
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync; @param A1 Pointer to a IEMFPURESULT for the output.
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync; @param A2 Pointer to the first 80-bit value (ST1).
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync; @param A3 Pointer to the second 80-bit value (ST0).
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync%macro IEMIMPL_FPU_R80_BY_R80_ST1_ST0_POP 1
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r80, 16
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync PROLOGUE_4_ARGS
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync sub xSP, 20h
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync fld tword [A2]
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync fld tword [A3]
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync fnstsw word [A1 + IEMFPURESULT.FSW]
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync fstp tword [A1 + IEMFPURESULT.r80Result]
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync add xSP, 20h
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync EPILOGUE_4_ARGS 8
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80_by_r80
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80_BY_R80_ST1_ST0_POP fpatan
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80_BY_R80_ST1_ST0_POP fyl2xp1
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; FPU instruction working on two 80-bit floating point values, only
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; returning FSW.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param 1 The instruction
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A0 FPU context (fxsave).
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A1 Pointer to a uint16_t for the resulting FSW.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A2 Pointer to the first 80-bit value.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync; @param A3 Pointer to the second 80-bit value.
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync%macro IEMIMPL_FPU_R80_BY_R80_FSW 1
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r80, 16
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync PROLOGUE_4_ARGS
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync sub xSP, 20h
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fld tword [A3]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fld tword [A2]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync %1 st0, st1
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync fnstsw word [A1]
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync add xSP, 20h
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsync EPILOGUE_4_ARGS 8
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80_by_r80
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncIEMIMPL_FPU_R80_BY_R80_FSW fcom
5ca366bb4004d8335376abb1718d1cb9beedf4efvboxsyncIEMIMPL_FPU_R80_BY_R80_FSW fucom
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync; FPU instruction working on two 80-bit floating point values,
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync; returning FSW and EFLAGS (eax).
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync; @param 1 The instruction
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync; @returns EFLAGS in EAX.
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync; @param A0 FPU context (fxsave).
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync; @param A1 Pointer to a uint16_t for the resulting FSW.
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync; @param A2 Pointer to the first 80-bit value.
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync; @param A3 Pointer to the second 80-bit value.
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync%macro IEMIMPL_FPU_R80_BY_R80_EFL 1
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_by_r80, 16
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync PROLOGUE_4_ARGS
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync sub xSP, 20h
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync fld tword [A3]
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync fld tword [A2]
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync fnstsw word [A1]
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync add xSP, 20h
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsync EPILOGUE_4_ARGS 8
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80_by_r80
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsyncIEMIMPL_FPU_R80_BY_R80_EFL fcomi
8ae783bf7da7b2f0abb7b8d243b79aaafa35aa73vboxsyncIEMIMPL_FPU_R80_BY_R80_EFL fucomi
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; FPU instruction working on one 80-bit floating point value.
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; @param 1 The instruction
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; @param A0 FPU context (fxsave).
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; @param A1 Pointer to a IEMFPURESULT for the output.
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; @param A2 Pointer to the 80-bit value.
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync%macro IEMIMPL_FPU_R80 1
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80, 12
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync PROLOGUE_3_ARGS
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync sub xSP, 20h
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync fld tword [A2]
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync fnstsw word [A1 + IEMFPURESULT.FSW]
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync fstp tword [A1 + IEMFPURESULT.r80Result]
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync add xSP, 20h
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync EPILOGUE_3_ARGS 4
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncIEMIMPL_FPU_R80 fchs
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncIEMIMPL_FPU_R80 fabs
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsyncIEMIMPL_FPU_R80 f2xm1
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsyncIEMIMPL_FPU_R80 fyl2x
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80 fsqrt
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80 frndint
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80 fsin
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80 fcos
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; FPU instruction working on one 80-bit floating point value, only
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; returning FSW.
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; @param 1 The instruction
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; @param A0 FPU context (fxsave).
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; @param A1 Pointer to a uint16_t for the resulting FSW.
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; @param A2 Pointer to the 80-bit value.
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync%macro IEMIMPL_FPU_R80_FSW 1
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80, 12
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync PROLOGUE_3_ARGS
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync sub xSP, 20h
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync fld tword [A2]
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync fnstsw word [A1]
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync add xSP, 20h
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync EPILOGUE_3_ARGS 4
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncIEMIMPL_FPU_R80_FSW ftst
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncIEMIMPL_FPU_R80_FSW fxam
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; FPU instruction loading a 80-bit floating point constant.
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; @param 1 The instruction
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; @param A0 FPU context (fxsave).
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync; @param A1 Pointer to a IEMFPURESULT for the output.
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync%macro IEMIMPL_FPU_R80_CONST 1
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1, 8
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync PROLOGUE_2_ARGS
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync sub xSP, 20h
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync fnstsw word [A1 + IEMFPURESULT.FSW]
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync fstp tword [A1 + IEMFPURESULT.r80Result]
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync add xSP, 20h
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsync EPILOGUE_2_ARGS 0
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncENDPROC iemAImpl_ %+ %1 %+
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncIEMIMPL_FPU_R80_CONST fld1
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncIEMIMPL_FPU_R80_CONST fldl2t
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncIEMIMPL_FPU_R80_CONST fldl2e
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncIEMIMPL_FPU_R80_CONST fldpi
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncIEMIMPL_FPU_R80_CONST fldlg2
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncIEMIMPL_FPU_R80_CONST fldln2
44e92d62784be5a0b1410eb28c248a4603bbed40vboxsyncIEMIMPL_FPU_R80_CONST fldz
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync; FPU instruction working on one 80-bit floating point value, outputing two.
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync; @param 1 The instruction
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync; @param A0 FPU context (fxsave).
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync; @param A1 Pointer to a IEMFPURESULTTWO for the output.
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync; @param A2 Pointer to the 80-bit value.
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsync%macro IEMIMPL_FPU_R80_R80 1
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncBEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _r80_r80, 12
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync PROLOGUE_3_ARGS
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync sub xSP, 20h
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync fld tword [A2]
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync FPU_LD_FXSTATE_FCW_AND_SAFE_FSW A0
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync fnstsw word [A1 + IEMFPURESULTTWO.FSW]
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync fstp tword [A1 + IEMFPURESULTTWO.r80Result2]
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync fstp tword [A1 + IEMFPURESULTTWO.r80Result1]
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync add xSP, 20h
1bdc710f98c4004b2b449c82cf550224b5372f70vboxsync EPILOGUE_3_ARGS 4
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncENDPROC iemAImpl_ %+ %1 %+ _r80_r80
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80_R80 fptan
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80_R80 fxtract
14db9e3f0003e1e290ba2c50a3bf2bcf89750a4dvboxsyncIEMIMPL_FPU_R80_R80 fsincos