GIMAllKvm.cpp revision 66d96ba0c4c722996a3a1e6d92403a14a27db1b4
/* $Id$ */
/** @file
* GIM - Guest Interface Manager, KVM, All Contexts.
*/
/*
* Copyright (C) 2015 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_GIM
#include "GIMKvmInternal.h"
#include "GIMInternal.h"
#include <iprt/asm-amd64-x86.h>
/**
* Handles the KVM hypercall.
*
* @returns VBox status code.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest-CPU context.
*/
{
/*
* Get the hypercall operation and arguments.
*/
if (!fIs64BitMode)
{
}
/*
* Verify that guest ring-0 is the one making the hypercall.
*/
if (uCpl)
{
return VINF_SUCCESS;
}
/*
* Do the work.
*/
switch (uHyperOp)
{
{
{
#ifdef IN_RING0
#endif
}
break;
}
break;
default:
break;
}
/*
*/
return VINF_SUCCESS;
}
/**
* Returns whether the guest has configured and enabled the use of KVM's
* hypercall interface.
*
* @returns true if hypercalls are enabled, false otherwise.
* @param pVCpu Pointer to the VMCPU.
*/
{
/* KVM paravirt interface doesn't have hypercall control bits like Hyper-V does
that guests can control. It's always enabled. */
return true;
}
/**
* Returns whether the guest has configured and enabled the use of KVM's
* paravirtualized TSC.
*
* @returns true if paravirt. TSC is enabled, false otherwise.
* @param pVM Pointer to the VM.
*/
{
{
return true;
}
return false;
}
/**
* MSR read handler for KVM.
*
* @returns Strict VBox status code like CPUMQueryGuestMsr().
* @retval VINF_CPUM_R3_MSR_READ
* @retval VERR_CPUM_RAISE_GP_0
*
* @param pVCpu Pointer to the VMCPU.
* @param idMsr The MSR being read.
* @param pRange The range this MSR belongs to.
* @param puValue Where to store the MSR value read.
*/
VMM_INT_DECL(VBOXSTRICTRC) gimKvmReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
{
switch (idMsr)
{
case MSR_GIM_KVM_SYSTEM_TIME:
return VINF_SUCCESS;
case MSR_GIM_KVM_WALL_CLOCK:
return VINF_SUCCESS;
default:
{
#ifdef IN_RING3
if (s_cTimes++ < 20)
#endif
break;
}
}
return VERR_CPUM_RAISE_GP_0;
}
/**
* MSR write handler for KVM.
*
* @returns Strict VBox status code like CPUMSetGuestMsr().
* @retval VINF_CPUM_R3_MSR_WRITE
* @retval VERR_CPUM_RAISE_GP_0
*
* @param pVCpu Pointer to the VMCPU.
* @param idMsr The MSR being written.
* @param pRange The range this MSR belongs to.
* @param uRawValue The raw value with the ignored bits not masked.
*/
VMM_INT_DECL(VBOXSTRICTRC) gimKvmWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
{
switch (idMsr)
{
case MSR_GIM_KVM_SYSTEM_TIME:
{
#ifndef IN_RING3
if (fEnable)
{
}
return VINF_CPUM_R3_MSR_WRITE;
#else
if (!fEnable)
{
return VINF_SUCCESS;
}
/* Is the system-time struct. already enabled? If so, get flags that need preserving. */
{
int rc2 = PGMPhysSimpleReadGCPhys(pVM, &SystemTime, pKvmCpu->GCPhysSystemTime, sizeof(GIMKVMSYSTEMTIME));
if (RT_SUCCESS(rc2))
}
/* Enable and populate the system-time struct. */
if (RT_FAILURE(rc))
{
pKvmCpu->u64SystemTimeMsr = 0;
return VERR_CPUM_RAISE_GP_0;
}
return VINF_SUCCESS;
#endif /* IN_RING3 */
}
case MSR_GIM_KVM_WALL_CLOCK:
{
#ifndef IN_RING3
return VINF_CPUM_R3_MSR_WRITE;
#else
/* Enable the wall-clock struct. */
{
if (RT_SUCCESS(rc))
{
return VINF_SUCCESS;
}
}
return VERR_CPUM_RAISE_GP_0;
#endif /* IN_RING3 */
}
default:
{
#ifdef IN_RING3
if (s_cTimes++ < 20)
#endif
break;
}
}
return VERR_CPUM_RAISE_GP_0;
}
/**
* Whether we need to trap #UD exceptions in the guest.
*
* the Intel VMCALL instruction to make hypercalls and we need to trap and
* optionally patch them to the AMD-V VMMCALL instruction and handle the
* hypercall.
*
* I guess this was done so that guest teleporation between an AMD and an Intel
* machine would working without any changes at the time of teleporation.
* However, this also means we -always- need to intercept #UD exceptions on one
* of the two CPU models (Intel or AMD). Hyper-V solves this problem more
* elegantly by letting the hypervisor supply an opaque hypercall page.
*
* For raw-mode VMs, this function will always return true. See gimR3KvmInit().
*
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* Exception handler for #UD.
*
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest-CPU context.
* @param pDis Pointer to the disassembled instruction state at RIP.
* Optional, can be NULL.
*/
{
/*
* If we didn't ask for #UD to be trapped, bail.
*/
return VERR_GIM_OPERATION_FAILED;
/*
* Make sure guest ring-0 is the one making the hypercall.
*/
if (CPUMGetGuestCPL(pVCpu))
return VERR_GIM_HYPERCALL_ACCESS_DENIED;
int rc = VINF_SUCCESS;
if (!pDis)
{
/*
* Disassemble the instruction at RIP to figure out if it's the Intel
* VMCALL instruction and if so, handle it as a hypercall.
*/
}
if (RT_SUCCESS(rc))
{
/*
* Patch the instruction to so we don't have to spend time disassembling it each time.
* Makes sense only for HM as with raw-mode we will be getting a #UD regardless.
*/
{
&& HMIsEnabled(pVM))
{
}
/*
* Perform the hypercall and update RIP.
*
* For HM, we can simply resume guest execution without perform the hypercall now and
*
* For raw-mode we need to do this now anyway. So we do it here regardless with an added
* advantage is that it saves one world-switch for the HM case.
*/
if (RT_SUCCESS(rc))
{
}
return rc;
}
}
return VERR_GIM_OPERATION_FAILED;
}