GIMAllHv.cpp revision ce9f428fc2f581b4d8968d870967e259d9924d8d
/* $Id$ */
/** @file
* GIM - Guest Interface Manager, Microsoft Hyper-V, All Contexts.
*/
/*
* Copyright (C) 2014 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_GIM
#include "GIMHvInternal.h"
#include "GIMInternal.h"
#include <iprt/asm-amd64-x86.h>
#include <iprt/spinlock.h>
/**
* Handles the Hyper-V hypercall.
*
* @returns VBox status code.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest-CPU context.
*/
{
return VERR_GIM_HYPERCALLS_NOT_ENABLED;
/** @todo Handle hypercalls. Fail for now */
return VERR_GIM_IPE_3;
}
/**
* Returns whether the guest has configured and enabled the use of Hyper-V's
* hypercall interface.
*
* @returns true if hypercalls are enabled, false otherwise.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* Returns whether the guest has configured and enabled the use of Hyper-V's
* paravirtualized TSC.
*
* @returns true if paravirt. TSC is enabled, false otherwise.
* @param pVM Pointer to the VM.
*/
{
}
/**
* MSR read handler for Hyper-V.
*
* @returns VBox status code.
* @param pVCpu Pointer to the VMCPU.
* @param idMsr The MSR being read.
* @param pRange The range this MSR belongs to.
* @param puValue Where to store the MSR value read.
*/
VMM_INT_DECL(int) GIMHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
{
switch (idMsr)
{
{
/** @todo r=ramshankar: Shouldn't we add the TSC offset here? */
/* Hyper-V reports the time in 100 ns units (10 MHz). */
return VINF_SUCCESS;
}
case MSR_GIM_HV_VP_INDEX:
return VINF_SUCCESS;
case MSR_GIM_HV_TPR:
return VINF_SUCCESS;
case MSR_GIM_HV_EOI:
return VINF_SUCCESS;
case MSR_GIM_HV_ICR:
return VINF_SUCCESS;
case MSR_GIM_HV_GUEST_OS_ID:
return VINF_SUCCESS;
case MSR_GIM_HV_HYPERCALL:
return VINF_SUCCESS;
case MSR_GIM_HV_REF_TSC:
return VINF_SUCCESS;
case MSR_GIM_HV_TSC_FREQ:
return VINF_SUCCESS;
case MSR_GIM_HV_APIC_FREQ:
/** @todo Fix this later! Get the information from DevApic. */
return VINF_SUCCESS;
case MSR_GIM_HV_RESET:
*puValue = 0;
return VINF_SUCCESS;
default:
#ifdef IN_RING3
if (s_cTimes++ < 20)
#endif
break;
}
return VERR_CPUM_RAISE_GP_0;
}
/**
* MSR write handler for Hyper-V.
*
* @returns VBox status code.
* @param pVCpu Pointer to the VMCPU.
* @param idMsr The MSR being written.
* @param pRange The range this MSR belongs to.
* @param uRawValue The raw value with the ignored bits not masked.
*/
VMM_INT_DECL(int) GIMHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
{
switch (idMsr)
{
case MSR_GIM_HV_TPR:
return VINF_SUCCESS;
case MSR_GIM_HV_EOI:
return VINF_SUCCESS;
case MSR_GIM_HV_ICR:
return VINF_SUCCESS;
case MSR_GIM_HV_GUEST_OS_ID:
{
#ifndef IN_RING3
return VERR_EM_INTERPRETER;
#else
/* Disable the hypercall-page if 0 is written to this MSR. */
if (!uRawValue)
{
}
return VINF_SUCCESS;
#endif /* !IN_RING3 */
}
case MSR_GIM_HV_HYPERCALL:
{
#ifndef IN_RING3
return VERR_EM_INTERPRETER;
#else /* IN_RING3 */
/* First, update all but the hypercall enable bit. */
/* Hypercalls can only be enabled when the guest has set the Guest-OS Id Msr. */
if ( fEnable
&& !pHv->u64GuestOsIdMsr)
{
return VINF_SUCCESS;
}
/* Is the guest disabling the hypercall-page? Allow it regardless of the Guest-OS Id Msr. */
if (!fEnable)
{
return VINF_SUCCESS;
}
/* Enable the hypercall-page. */
if (RT_SUCCESS(rc))
{
return VINF_SUCCESS;
}
return VERR_CPUM_RAISE_GP_0;
#endif /* !IN_RING3 */
}
case MSR_GIM_HV_REF_TSC:
{
#ifndef IN_RING3
return VERR_EM_INTERPRETER;
#else /* IN_RING3 */
/* First, update all but the TSC-page enable bit. */
/* Is the guest disabling the TSC-page? */
if (!fEnable)
{
return VINF_SUCCESS;
}
/* Enable the TSC-page. */
int rc = GIMR3HvEnableTscPage(pVM, GCPhysTscPage, false /* fUseThisTscSequence */, 0 /* uTscSequence */);
if (RT_SUCCESS(rc))
{
return VINF_SUCCESS;
}
return VERR_CPUM_RAISE_GP_0;
#endif /* !IN_RING3 */
}
case MSR_GIM_HV_RESET:
{
#ifndef IN_RING3
return VERR_EM_INTERPRETER;
#else
{
LogRel(("GIM: HyperV: Reset initiated through MSR.\n"));
}
/* else: Ignore writes to other bits. */
return VINF_SUCCESS;
#endif /* !IN_RING3 */
}
case MSR_GIM_HV_TIME_REF_COUNT: /* Read-only MSRs. */
case MSR_GIM_HV_VP_INDEX:
case MSR_GIM_HV_TSC_FREQ:
case MSR_GIM_HV_APIC_FREQ:
return VERR_CPUM_RAISE_GP_0;
default:
#ifdef IN_RING3
if (s_cTimes++ < 20)
LogRel(("GIM: HyperV: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr, uRawValue & UINT64_C(0xffffffff00000000),
#endif
break;
}
return VERR_CPUM_RAISE_GP_0;
}