CPUMAllRegs.cpp revision 4d02c6ebc68acd1bdfa5a26f9bbcfb64cb8463ae
/* $Id$ */
/** @file
* CPUM - CPU Monitor(/Manager) - Getters and Setters.
*/
/*
* Copyright (C) 2006-2013 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_CPUM
#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
#endif
#include "CPUMInternal.h"
#include <iprt/asm-amd64-x86.h>
#ifdef IN_RING3
#endif
/** Disable stack frame pointer generation here. */
#endif
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
/**
* Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
*
* @returns Pointer to the Virtual CPU.
* @param a_pGuestCtx Pointer to the guest context.
*/
/**
* Lazily loads the hidden parts of a selector register when using raw-mode.
*/
#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
do \
{ \
} while (0)
#else
#endif
#ifdef VBOX_WITH_RAW_MODE_NOT_R0
/**
* Does the lazy hidden selector register loading.
*
* @param pVCpu The current Virtual CPU.
* @param pSReg The selector register to lazily load hidden parts of.
*/
{
{
/* V8086 mode - Tightly controlled environment, no question about the limit or flags. */
pSReg->Attr.n.u4Type = pSReg == &pVCpu->cpum.s.Guest.cs ? X86_SEL_TYPE_ER_ACC : X86_SEL_TYPE_RW_ACC;
/** @todo Check what the accessed bit should be (VT-x and AMD-V). */
}
{
/* Real mode - leave the limit and flags alone here, at least for now. */
}
else
{
/* Protected mode - get it from the selector descriptor tables. */
{
/** @todo see todo in iemHlpLoadNullDataSelectorProt. */
}
else
}
}
/**
* Makes sure the hidden CS and SS selector registers are valid, loading them if
* necessary.
*
* @param pVCpu The current virtual CPU.
*/
{
}
/**
* Loads a the hidden parts of a selector register.
*
* @param pVCpu The current virtual CPU.
*/
{
}
#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
/**
* Obsolete.
*
* We don't support nested hypervisor context interrupts or traps. Life is much
* simpler when we don't. It's also slightly faster at times.
*
* @param pVM Handle to the virtual machine.
*/
{
}
/**
* Gets the pointer to the hypervisor CPU context structure of a virtual CPU.
*
* @param pVCpu Pointer to the VMCPU.
*/
{
}
{
}
{
}
{
#ifdef IN_RC
/* Update the current CR3. */
#endif
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
return VINF_SUCCESS;
}
{
}
/**
* Used by VMMR3RawRunGC to reinitialize the general raw-mode context registers,
* EFLAGS and EIP prior to resuming guest execution.
*
* All general register not given as a parameter will be set to 0. The EFLAGS
* register will be set to sane values for C/C++ code execution with interrupts
* disabled and IOPL 0.
*
* @param pVCpu The current virtual CPU.
* @param u32EIP The EIP value.
* @param u32ESP The ESP value.
* @param u32EAX The EAX value.
* @param u32EDX The EDX value.
*/
VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX)
{
}
{
}
{
}
/** @MAYBE_LOAD_DRx
* Macro for updating DRx values in raw-mode and ring-0 contexts.
*/
#ifdef IN_RING0
# ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
do { \
else \
} while (0)
# else
do { \
/** @todo we're not loading the correct guest value here! */ \
} while (0)
# endif
# else
do { \
} while (0)
# endif
do { \
} while (0)
#else
#endif
{
}
{
}
{
}
{
}
{
}
{
#ifdef IN_RC
#endif
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
if (pcbLimit)
}
{
if (pcbLimit)
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
/**
* Gets the pointer to the internal CPUMCTXCORE structure.
* This is only for reading in order to save a few calls.
*
* @param pVCpu Handle to the virtual cpu.
*/
{
}
/**
* Queries the pointer to the internal CPUMCTX structure.
*
* @returns The CPUMCTX pointer.
* @param pVCpu Handle to the virtual cpu.
*/
{
}
{
#ifdef VBOX_WITH_IEM
# ifdef VBOX_WITH_RAW_MODE_NOT_R0
# endif
#endif
return VINF_SUCCESS; /* formality, consider it void. */
}
{
#ifdef VBOX_WITH_IEM
# ifdef VBOX_WITH_RAW_MODE_NOT_R0
# endif
#endif
return VINF_SUCCESS; /* formality, consider it void. */
}
{
#ifdef VBOX_WITH_IEM
# ifdef VBOX_WITH_RAW_MODE_NOT_R0
# endif
#endif
return VINF_SUCCESS; /* formality, consider it void. */
}
{
#ifdef VBOX_WITH_IEM
# ifdef VBOX_WITH_RAW_MODE_NOT_R0
if ( ( ldtr != 0
# endif
#endif
/* The caller will set more hidden bits if it has them. */
return VINF_SUCCESS; /* formality, consider it void. */
}
/**
* Set the guest CR0.
*
* When called in GC, the hyper CR0 may be updated if that is
* required. The caller only has to take special action if AM,
* WP, PG or PE changes.
*
* @returns VINF_SUCCESS (consider it void).
* @param pVCpu Handle to the virtual cpu.
* @param cr0 The new CR0 value.
*/
{
#ifdef IN_RC
/*
* Check if we need to change hypervisor CR0 because
* of math stuff.
*/
{
{
/*
* We haven't saved the host FPU state yet, so TS and MT are both set
* and EM should be reflecting the guest EM (it always does this).
*/
{
AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
HyperCR0 &= ~X86_CR0_EM;
}
# ifdef VBOX_STRICT
else
{
AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
}
# endif
}
else
{
/*
* Already saved the state, so we're just mirroring
* the guest flags.
*/
}
}
#endif /* IN_RC */
/*
* Check for changes causing TLB flushes (for REM).
* The caller is responsible for calling PGM when appropriate.
*/
/*
* Let PGM know if the WP goes from 0 to 1 (netware WP0+RO+US hack)
*/
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
cr4 &= ~X86_CR4_OSFSXR;
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
}
/**
* Worker for CPUMQueryGuestMsr().
*
* @retval VINF_SUCCESS
* @retval VERR_CPUM_RAISE_GP_0
* @param pVCpu The cross context CPU structure.
* @param idMsr The MSR to read.
* @param puValue Where to store the return value.
*/
{
/*
* If we don't indicate MSR support in the CPUID feature bits, indicate
* that a #GP(0) should be raised.
*/
{
*puValue = 0;
return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
}
int rc = VINF_SUCCESS;
switch (idMsr)
{
case MSR_IA32_TSC:
break;
case MSR_IA32_APICBASE:
{
{
}
else
{
*puValue = 0;
}
break;
}
case MSR_IA32_CR_PAT:
break;
case MSR_IA32_SYSENTER_CS:
break;
case MSR_IA32_SYSENTER_EIP:
break;
case MSR_IA32_SYSENTER_ESP:
break;
case MSR_IA32_MTRR_CAP:
{
/* This is currently a bit weird. :-) */
uint8_t const cVariableRangeRegs = 0;
bool const fSystemManagementRangeRegisters = false;
bool const fFixedRangeRegisters = false;
bool const fWriteCombiningType = false;
break;
}
case IA32_MTRR_PHYSBASE0: case IA32_MTRR_PHYSMASK0:
case IA32_MTRR_PHYSBASE1: case IA32_MTRR_PHYSMASK1:
case IA32_MTRR_PHYSBASE2: case IA32_MTRR_PHYSMASK2:
case IA32_MTRR_PHYSBASE3: case IA32_MTRR_PHYSMASK3:
case IA32_MTRR_PHYSBASE4: case IA32_MTRR_PHYSMASK4:
case IA32_MTRR_PHYSBASE5: case IA32_MTRR_PHYSMASK5:
case IA32_MTRR_PHYSBASE6: case IA32_MTRR_PHYSMASK6:
case IA32_MTRR_PHYSBASE7: case IA32_MTRR_PHYSMASK7:
/** @todo implement variable MTRRs. */
*puValue = 0;
break;
#if 0 /** @todo newer CPUs have more, figure since when and do selective GP(). */
case IA32_MTRR_PHYSBASE8: case IA32_MTRR_PHYSMASK8:
case IA32_MTRR_PHYSBASE9: case IA32_MTRR_PHYSMASK9:
*puValue = 0;
break;
#endif
case MSR_IA32_MTRR_DEF_TYPE:
break;
case IA32_MTRR_FIX64K_00000:
break;
case IA32_MTRR_FIX16K_80000:
break;
case IA32_MTRR_FIX16K_A0000:
break;
case IA32_MTRR_FIX4K_C0000:
break;
case IA32_MTRR_FIX4K_C8000:
break;
case IA32_MTRR_FIX4K_D0000:
break;
case IA32_MTRR_FIX4K_D8000:
break;
case IA32_MTRR_FIX4K_E0000:
break;
case IA32_MTRR_FIX4K_E8000:
break;
case IA32_MTRR_FIX4K_F0000:
break;
case IA32_MTRR_FIX4K_F8000:
break;
case MSR_K6_EFER:
break;
case MSR_K8_SF_MASK:
break;
case MSR_K6_STAR:
break;
case MSR_K8_LSTAR:
break;
case MSR_K8_CSTAR:
break;
case MSR_K8_FS_BASE:
break;
case MSR_K8_GS_BASE:
break;
case MSR_K8_KERNEL_GS_BASE:
break;
case MSR_K8_TSC_AUX:
break;
case MSR_IA32_PERF_STATUS:
/** @todo could really be not exactly correct, maybe use host's values */
break;
case MSR_IA32_FSB_CLOCK_STS:
/*
* Encoded as:
* 0 - 266
* 1 - 133
* 2 - 200
* 3 - return 166
* 5 - return 100
*/
break;
case MSR_IA32_PLATFORM_INFO:
break;
case MSR_IA32_THERM_STATUS:
/* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
break;
case MSR_IA32_MISC_ENABLE:
#if 0
/* Needs to be tested more before enabling. */
#else
/* Currenty we don't allow guests to modify enable MSRs. */
/** @todo: add more cpuid-controlled features this way. */
#endif
break;
/** @todo virtualize DEBUGCTL and relatives */
case MSR_IA32_DEBUGCTL:
*puValue = 0;
break;
#if 0 /*def IN_RING0 */
case MSR_IA32_PLATFORM_ID:
case MSR_IA32_BIOS_SIGN_ID:
{
/* Available since the P6 family. VT-x implies that this feature is present. */
if (idMsr == MSR_IA32_PLATFORM_ID)
else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
break;
}
/* no break */
#endif
/*
* The BIOS_SIGN_ID MSR and MSR_IA32_MCP_CAP et al exist on AMD64 as
* well, at least bulldozer have them. Windows 7 is querying them.
* XP has been observed querying MSR_IA32_MC0_CTL.
*/
case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
case MSR_IA32_MCG_CAP: /* fam/mod >= 6_01 */
case MSR_IA32_MCG_STATUS: /* indicated as not present in CAP */
/*case MSR_IA32_MCG_CTRL: - indicated as not present in CAP */
case MSR_IA32_MC0_CTL:
case MSR_IA32_MC0_STATUS:
*puValue = 0;
break;
/*
* Intel specifics MSRs:
*/
case MSR_P5_MC_ADDR:
case MSR_P5_MC_TYPE:
case MSR_P4_LASTBRANCH_TOS: /** @todo Are these branch regs still here on more recent CPUs? The documentation doesn't mention them for several archs. */
case MSR_P4_LASTBRANCH_0:
case MSR_P4_LASTBRANCH_1:
case MSR_P4_LASTBRANCH_2:
case MSR_P4_LASTBRANCH_3:
case MSR_IA32_PERFEVTSEL0: /* NetWare 6.5 wants the these four. (Bet on AMD as well.) */
case MSR_IA32_PERFEVTSEL1:
case MSR_IA32_PMC0:
case MSR_IA32_PMC1:
case MSR_IA32_PLATFORM_ID: /* fam/mod >= 6_01 */
case MSR_IA32_MPERF: /* intel_pstate depends on this but does a validation test */
case MSR_IA32_APERF: /* intel_pstate depends on this but does a validation test */
/*case MSR_IA32_BIOS_UPDT_TRIG: - write-only? */
case MSR_RAPL_POWER_UNIT:
case MSR_BBL_CR_CTL3: /* ca. core arch? */
case MSR_PKG_CST_CONFIG_CONTROL: /* Nahalem, Sandy Bridge */
*puValue = 0;
{
break;
}
/* Provide more plausive values for some of them. */
switch (idMsr)
{
case MSR_RAPL_POWER_UNIT:
16 /* 15.3 micro-Joules */,
10 /* 976 microseconds increments */,
0);
break;
case MSR_BBL_CR_CTL3:
1, /* bit 8 - L2 Enabled (R/W). */
0, /* bit 23 - L2 Not Present (RO). */
0);
break;
break;
}
break;
#if 0 /* Only on pentium CPUs! */
/* Event counters, not supported. */
case MSR_IA32_CESR:
case MSR_IA32_CTR0:
case MSR_IA32_CTR1:
*puValue = 0;
break;
#endif
/*
* AMD specific MSRs:
*/
case MSR_K8_SYSCFG:
case MSR_K8_INT_PENDING:
case MSR_K8_NB_CFG: /* (All known values are 0 on reset.) */
case MSR_K8_HWCR: /* Very interesting bits here. :) */
case MSR_K8_VM_CR: /* Windows 8 */
*puValue = 0;
{
return VERR_CPUM_RAISE_GP_0;
}
/* ignored */
break;
default:
/*
* Hand the X2APIC range to PDM and the APIC.
*/
if ( idMsr >= MSR_IA32_X2APIC_START
&& idMsr <= MSR_IA32_X2APIC_END)
{
if (RT_SUCCESS(rc))
rc = VINF_SUCCESS;
else
{
*puValue = 0;
}
}
else
{
*puValue = 0;
}
break;
}
return rc;
}
/**
* Query an MSR.
*
* The caller is responsible for checking privilege if the call is the result
* of a RDMSR instruction. We'll do the rest.
*
* @retval VINF_SUCCESS on success.
* @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
* expected to take the appropriate actions. @a *puValue is set to 0.
* @param pVCpu Pointer to the VMCPU.
* @param idMsr The MSR.
* @param puValue Where to return the value.
*
* @remarks This will always return the right values, even when we're in the
* recompiler.
*/
{
return rc;
}
/**
* Sets the MSR.
*
* The caller is responsible for checking privilege if the call is the result
* of a WRMSR instruction. We'll do the rest.
*
* @retval VINF_SUCCESS on success.
* @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
* appropriate actions.
*
* @param pVCpu Pointer to the VMCPU.
* @param idMsr The MSR id.
* @param uValue The value to set.
*
* @remarks Everyone changing MSR values, including the recompiler, shall do it
* by calling this method. This makes sure we have current values and
* that we trigger all the right actions when something changes.
*/
{
/*
* If we don't indicate MSR support in the CPUID feature bits, indicate
* that a #GP(0) should be raised.
*/
return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
int rc = VINF_SUCCESS;
switch (idMsr)
{
case MSR_IA32_MISC_ENABLE:
break;
case MSR_IA32_TSC:
break;
case MSR_IA32_APICBASE:
if (rc != VINF_SUCCESS)
break;
case MSR_IA32_CR_PAT:
break;
case MSR_IA32_SYSENTER_CS:
break;
case MSR_IA32_SYSENTER_EIP:
break;
case MSR_IA32_SYSENTER_ESP:
break;
case MSR_IA32_MTRR_CAP:
return VERR_CPUM_RAISE_GP_0;
case MSR_IA32_MTRR_DEF_TYPE:
|| ( (uValue & 0xff) != 0
{
return VERR_CPUM_RAISE_GP_0;
}
break;
case IA32_MTRR_PHYSBASE0: case IA32_MTRR_PHYSMASK0:
case IA32_MTRR_PHYSBASE1: case IA32_MTRR_PHYSMASK1:
case IA32_MTRR_PHYSBASE2: case IA32_MTRR_PHYSMASK2:
case IA32_MTRR_PHYSBASE3: case IA32_MTRR_PHYSMASK3:
case IA32_MTRR_PHYSBASE4: case IA32_MTRR_PHYSMASK4:
case IA32_MTRR_PHYSBASE5: case IA32_MTRR_PHYSMASK5:
case IA32_MTRR_PHYSBASE6: case IA32_MTRR_PHYSMASK6:
case IA32_MTRR_PHYSBASE7: case IA32_MTRR_PHYSMASK7:
/** @todo implement variable MTRRs. */
break;
#if 0 /** @todo newer CPUs have more, figure since when and do selective GP(). */
case IA32_MTRR_PHYSBASE8: case IA32_MTRR_PHYSMASK8:
case IA32_MTRR_PHYSBASE9: case IA32_MTRR_PHYSMASK9:
break;
#endif
case IA32_MTRR_FIX64K_00000:
break;
case IA32_MTRR_FIX16K_80000:
break;
case IA32_MTRR_FIX16K_A0000:
break;
case IA32_MTRR_FIX4K_C0000:
break;
case IA32_MTRR_FIX4K_C8000:
break;
case IA32_MTRR_FIX4K_D0000:
break;
case IA32_MTRR_FIX4K_D8000:
break;
case IA32_MTRR_FIX4K_E0000:
break;
case IA32_MTRR_FIX4K_E8000:
break;
case IA32_MTRR_FIX4K_F0000:
break;
case IA32_MTRR_FIX4K_F8000:
break;
/*
* AMD64 MSRs.
*/
case MSR_K6_EFER:
{
: 0;
/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
fMask |= MSR_K6_EFER_NXE;
fMask |= MSR_K6_EFER_LME;
fMask |= MSR_K6_EFER_SCE;
/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
{
Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
return VERR_CPUM_RAISE_GP_0;
}
/* There are a few more: e.g. MSR_K6_EFER_LMSLE */
AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
("Unexpected value %RX64\n", uValue));
/* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
{
/// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
/* Notify PGM about NXE changes. */
if ( (uOldEFER & MSR_K6_EFER_NXE)
}
break;
}
case MSR_K8_SF_MASK:
break;
case MSR_K6_STAR:
break;
case MSR_K8_LSTAR:
break;
case MSR_K8_CSTAR:
break;
case MSR_K8_FS_BASE:
break;
case MSR_K8_GS_BASE:
break;
case MSR_K8_KERNEL_GS_BASE:
break;
case MSR_K8_TSC_AUX:
break;
case MSR_IA32_DEBUGCTL:
/** @todo virtualize DEBUGCTL and relatives */
break;
/*
* Intel specifics MSRs:
*/
/*case MSR_IA32_PLATFORM_ID: - read-only */
case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
case MSR_IA32_BIOS_UPDT_TRIG: /* fam/mod >= 6_01 */
/*case MSR_IA32_MCP_CAP: - read-only */
/*case MSR_IA32_MCG_STATUS: - read-only */
/*case MSR_IA32_MCG_CTRL: - indicated as not present in CAP */
/*case MSR_IA32_MC0_CTL: - read-only? */
/*case MSR_IA32_MC0_STATUS: - read-only? */
{
return VERR_CPUM_RAISE_GP_0;
}
switch (idMsr)
{
{
{
Log(("MSR_PKG_CST_CONFIG_CONTROL: Write protected -> #GP\n"));
return VERR_CPUM_RAISE_GP_0;
}
static uint64_t s_fMask = UINT64_C(0x01f08407); /** @todo Only Nehalem has 24; Only Sandy has 27 and 28. */
static uint64_t s_fGpInvalid = UINT64_C(0xffffffff00ff0000); /** @todo figure out exactly what's off limits. */
{
return VERR_CPUM_RAISE_GP_0;
}
break;
}
}
/* ignored */
break;
/*
* AMD specific MSRs:
*/
case MSR_K8_SYSCFG: /** @todo can be written, but we ignore that for now. */
case MSR_K8_INT_PENDING: /** @todo can be written, but we ignore that for now. */
case MSR_K8_NB_CFG: /** @todo can be written; the apicid swapping might be used and would need saving, but probably unnecessary. */
{
return VERR_CPUM_RAISE_GP_0;
}
/* ignored */
break;
default:
/*
* Hand the X2APIC range to PDM and the APIC.
*/
if ( idMsr >= MSR_IA32_X2APIC_START
&& idMsr <= MSR_IA32_X2APIC_END)
{
if (rc != VINF_SUCCESS)
}
else
{
/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
/** @todo rc = VERR_CPUM_RAISE_GP_0 */
}
break;
}
return rc;
}
{
if (pcbLimit)
}
{
if (pHidden)
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
if (RT_FAILURE(rc))
u64 = 0;
return u64;
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
switch (iReg)
{
case DISCREG_CR0:
break;
case DISCREG_CR2:
break;
case DISCREG_CR3:
break;
case DISCREG_CR4:
break;
case DISCREG_CR8:
{
if (RT_FAILURE(rc))
{
*pValue = 0;
return rc;
}
break;
}
default:
return VERR_INVALID_PARAMETER;
}
return VINF_SUCCESS;
}
{
}
{
}
{
}
{
}
{
}
{
}
{
/* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
iReg += 2;
return VINF_SUCCESS;
}
{
}
/**
* Gets a CPUID leaf.
*
* @param pVCpu Pointer to the VMCPU.
* @param iLeaf The CPUID leaf to get.
* @param pEax Where to store the EAX value.
* @param pEbx Where to store the EBX value.
* @param pEcx Where to store the ECX value.
* @param pEdx Where to store the EDX value.
*/
VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
{
pCpuId = &pVM->cpum.s.aGuestCpuIdHyper[iLeaf - UINT32_C(0x40000000)]; /* Only report if HVP bit set. */
else
if ( iLeaf == 1)
{
/* Bits 31-24: Initial APIC ID */
}
if ( iLeaf == 4
&& cCurrentCacheIndex < 3
{
/* For type: 1 - data cache, 2 - i-cache, 3 - unified */
partitions = 1;
/* Those are only to shut up compiler, as they will always
get overwritten, and compiler should be able to figure that out */
switch (cCurrentCacheIndex)
{
case 0:
type = 1;
level = 1;
sharing = 1;
linesize = 64;
associativity = 8;
sets = 64;
break;
case 1:
level = 1;
type = 2;
sharing = 1;
linesize = 64;
associativity = 8;
sets = 64;
break;
default: /* shut up gcc.*/
AssertFailed();
case 2:
level = 2;
type = 3;
linesize = 64;
associativity = 24;
sets = 4096;
break;
}
(level << 5) |
1;
}
Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
}
/**
* Gets a number of standard CPUID leafs.
*
* @returns Number of leafs.
* @param pVM Pointer to the VM.
* @remark Intended for PATM.
*/
{
}
/**
* Gets a number of extended CPUID leafs.
*
* @returns Number of leafs.
* @param pVM Pointer to the VM.
* @remark Intended for PATM.
*/
{
}
/**
* Gets a number of centaur CPUID leafs.
*
* @returns Number of leafs.
* @param pVM Pointer to the VM.
* @remark Intended for PATM.
*/
{
}
/**
* Sets a CPUID feature bit.
*
* @param pVM Pointer to the VM.
* @param enmFeature The feature to set.
*/
{
switch (enmFeature)
{
/*
* Set the APIC bit in both feature masks.
*/
case CPUMCPUIDFEATURE_APIC:
LogRel(("CPUM: SetGuestCpuIdFeature: Enabled APIC\n"));
break;
/*
* Set the x2APIC bit in the standard feature mask.
*/
case CPUMCPUIDFEATURE_X2APIC:
LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
break;
/*
* Assumes the caller knows what it's doing! (host must support these)
*/
case CPUMCPUIDFEATURE_SEP:
{
{
AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
return;
}
break;
}
/*
* Assumes the caller knows what it's doing! (host must support these)
*/
case CPUMCPUIDFEATURE_SYSCALL:
{
{
#if HC_ARCH_BITS == 32
/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32 bits mode.
* Even when the cpu is capable of doing so in 64 bits mode.
*/
#endif
{
return;
}
}
/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
break;
}
/*
* Set the PAE bit in both feature masks.
* Assumes the caller knows what it's doing! (host must support these)
*/
case CPUMCPUIDFEATURE_PAE:
{
{
LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
return;
}
LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
break;
}
/*
* Set the LONG MODE bit in the extended feature mask.
* Assumes the caller knows what it's doing! (host must support these)
*/
{
{
LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
return;
}
/* Valid for both Intel and AMD. */
LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
break;
}
/*
* Assumes the caller knows what it's doing! (host must support these)
*/
case CPUMCPUIDFEATURE_NX:
{
{
return;
}
/* Valid for both Intel and AMD. */
LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
break;
}
/*
* Assumes the caller knows what it's doing! (host must support this)
*/
case CPUMCPUIDFEATURE_LAHF:
{
{
return;
}
/* Valid for both Intel and AMD. */
break;
}
case CPUMCPUIDFEATURE_PAT:
{
LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
break;
}
/*
* Set the RDTSCP support bit.
* Assumes the caller knows what it's doing! (host must support this)
*/
case CPUMCPUIDFEATURE_RDTSCP:
{
{
LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
return;
}
/* Valid for both Intel and AMD. */
LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
break;
}
/*
* Set the Hypervisor Present bit in the standard feature mask.
*/
case CPUMCPUIDFEATURE_HVP:
LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
break;
default:
break;
}
{
}
}
/**
* Queries a CPUID feature bit.
*
* @returns boolean for feature presence
* @param pVM Pointer to the VM.
* @param enmFeature The feature to query.
*/
{
switch (enmFeature)
{
case CPUMCPUIDFEATURE_PAE:
{
break;
}
case CPUMCPUIDFEATURE_NX:
{
}
case CPUMCPUIDFEATURE_SYSCALL:
{
}
case CPUMCPUIDFEATURE_RDTSCP:
{
break;
}
{
break;
}
default:
break;
}
return false;
}
/**
* Clears a CPUID feature bit.
*
* @param pVM Pointer to the VM.
* @param enmFeature The feature to clear.
*/
{
switch (enmFeature)
{
/*
* Set the APIC bit in both feature masks.
*/
case CPUMCPUIDFEATURE_APIC:
Log(("CPUM: ClearGuestCpuIdFeature: Disabled APIC\n"));
break;
/*
* Clear the x2APIC bit in the standard feature mask.
*/
case CPUMCPUIDFEATURE_X2APIC:
Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
break;
case CPUMCPUIDFEATURE_PAE:
{
Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
break;
}
case CPUMCPUIDFEATURE_PAT:
{
Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
break;
}
{
break;
}
case CPUMCPUIDFEATURE_LAHF:
{
break;
}
case CPUMCPUIDFEATURE_RDTSCP:
{
Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
break;
}
case CPUMCPUIDFEATURE_HVP:
break;
default:
break;
}
{
}
}
/**
* Gets the host CPU vendor.
*
* @returns CPU vendor.
* @param pVM Pointer to the VM.
*/
{
}
/**
* Gets the CPU vendor.
*
* @returns CPU vendor.
* @param pVM Pointer to the VM.
*/
{
}
{
return CPUMRecalcHyperDRx(pVCpu, 0, false);
}
{
}
{
}
{
}
{
return VINF_SUCCESS; /* No need to recalc. */
}
{
}
{
/* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
iReg += 2;
}
/**
* Recalculates the hypervisor DRx register values based on current guest
* registers and DBGF breakpoints, updating changed registers depending on the
* context.
*
* This is called whenever a guest DRx register is modified (any context) and
* when DBGF sets a hardware breakpoint (ring-3 only, rendezvous).
*
* In raw-mode context this function will reload any (hyper) DRx registers which
* comes out with a different value. It may also have to save the host debug
* registers if that haven't been done already. In this context though, we'll
* be intercepting and emulating all DRx accesses, so the hypervisor DRx values
* are only important when breakpoints are actually enabled.
*
* In ring-0 (HM) context DR0-3 will be relocated by us, while DR7 will be
* reloaded by the HM code if it changes. Further more, we will only use the
* combined register set when the VBox debugger is actually using hardware BPs,
* when it isn't we'll keep the guest DR0-3 + (maybe) DR6 loaded (DR6 doesn't
* concern us here).
*
* In ring-3 we won't be loading anything, so well calculate hypervisor values
* all the time.
*
* @returns VINF_SUCCESS.
* @param pVCpu Pointer to the VMCPU.
* @param iGstReg The guest debug register number that was modified.
* UINT8_MAX if not guest register.
* @param fForceHyper Used in HM to force hyper registers because of single
* stepping.
*/
{
/*
* Compare the DR7s first.
*
* We only care about the enabled flags. GD is virtualized when we
* dispatch the #DB, we never enable it. The DBGF DR7 value is will
* always have the LE and GE bits set, so no need to check and disable
* stuff if they're cleared like we have to for the guest DR7.
*/
uGstDr7 = 0;
else if (!(uGstDr7 & X86_DR7_LE))
uGstDr7 &= ~X86_DR7_LE_ALL;
else if (!(uGstDr7 & X86_DR7_GE))
uGstDr7 &= ~X86_DR7_GE_ALL;
#ifdef IN_RING0
fForceHyper = true;
#endif
if (( HMIsEnabled(pVCpu->CTX_SUFF(pVM)) && !fForceHyper ? uDbgfDr7 : (uGstDr7 | uDbgfDr7)) & X86_DR7_ENABLED_MASK)
{
#ifdef IN_RC
bool const fHmEnabled = false;
#endif
/*
* Ok, something is enabled. Recalc each of the breakpoints, taking
* the VM debugger ones of the guest ones. In raw-mode context we will
* not allow breakpoints with values inside the hypervisor area.
*/
/* bp 0 */
{
}
{
#ifndef IN_RING0
uNewDr0 = 0;
else
#endif
}
else
uNewDr0 = 0;
/* bp 1 */
{
}
{
#ifndef IN_RING0
uNewDr1 = 0;
else
#endif
}
else
uNewDr1 = 0;
/* bp 2 */
{
}
{
#ifndef IN_RING0
uNewDr2 = 0;
else
#endif
}
else
uNewDr2 = 0;
/* bp 3 */
{
}
{
#ifndef IN_RING0
uNewDr3 = 0;
else
#endif
}
else
uNewDr3 = 0;
/*
* Apply the updates.
*/
#ifdef IN_RC
/* Make sure to save host registers first. */
{
{
}
pVCpu->cpum.s.fUseFlags |= CPUM_USED_DEBUG_REGS_HOST | CPUM_USE_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HYPER;
/* We haven't loaded any hyper DRxes yet, so we'll have to load them all now. */
}
else
#endif
{
}
}
#ifdef IN_RING0
else if (CPUMIsGuestDebugStateActive(pVCpu))
{
/*
* Reload the register that was modified. Normally this won't happen
* as we won't intercept DRx writes when not having the hyper debug
* state loaded, but in case we do for some reason we'll simply deal
* with it.
*/
switch (iGstReg)
{
default:
}
}
#endif
else
{
/*
* No active debug state any more. In raw-mode this means we have to
* make sure DR7 has everything disabled now, if we armed it already.
* In ring-0 we might end up here when just single stepping.
*/
{
# ifdef IN_RC
# endif
ASMSetDR0(0);
ASMSetDR1(0);
ASMSetDR2(0);
ASMSetDR3(0);
}
#endif
/* Clear all the registers. */
}
Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
return VINF_SUCCESS;
}
/**
* Tests if the guest has No-Execute Page Protection Enabled (NXE).
*
* @returns true if in real mode, otherwise false.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* Tests if the guest has the Page Size Extension enabled (PSE).
*
* @returns true if in real mode, otherwise false.
* @param pVCpu Pointer to the VMCPU.
*/
{
/* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
}
/**
* Tests if the guest has the paging enabled (PG).
*
* @returns true if in real mode, otherwise false.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* Tests if the guest has the paging enabled (PG).
*
* @returns true if in real mode, otherwise false.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* Tests if the guest is running in real mode or not.
*
* @returns true if in real mode, otherwise false.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* Tests if the guest is running in real or virtual 8086 mode.
*
* @returns @c true if it is, @c false if not.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* Tests if the guest is running in protected or not.
*
* @returns true if in protected mode, otherwise false.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* Tests if the guest is running in paged protected or not.
*
* @returns true if in paged protected mode, otherwise false.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* Tests if the guest is running in long mode or not.
*
* @returns true if in long mode, otherwise false.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* Tests if the guest is running in PAE mode or not.
*
* @returns true if in PAE mode, otherwise false.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* Tests if the guest is running in 64 bits mode or not.
*
* @returns true if in 64 bits protected mode, otherwise false.
* @param pVCpu The current virtual CPU.
*/
{
if (!CPUMIsGuestInLongMode(pVCpu))
return false;
}
/**
* Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
* registers.
*
* @returns true if in 64 bits protected mode, otherwise false.
* @param pCtx Pointer to the current guest CPU context.
*/
{
}
#ifdef VBOX_WITH_RAW_MODE_NOT_R0
/**
*
* @returns @c true if we've entered raw-mode and selectors with RPL=1 are
* really RPL=0, @c false if we've not (RPL=1 really is RPL=1).
* @param pVCpu The current virtual CPU.
*/
{
}
/**
* Transforms the guest CPU state to raw-ring mode.
*
* This function will change the any of the cs and ss register with DPL=0 to DPL=1.
*
* @returns VBox status. (recompiler failure)
* @param pVCpu Pointer to the VMCPU.
* @param pCtxCore The context core (for trap usage).
* @see @ref pg_raw
*/
{
if (!pCtxCore)
/*
* Are we in Ring-0?
*/
{
/*
* Enter execution mode.
*/
/*
* Set CPL to Ring-1.
*/
}
else
{
# ifdef VBOX_WITH_RAW_RING1
if ( EMIsRawRing1Enabled(pVM)
{
/* Set CPL to Ring-2. */
}
# else
("ring-1 code not supported\n"));
# endif
/*
* PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
*/
}
/*
* Assert sanity.
*/
Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
return VINF_SUCCESS;
}
/**
* Transforms the guest CPU state from raw-ring mode to correct values.
*
* This function will change any selector registers with DPL=1 to DPL=0.
*
* @returns Adjusted rc.
* @param pVCpu Pointer to the VMCPU.
* @param rc Raw mode return code
* @param pCtxCore The context core (for trap usage).
* @see @ref pg_raw
*/
{
/*
* Don't leave if we've already left (in RC).
*/
return rc;
if (!pCtxCore)
AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL),
/*
* Are we executing in raw ring-1?
*/
{
/*
* Leave execution mode.
*/
/* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
/** @todo See what happens if we remove this. */
/*
* Ring-1 selector => Ring-0.
*/
}
else
{
/*
* PATM is taking care of the IOPL and IF flags for us.
*/
{
# ifdef VBOX_WITH_RAW_RING1
if ( EMIsRawRing1Enabled(pVM)
{
/* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
/** @todo See what happens if we remove this. */
/*
* Ring-2 selector => Ring-1.
*/
}
else
{
# endif
/** @todo See what happens if we remove this. */
# ifdef VBOX_WITH_RAW_RING1
}
# endif
}
}
return rc;
}
#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
/**
* Updates the EFLAGS while we're in raw-mode.
*
* @param pVCpu Pointer to the VMCPU.
* @param fEfl The new EFLAGS value.
*/
{
#ifdef VBOX_WITH_RAW_MODE_NOT_R0
else
#endif
}
/**
* Gets the EFLAGS while we're in raw-mode.
*
* @returns The eflags.
* @param pVCpu Pointer to the current virtual CPU.
*/
{
#ifdef VBOX_WITH_RAW_MODE_NOT_R0
#endif
}
/**
* Sets the specified changed flags (CPUM_CHANGED_*).
*
* @param pVCpu Pointer to the current virtual CPU.
*/
{
}
/**
* Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
* @returns true if supported.
* @returns false if not supported.
* @param pVM Pointer to the VM.
*/
{
}
/**
* Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
* @returns true if used.
* @returns false if not used.
* @param pVM Pointer to the VM.
*/
{
}
/**
* Checks if the host OS uses the SYSCALL / SYSRET instructions.
* @returns true if used.
* @returns false if not used.
* @param pVM Pointer to the VM.
*/
{
}
#ifndef IN_RING3
/**
*
* @returns VBox status code.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
#endif /* !IN_RING3 */
/**
* @returns true if we did.
* @returns false if not.
* @param pVCpu Pointer to the VMCPU.
*/
{
}
/**
* @param pVCpu Pointer to the VMCPU.
*
* @todo r=bird: Why is this needed? Looks like a workaround for mishandled
* FPU state management.
*/
{
}
/**
* Checks if the guest debug state is active.
*
* @returns boolean
* @param pVM Pointer to the VMCPU.
*/
{
}
/**
* Checks if the guest debug state is to be made active during the world-switch
* (currently only used for the 32->64 switcher case).
*
* @returns boolean
* @param pVM Pointer to the VMCPU.
*/
{
}
/**
* Checks if the hyper debug state is active.
*
* @returns boolean
* @param pVM Pointer to the VM.
*/
{
}
/**
* Checks if the hyper debug state is to be made active during the world-switch
* (currently only used for the 32->64 switcher case).
*
* @returns boolean
* @param pVM Pointer to the VMCPU.
*/
{
}
/**
* Mark the guest's debug state as inactive.
*
* @returns boolean
* @param pVM Pointer to the VM.
* @todo This API doesn't make sense any more.
*/
{
Assert(!(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER | CPUM_USED_DEBUG_REGS_HOST)));
}
/**
* Get the current privilege level of the guest.
*
* @returns CPL
* @param pVCpu Pointer to the current virtual CPU.
*/
{
/*
* CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
*
* Note! We used to check CS.DPL here, assuming it was always equal to
* CPL even if a conforming segment was loaded. But this truned out to
* only apply to older AMD-V. With VT-x we had an ACP2 regression
* during install after a far call to ring 2 with VT-x. Then on newer
* AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
* as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
*
* So, forget CS.DPL, always use SS.DPL.
*
* Note! The SS RPL is always equal to the CPL, while the CS RPL
* isn't necessarily equal if the segment is conforming.
* See section 4.11.1 in the AMD manual.
*
* Update: Where the heck does it say CS.RPL can differ from CPL other than
* right after real->prot mode switch and when in V8086 mode? That
* section says the RPL specified in a direct transfere (call, jmp,
* ret) is not the one loaded into CS. Besides, if CS.RPL != CPL
* it would be impossible for an exception handle or the iret
* instruction to figure out whether SS:ESP are part of the frame
* or not. VBox or qemu bug must've lead to this misconception.
*
* Update2: On an AMD bulldozer system here, I've no trouble loading a null
* selector into SS with an RPL other than the CPL when CPL != 3 and
* we're in 64-bit mode. The intel dev box doesn't allow this, on
* RPL = CPL. Weird.
*/
{
{
else
{
#ifdef VBOX_WITH_RAW_MODE_NOT_R0
# ifdef VBOX_WITH_RAW_RING1
{
if ( uCpl == 2
uCpl = 1;
else if (uCpl == 1)
uCpl = 0;
}
# else
if (uCpl == 1)
uCpl = 0;
# endif
#endif
}
}
else
}
else
uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
return uCpl;
}
/**
* Gets the current guest CPU mode.
*
* If paging mode is what you need, check out PGMGetGuestMode().
*
* @returns The CPU mode.
* @param pVCpu Pointer to the VMCPU.
*/
{
else
return enmMode;
}
/**
* Figure whether the CPU is currently executing 16, 32 or 64 bit code.
*
* @returns 16, 32 or 64.
* @param pVCpu The current virtual CPU.
*/
{
return 16;
{
return 16;
}
return 64;
return 32;
return 16;
}
{
return DISCPUMODE_16BIT;
{
return DISCPUMODE_16BIT;
}
return DISCPUMODE_64BIT;
return DISCPUMODE_32BIT;
return DISCPUMODE_16BIT;
}