CPUMAllRegs.cpp revision 4a296be15f381ac7f3506e4eb2861627d062fee3
/* $Id$ */
/** @file
* CPUM - CPU Monitor(/Manager) - Getters and Setters.
*/
/*
* Copyright (C) 2006-2007 Sun Microsystems, Inc.
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
* Clara, CA 95054 USA or visit http://www.sun.com if you need
* additional information or have any questions.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_CPUM
#include "CPUMInternal.h"
#ifdef IN_RING3
#endif
/** Disable stack frame pointer generation here. */
#endif
/**
* Sets or resets an alternative hypervisor context core.
*
* This is called when we get a hypervisor trap set switch the context
* core with the trap frame on the stack. It is called again to reset
* back to the default context core when resuming hypervisor execution.
*
* @param pVM The VM handle.
* @param pCtxCore Pointer to the alternative context core or NULL
* to go back to the default context core.
*/
{
if (!pCtxCore)
{
}
else
{
}
}
/**
* Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
* This is only for reading in order to save a few calls.
*
* @param pVM Handle to the virtual machine.
*/
{
}
/**
* Queries the pointer to the internal CPUMCTX structure for the hypervisor.
*
* @returns VBox status code.
* @param pVM Handle to the virtual machine.
* @param ppCtx Receives the hyper CPUMCTX pointer when successful.
*
* @deprecated This will *not* (and has never) given the right picture of the
* hypervisor register state. With CPUMHyperSetCtxCore() this is
* getting much worse. So, use the individual functions for getting
* and esp. setting the hypervisor registers.
*/
{
return VINF_SUCCESS;
}
{
}
{
}
{
#ifdef IN_RC
/* Update the current CR3. */
#endif
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
return VINF_SUCCESS;
}
{
}
{
}
{
}
{
/** @todo in GC we must load it! */
}
{
/** @todo in GC we must load it! */
}
{
/** @todo in GC we must load it! */
}
{
/** @todo in GC we must load it! */
}
{
/** @todo in GC we must load it! */
}
{
/** @todo in GC we must load it! */
}
{
}
{
}
{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
}
{
}
{
}
{
if (pcbLimit)
}
{
if (pcbLimit)
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
/**
* Gets the pointer to the internal CPUMCTXCORE structure.
* This is only for reading in order to save a few calls.
*
* @param pVM Handle to the virtual machine.
*/
{
}
/**
* Gets the pointer to the internal CPUMCTXCORE structure.
* This is only for reading in order to save a few calls.
*
* @param pVM Handle to the virtual machine.
*/
{
}
/**
* Sets the guest context core registers.
*
* @param pVM Handle to the virtual machine.
* @param pCtxCore The new context core values.
*/
{
/** @todo #1410 requires selectors to be checked. (huh? 1410?) */
*pCtxCoreDst = *pCtxCore;
/* Mask away invalid parts of the cpu context. */
if (!CPUMIsGuestInLongMode(pVM))
{
pCtxCoreDst->r8 = 0;
pCtxCoreDst->r9 = 0;
pCtxCoreDst->r10 = 0;
pCtxCoreDst->r11 = 0;
pCtxCoreDst->r12 = 0;
pCtxCoreDst->r13 = 0;
pCtxCoreDst->r14 = 0;
pCtxCoreDst->r15 = 0;
}
}
/**
* Queries the pointer to the internal CPUMCTX structure
*
* @returns The CPUMCTX pointer.
* @param pVM Handle to the virtual machine.
*/
{
}
{
}
{
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
/**
* Set the guest CR0.
*
* When called in GC, the hyper CR0 may be updated if that is
* required. The caller only has to take special action if AM,
* WP, PG or PE changes.
*
* @returns VINF_SUCCESS (consider it void).
* @param pVM Pointer to the shared VM structure.
* @param cr0 The new CR0 value.
*/
{
#ifdef IN_RC
/*
* Check if we need to change hypervisor CR0 because
* of math stuff.
*/
{
{
/*
* We haven't saved the host FPU state yet, so TS and MT are both set
* and EM should be reflecting the guest EM (it always does this).
*/
{
AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
HyperCR0 &= ~X86_CR0_EM;
}
# ifdef VBOX_STRICT
else
{
AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
}
# endif
}
else
{
/*
* Already saved the state, so we're just mirroring
* the guest flags.
*/
}
}
#endif /* IN_RC */
/*
* Check for changes causing TLB flushes (for REM).
* The caller is responsible for calling PGM when appropriate.
*/
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
if (!CPUMSupportsFXSR(pVM))
cr4 &= ~X86_CR4_OSFSXR;
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
return VINF_SUCCESS;
}
{
}
{
switch (idMsr)
{
case MSR_IA32_CR_PAT:
break;
case MSR_IA32_SYSENTER_CS:
break;
case MSR_IA32_SYSENTER_EIP:
break;
case MSR_IA32_SYSENTER_ESP:
break;
case MSR_K6_EFER:
break;
case MSR_K8_SF_MASK:
break;
case MSR_K6_STAR:
break;
case MSR_K8_LSTAR:
break;
case MSR_K8_CSTAR:
break;
case MSR_K8_KERNEL_GS_BASE:
break;
case MSR_K8_TSC_AUX:
break;
/* fs & gs base skipped on purpose as the current context might not be up-to-date. */
default:
AssertFailed();
break;
}
return u64;
}
{
/* On purpose only a limited number of MSRs; use the emulation function to update the others. */
switch (idMsr)
{
case MSR_K8_TSC_AUX:
break;
default:
AssertFailed();
break;
}
}
{
if (pcbLimit)
}
{
}
{
}
{
}
{
}
{
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{
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///@todo: crx should be an array
{
switch (iReg)
{
case USE_REG_CR0:
break;
case USE_REG_CR2:
break;
case USE_REG_CR3:
break;
case USE_REG_CR4:
break;
default:
return VERR_INVALID_PARAMETER;
}
return VINF_SUCCESS;
}
{
}
{
}
{
}
{
}
{
}
{
}
{
/* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
iReg += 2;
return VINF_SUCCESS;
}
{
}
/**
* Gets a CpuId leaf.
*
* @param pVM The VM handle.
* @param iLeaf The CPUID leaf to get.
* @param pEax Where to store the EAX value.
* @param pEbx Where to store the EBX value.
* @param pEcx Where to store the ECX value.
* @param pEdx Where to store the EDX value.
*/
VMMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
{
else
Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
}
/**
* Gets a pointer to the array of standard CPUID leafs.
*
* CPUMGetGuestCpuIdStdMax() give the size of the array.
*
* @returns Pointer to the standard CPUID leafs (read-only).
* @param pVM The VM handle.
* @remark Intended for PATM.
*/
{
}
/**
* Gets a pointer to the array of extended CPUID leafs.
*
* CPUMGetGuestCpuIdExtMax() give the size of the array.
*
* @returns Pointer to the extended CPUID leafs (read-only).
* @param pVM The VM handle.
* @remark Intended for PATM.
*/
{
}
/**
* Gets a pointer to the array of centaur CPUID leafs.
*
* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
*
* @returns Pointer to the centaur CPUID leafs (read-only).
* @param pVM The VM handle.
* @remark Intended for PATM.
*/
{
}
/**
* Gets a pointer to the default CPUID leaf.
*
* @returns Pointer to the default CPUID leaf (read-only).
* @param pVM The VM handle.
* @remark Intended for PATM.
*/
{
}
/**
* Gets a number of standard CPUID leafs.
*
* @returns Number of leafs.
* @param pVM The VM handle.
* @remark Intended for PATM.
*/
{
}
/**
* Gets a number of extended CPUID leafs.
*
* @returns Number of leafs.
* @param pVM The VM handle.
* @remark Intended for PATM.
*/
{
}
/**
* Gets a number of centaur CPUID leafs.
*
* @returns Number of leafs.
* @param pVM The VM handle.
* @remark Intended for PATM.
*/
{
}
/**
* Sets a CPUID feature bit.
*
* @param pVM The VM Handle.
* @param enmFeature The feature to set.
*/
{
switch (enmFeature)
{
/*
* Set the APIC bit in both feature masks.
*/
case CPUMCPUIDFEATURE_APIC:
LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
break;
/*
* Set the x2APIC bit in the standard feature mask.
*/
case CPUMCPUIDFEATURE_X2APIC:
LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
break;
/*
* Assumes the caller knows what it's doing! (host must support these)
*/
case CPUMCPUIDFEATURE_SEP:
{
{
AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
return;
}
break;
}
/*
* Assumes the caller knows what it's doing! (host must support these)
*/
case CPUMCPUIDFEATURE_SYSCALL:
{
{
#if HC_ARCH_BITS == 32
/* X86_CPUID_AMD_FEATURE_EDX_SEP not set it seems in 32 bits mode.
* Even when the cpu is capable of doing so in 64 bits mode.
*/
#endif
{
return;
}
}
/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
break;
}
/*
* Set the PAE bit in both feature masks.
* Assumes the caller knows what it's doing! (host must support these)
*/
case CPUMCPUIDFEATURE_PAE:
{
{
LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
return;
}
LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
break;
}
/*
* Set the LONG MODE bit in the extended feature mask.
* Assumes the caller knows what it's doing! (host must support these)
*/
{
{
LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
return;
}
/* Valid for both Intel and AMD. */
LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
break;
}
/*
* Set the NXE bit in the extended feature mask.
* Assumes the caller knows what it's doing! (host must support these)
*/
case CPUMCPUIDFEATURE_NXE:
{
{
LogRel(("WARNING: Can't turn on NXE when the host doesn't support it!!\n"));
return;
}
/* Valid for both Intel and AMD. */
LogRel(("CPUMSetGuestCpuIdFeature: Enabled NXE\n"));
break;
}
case CPUMCPUIDFEATURE_LAHF:
{
{
return;
}
break;
}
case CPUMCPUIDFEATURE_PAT:
{
LogRel(("CPUMClearGuestCpuIdFeature: Enabled PAT\n"));
break;
}
case CPUMCPUIDFEATURE_RDTSCP:
{
{
LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
return;
}
/* Valid for AMD only (for now). */
LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
break;
}
default:
break;
}
}
/**
* Queries a CPUID feature bit.
*
* @returns boolean for feature presence
* @param pVM The VM Handle.
* @param enmFeature The feature to query.
*/
{
switch (enmFeature)
{
case CPUMCPUIDFEATURE_PAE:
{
break;
}
case CPUMCPUIDFEATURE_RDTSCP:
{
break;
}
{
break;
}
default:
break;
}
return false;
}
/**
* Clears a CPUID feature bit.
*
* @param pVM The VM Handle.
* @param enmFeature The feature to clear.
*/
{
switch (enmFeature)
{
/*
* Set the APIC bit in both feature masks.
*/
case CPUMCPUIDFEATURE_APIC:
Log(("CPUMSetGuestCpuIdFeature: Disabled APIC\n"));
break;
/*
* Clear the x2APIC bit in the standard feature mask.
*/
case CPUMCPUIDFEATURE_X2APIC:
LogRel(("CPUMSetGuestCpuIdFeature: Disabled x2APIC\n"));
break;
case CPUMCPUIDFEATURE_PAE:
{
LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
break;
}
case CPUMCPUIDFEATURE_PAT:
{
LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
break;
}
{
break;
}
case CPUMCPUIDFEATURE_LAHF:
{
break;
}
default:
break;
}
}
/**
* Gets the CPU vendor
*
* @returns CPU vendor
* @param pVM The VM handle.
*/
{
}
{
return CPUMRecalcHyperDRx(pVM);
}
{
return CPUMRecalcHyperDRx(pVM);
}
{
return CPUMRecalcHyperDRx(pVM);
}
{
return CPUMRecalcHyperDRx(pVM);
}
{
return CPUMRecalcHyperDRx(pVM);
}
{
return CPUMRecalcHyperDRx(pVM);
}
{
/* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
iReg += 2;
return CPUMRecalcHyperDRx(pVM);
}
/**
* Recalculates the hypvervisor DRx register values based on
* current guest registers and DBGF breakpoints.
*
* This is called whenever a guest DRx register is modified and when DBGF
* sets a hardware breakpoint. In guest context this function will reload
* any (hyper) DRx registers which comes out with a different value.
*
* @returns VINF_SUCCESS.
* @param pVM The VM handle.
*/
{
/*
* Compare the DR7s first.
*
* We only care about the enabled flags. The GE and LE flags are always
* set and we don't care if the guest doesn't set them. GD is virtualized
* when we dispatch #DB, we never enable it.
*/
#ifdef CPUM_VIRTUALIZE_DRX
#else
const RTGCUINTREG uGstDr7 = 0;
#endif
{
/*
* Ok, something is enabled. Recalc each of the breakpoints.
*/
/* bp 0 */
{
}
{
}
else
/* bp 1 */
{
}
{
}
else
/* bp 2 */
{
}
{
}
else
/* bp 3 */
{
}
{
}
else
/*
* Apply the updates.
*/
#ifdef IN_RC
{
/** @todo save host DBx registers. */
}
#endif
}
else
{
#ifdef IN_RC
{
/** @todo restore host DBx registers. */
}
#endif
}
Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
return VINF_SUCCESS;
}
#ifndef IN_RING0 /** @todo I don't think we need this in R0, so move it to CPUMAll.cpp? */
/**
* Transforms the guest CPU state to raw-ring mode.
*
* This function will change the any of the cs and ss register with DPL=0 to DPL=1.
*
* @returns VBox status. (recompiler failure)
* @param pVM VM handle.
* @param pCtxCore The context core (for trap usage).
* @see @ref pg_raw
*/
{
if (!pCtxCore)
/*
* Are we in Ring-0?
*/
{
/*
* Enter execution mode.
*/
/*
* Set CPL to Ring-1.
*/
}
else
{
("ring-1 code not supported\n"));
/*
* PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
*/
}
/*
* Assert sanity.
*/
Assert((pCpumCpu->Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
return VINF_SUCCESS;
}
/**
* Transforms the guest CPU state from raw-ring mode to correct values.
*
* This function will change any selector registers with DPL=1 to DPL=0.
*
* @returns Adjusted rc.
* @param pVM VM handle.
* @param rc Raw mode return code
* @param pCtxCore The context core (for trap usage).
* @see @ref pg_raw
*/
{
/*
* Don't leave if we've already left (in GC).
*/
return rc;
if (!pCtxCore)
AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
/*
* Are we executing in raw ring-1?
*/
{
/*
* Leave execution mode.
*/
/* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
/** @todo See what happens if we remove this. */
/*
* Ring-1 selector => Ring-0.
*/
}
else
{
/*
* PATM is taking care of the IOPL and IF flags for us.
*/
{
/** @todo See what happens if we remove this. */
}
}
return rc;
}
/**
* Updates the EFLAGS while we're in raw-mode.
*
* @param pVM The VM handle.
* @param pCtxCore The context core.
* @param eflags The new EFLAGS value.
*/
{
{
return;
}
}
#endif /* !IN_RING0 */
/**
* Gets the EFLAGS while we're in raw-mode.
*
* @returns The eflags.
* @param pVM The VM handle.
* @param pCtxCore The context core.
*/
{
#ifdef IN_RING0
#else
#endif
}
/**
* Gets and resets the changed flags (CPUM_CHANGED_*).
* Only REM should call this function.
*
* @returns The changed flags.
* @param pVM The VM handle.
*/
{
/** @todo change the switcher to use the fChanged flags. */
{
}
return fFlags;
}
/**
* Sets the specified changed flags (CPUM_CHANGED_*).
*
* @param pVM The VM handle.
*/
{
}
/**
* Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
* @returns true if supported.
* @returns false if not supported.
* @param pVM The VM handle.
*/
{
}
/**
* Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
* @returns true if used.
* @returns false if not used.
* @param pVM The VM handle.
*/
{
}
/**
* Checks if the host OS uses the SYSCALL / SYSRET instructions.
* @returns true if used.
* @returns false if not used.
* @param pVM The VM handle.
*/
{
}
#ifndef IN_RING3
/**
*
* @returns VBox status code.
* @param pVM VM handle.
* @param pVCpu VMCPU handle
*/
{
}
#endif /* !IN_RING3 */
/**
* @returns true if we did.
* @returns false if not.
* @param pVCpu The VMCPU handle.
*/
{
}
/**
* @param pVM The VM handle.
*/
{
}
/**
* Checks if the guest debug state is active
*
* @returns boolean
* @param pVM VM handle.
*/
{
}
/**
* Mark the guest's debug state as inactive
*
* @returns boolean
* @param pVM VM handle.
*/
{
}
/**
* Checks if the hidden selector registers are valid
* @returns true if they are.
* @returns false if not.
* @param pVM The VM handle.
*/
{
}
/**
* Checks if the hidden selector registers are valid
* @param pVM The VM handle.
* @param fValid Valid or not
*/
{
}
/**
* Get the current privilege level of the guest.
*
* @returns cpl
* @param pVM VM Handle.
* @param pRegFrame Trap register frame.
*/
{
if (CPUMAreHiddenSelRegsValid(pVM))
{
/*
* The hidden CS.DPL register is always equal to the CPL, it is
* not affected by loading a conforming coding segment.
*
* This only seems to apply to AMD-V; in the VT-x case we *do* need to look
* at SS. (ACP2 regression during install after a far call to ring 2)
*/
else
cpl = 0; /* CPL set to 3 for VT-x real-mode emulation. */
}
{
{
/*
* The SS RPL is always equal to the CPL, while the CS RPL
* isn't necessarily equal if the segment is conforming.
* See section 4.11.1 in the AMD manual.
*/
#ifndef IN_RING0
if (cpl == 1)
cpl = 0;
#endif
}
else
cpl = 3;
}
else
cpl = 0; /* real mode; cpl is zero */
return cpl;
}
/**
* Gets the current guest CPU mode.
*
* If paging mode is what you need, check out PGMGetGuestMode().
*
* @returns The CPU mode.
* @param pVM The VM handle.
*/
{
else
return enmMode;
}