CPUMAllMsrs.cpp revision 41d680dd6eb0287afc200adc5b0d61b07a32b72d
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync * CPUM - CPU MSR Registers.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * Copyright (C) 2013 Oracle Corporation
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync * available from http://www.virtualbox.org. This file is free software;
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync * you can redistribute it and/or modify it under the terms of the GNU
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync * General Public License (GPL) as published by the Free Software
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
76c5ade78ff18423f4a3aed5cf7fcc84b1c0933bvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/*******************************************************************************
76c5ade78ff18423f4a3aed5cf7fcc84b1c0933bvboxsync* Header Files *
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync*******************************************************************************/
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/*******************************************************************************
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync* Defined Constants And Macros *
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync*******************************************************************************/
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * pointing to it.
2a2095adf36a009010d72cf36ffabb3c1261ad08vboxsync * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * correctly.
444f91a8285333437cdc9da6bf750121b52f208dvboxsync#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/*******************************************************************************
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync* Structures and Typedefs *
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync*******************************************************************************/
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * Implements reading one or more MSRs.
ede381e58d677545f69d56df0b26b1959d1b9fbfvboxsync * @returns VBox status code.
ede381e58d677545f69d56df0b26b1959d1b9fbfvboxsync * @retval VINF_SUCCESS on success.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * @param pVCpu Pointer to the VMCPU.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * @param idMsr The MSR we're reading.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * @param pRange The MSR range descriptor.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * @param puValue Where to return the value.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsynctypedef DECLCALLBACK(int) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * Implements writing one or more MSRs.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * @retval VINF_SUCCESS on success.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * @retval VERR_CPUM_RAISE_GP_0 on failure.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * @param pVCpu Pointer to the VMCPU.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * @param idMsr The MSR we're writing.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * @param pRange The MSR range descriptor.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * @param uValue The value to set.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsynctypedef DECLCALLBACK(int) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue);
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * Generic functions.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * Generic functions.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * Generic functions.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
b97d0f715f8fe39ceb7d4138427da4a0030ff65fvboxsync/** @callback_method_impl{FNCPUMRDMSR} */
b97d0f715f8fe39ceb7d4138427da4a0030ff65fvboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
b97d0f715f8fe39ceb7d4138427da4a0030ff65fvboxsync *puValue = 0; /** @todo implement machine check injection. */
b97d0f715f8fe39ceb7d4138427da4a0030ff65fvboxsync/** @callback_method_impl{FNCPUMWRMSR} */
b97d0f715f8fe39ceb7d4138427da4a0030ff65fvboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
ede381e58d677545f69d56df0b26b1959d1b9fbfvboxsync /** @todo implement machine check injection. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync *puValue = 0; /** @todo implement machine check injection. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo implement machine check injection. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
3d0c9ab568ff32132049431e7dc45ea82cda6089vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync Log(("CPUM: %s, apic not present -> GP\n", pRange->szName));
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync *puValue = 1; /* Locked, no VT-X, no SYSENTER micromanagement. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo Fake bios update trigger better. The value is the address to an
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * update package, I think. We should probably GP if it's invalid. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsync /** @todo SMM. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
444f91a8285333437cdc9da6bf750121b52f208dvboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo SMM. */
444f91a8285333437cdc9da6bf750121b52f208dvboxsync/** @callback_method_impl{FNCPUMRDMSR} */
444f91a8285333437cdc9da6bf750121b52f208dvboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo check CPUID leaf 0ah. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2a2095adf36a009010d72cf36ffabb3c1261ad08vboxsync /** @todo check CPUID leaf 0ah. */
b97d0f715f8fe39ceb7d4138427da4a0030ff65fvboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync *puValue = 0x40; /** @todo Change to CPU cache line size. */
444f91a8285333437cdc9da6bf750121b52f208dvboxsync/** @callback_method_impl{FNCPUMWRMSR} */
444f91a8285333437cdc9da6bf750121b52f208dvboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo should remember writes, though it's supposedly something only a BIOS
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * would write so, it's not extremely important. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
444f91a8285333437cdc9da6bf750121b52f208dvboxsync /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
444f91a8285333437cdc9da6bf750121b52f208dvboxsync * what we want? */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
444f91a8285333437cdc9da6bf750121b52f208dvboxsync /** @todo Write MPERF: Calc adjustment. */
76c5ade78ff18423f4a3aed5cf7fcc84b1c0933bvboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
76c5ade78ff18423f4a3aed5cf7fcc84b1c0933bvboxsync /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
76c5ade78ff18423f4a3aed5cf7fcc84b1c0933bvboxsync * what we want? */
2a2095adf36a009010d72cf36ffabb3c1261ad08vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2a2095adf36a009010d72cf36ffabb3c1261ad08vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
76c5ade78ff18423f4a3aed5cf7fcc84b1c0933bvboxsync /** @todo Write APERF: Calc adjustment. */
b97d0f715f8fe39ceb7d4138427da4a0030ff65fvboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /* This is currently a bit weird. :-) */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync bool const fSystemManagementRangeRegisters = false;
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync bool const fFixedRangeRegisters = false;
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync bool const fWriteCombiningType = false;
76c5ade78ff18423f4a3aed5cf7fcc84b1c0933bvboxsync | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
76c5ade78ff18423f4a3aed5cf7fcc84b1c0933bvboxsync /** @todo Implement variable MTRR storage. */
76c5ade78ff18423f4a3aed5cf7fcc84b1c0933bvboxsync Assert(pRange->uInitOrReadValue == (idMsr - 0x200) / 2);
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
5a1e3fdfddd9fb23f043efc077dae781b9691c23vboxsync * Validate the value.
5a1e3fdfddd9fb23f043efc077dae781b9691c23vboxsync Assert(pRange->uInitOrReadValue == (idMsr - 0x200) / 2);
5a1e3fdfddd9fb23f043efc077dae781b9691c23vboxsync Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uValue & 0xff));
76c5ade78ff18423f4a3aed5cf7fcc84b1c0933bvboxsync uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
76c5ade78ff18423f4a3aed5cf7fcc84b1c0933bvboxsync Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync * Store it.
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync /** @todo Implement variable MTRR storage. */
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync/** @callback_method_impl{FNCPUMRDMSR} */
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync /** @todo Implement variable MTRR storage. */
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync Assert(pRange->uInitOrReadValue == (idMsr - 0x200) / 2);
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync/** @callback_method_impl{FNCPUMWRMSR} */
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync * Validate the value.
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync Assert(pRange->uInitOrReadValue == (idMsr - 0x200) / 2);
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync * Store it.
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo Implement variable MTRR storage. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
b6baf56a3d86bf6846cf312df344bbfe5b2fb01cvboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
ae20b83f0c94402a3e3ac021c3d4e5f827e4905cvboxsync CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync for (uint32_t cShift = 0; cShift < 63; cShift += 8)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync Log(("CPUM: Invalid MTRR default type value: %#llx (%#llx)\n", pRange->szName, uValue, uValue & 0xff));
76c5ade78ff18423f4a3aed5cf7fcc84b1c0933bvboxsync/** @callback_method_impl{FNCPUMRDMSR} */
76c5ade78ff18423f4a3aed5cf7fcc84b1c0933bvboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
5a1e3fdfddd9fb23f043efc077dae781b9691c23vboxsync /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync there are generally 32-bit working bits backing this register. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync#if 0 /** @todo implement machine checks. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync *puValue = pRange->uInitOrReadValue & (RT_BIT_64(8) | 0);
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo implement machine checks. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo implement machine checks. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo implement machine checks. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo implement machine checks. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo implement IA32_DEBUGCTL. */
b97d0f715f8fe39ceb7d4138427da4a0030ff65fvboxsync/** @callback_method_impl{FNCPUMWRMSR} */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsync /** @todo implement IA32_DEBUGCTL. */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
60d6a38322f01d471dec22b5836e7e450d85c3b1vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsync /** @todo implement intel SMM. */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsync /** @todo implement intel SMM. */
7ae61147cce23a4efff53b9cdf35541be62a0cb8vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
7ae61147cce23a4efff53b9cdf35541be62a0cb8vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync /** @todo implement intel SMM. */
7ae61147cce23a4efff53b9cdf35541be62a0cb8vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
7ae61147cce23a4efff53b9cdf35541be62a0cb8vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
7ae61147cce23a4efff53b9cdf35541be62a0cb8vboxsync /** @todo implement intel SMM. */
f4fa1b6b87341bfa5b45bacb7067beec05ca8f96vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
f4fa1b6b87341bfa5b45bacb7067beec05ca8f96vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
f4fa1b6b87341bfa5b45bacb7067beec05ca8f96vboxsync /** @todo implement intel direct cache access (DCA)?? */
f4fa1b6b87341bfa5b45bacb7067beec05ca8f96vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
f4fa1b6b87341bfa5b45bacb7067beec05ca8f96vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
f4fa1b6b87341bfa5b45bacb7067beec05ca8f96vboxsync /** @todo implement intel direct cache access (DCA)?? */
d1a46338dc24f48013833a67f3e30b6d43600924vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1f291c5acd315376ba984563c3165bc0edb53f49vboxsync /** @todo implement intel direct cache access (DCA)?? */
1f291c5acd315376ba984563c3165bc0edb53f49vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
1f291c5acd315376ba984563c3165bc0edb53f49vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1f291c5acd315376ba984563c3165bc0edb53f49vboxsync /** @todo implement intel direct cache access (DCA)?? */
5508f48d486b92a88593b6dcc2252969927faed4vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
5508f48d486b92a88593b6dcc2252969927faed4vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
5508f48d486b92a88593b6dcc2252969927faed4vboxsync /** @todo implement intel direct cache access (DCA)?? */
5508f48d486b92a88593b6dcc2252969927faed4vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
5508f48d486b92a88593b6dcc2252969927faed4vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
5508f48d486b92a88593b6dcc2252969927faed4vboxsync /** @todo implement IA32_PERFEVTSEL0+. */
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync/** @callback_method_impl{FNCPUMWRMSR} */
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync /** @todo implement IA32_PERFEVTSEL0+. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo implement IA32_PERFSTATUS. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo implement IA32_PERFCTL. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo implement IA32_PERFCTL. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo implement performance counters. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo implement performance counters. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
b97d0f715f8fe39ceb7d4138427da4a0030ff65fvboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync /** @todo implement performance counters. */
e2fe5c2c7eeaf4282b1f3d185fc3f379276fae5dvboxsync/** @callback_method_impl{FNCPUMWRMSR} */
e2fe5c2c7eeaf4282b1f3d185fc3f379276fae5dvboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
e2fe5c2c7eeaf4282b1f3d185fc3f379276fae5dvboxsync /** @todo implement performance counters. */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsync /** @todo implement performance counters. */
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync/** @callback_method_impl{FNCPUMWRMSR} */
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync /** @todo implement performance counters. */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync /** @todo implement performance counters. */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
ff62f2ecb95b5892be2edaa7d786d80727d64a2cvboxsync /** @todo implement performance counters. */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsync /** @todo implement performance counters. */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsync /** @todo implement performance counters. */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
1f5edbfd0fc9c890d44edbf915ebc06e75e08943vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
8b36c1115d96725cbbcbdb50bbe0a90993f7d5c1vboxsync /** @todo implement performance counters. */
8b36c1115d96725cbbcbdb50bbe0a90993f7d5c1vboxsync/** @callback_method_impl{FNCPUMWRMSR} */
8b36c1115d96725cbbcbdb50bbe0a90993f7d5c1vboxsyncstatic DECLCALLBACK(int) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
8b36c1115d96725cbbcbdb50bbe0a90993f7d5c1vboxsync /** @todo implement performance counters. */
8b36c1115d96725cbbcbdb50bbe0a90993f7d5c1vboxsync/** @callback_method_impl{FNCPUMRDMSR} */
2d97f8baccdd684bc0a8a15eb86bbe9ff2b85374vboxsyncstatic DECLCALLBACK(int) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
#ifdef LOG_ENABLED
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VERR_CPUM_RAISE_GP_0;
return VERR_CPUM_RAISE_GP_0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
if (uValue != 0)
return VERR_CPUM_RAISE_GP_0;
if (uValue != 0)
return VERR_CPUM_RAISE_GP_0;
if (uValue != 0)
return VERR_CPUM_RAISE_GP_0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VERR_CPUM_RAISE_GP_0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VERR_CPUM_RAISE_GP_0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VERR_CPUM_RAISE_GP_0;
AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VERR_CPUM_RAISE_GP_0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VERR_CPUM_RAISE_GP_0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo100MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo133MHz(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VERR_CPUM_RAISE_GP_0;
Log(("CPUM: WRMDR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
return VERR_CPUM_RAISE_GP_0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VERR_CPUM_RAISE_GP_0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VERR_CPUM_RAISE_GP_0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VERR_CPUM_RAISE_GP_0;
static DECLCALLBACK(int) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uInitOrReadValue / 2 + 0x80000001, 0);
if (pLeaf)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
if (pLeaf)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
if (pLeaf)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
if (pLeaf)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
if (pLeaf)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VERR_CPUM_RAISE_GP_0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VERR_CPUM_RAISE_GP_0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
*puValue = 0;
return VINF_SUCCESS;
static DECLCALLBACK(int) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue)
return VERR_CPUM_RAISE_GP_0;
return VINF_SUCCESS;
# ifndef IN_RING3
while (cLeft-- > 0)
return pCur;
pCur++;
return NULL;
#ifdef VBOX_WITH_NEW_MSR_CODE
*puValue = 0;
int rc;
if (pRange)
return rc;
int rc;
if (pRange)
Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rc=%Rrc\n", idMsr, pRange->szName, uValueAdjusted, uValue, rc));
return rc;
int cpumR3MsrStrictInitChecks(void)
AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
return VINF_SUCCESS;
#ifdef IN_RING0