CPUMAllA.asm revision a41a001e5a4dd3f39faab90b412243ced6d59394
af062818b47340eef15700d2f0211576ba3506eevboxsync; CPUM - Guest Context Assembly Routines.
af062818b47340eef15700d2f0211576ba3506eevboxsync; Copyright (C) 2006-2007 Sun Microsystems, Inc.
af062818b47340eef15700d2f0211576ba3506eevboxsync; This file is part of VirtualBox Open Source Edition (OSE), as
af062818b47340eef15700d2f0211576ba3506eevboxsync; available from http://www.virtualbox.org. This file is free software;
af062818b47340eef15700d2f0211576ba3506eevboxsync; you can redistribute it and/or modify it under the terms of the GNU
af062818b47340eef15700d2f0211576ba3506eevboxsync; General Public License (GPL) as published by the Free Software
af062818b47340eef15700d2f0211576ba3506eevboxsync; Foundation, in version 2 as it comes in the "COPYING" file of the
af062818b47340eef15700d2f0211576ba3506eevboxsync; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
af062818b47340eef15700d2f0211576ba3506eevboxsync; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
af062818b47340eef15700d2f0211576ba3506eevboxsync; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
af062818b47340eef15700d2f0211576ba3506eevboxsync; Clara, CA 95054 USA or visit http://www.sun.com if you need
b955672b950093ff7416d1269dd4d3b69983bd8fvboxsync; additional information or have any questions.
b955672b950093ff7416d1269dd4d3b69983bd8fvboxsync;*******************************************************************************
b955672b950093ff7416d1269dd4d3b69983bd8fvboxsync;* Header Files *
b955672b950093ff7416d1269dd4d3b69983bd8fvboxsync;*******************************************************************************
af062818b47340eef15700d2f0211576ba3506eevboxsync%ifdef IN_RING3
af062818b47340eef15700d2f0211576ba3506eevboxsync %error "The jump table doesn't link on leopard."
af062818b47340eef15700d2f0211576ba3506eevboxsync; Enables write protection of Hypervisor memory pages.
af062818b47340eef15700d2f0211576ba3506eevboxsync; !note! Must be commented out for Trap8 debug handler.
af062818b47340eef15700d2f0211576ba3506eevboxsync%define ENABLE_WRITE_PROTECTION 1
af062818b47340eef15700d2f0211576ba3506eevboxsync; Handles lazy FPU saving and restoring.
af062818b47340eef15700d2f0211576ba3506eevboxsync; This handler will implement lazy fpu (sse/mmx/stuff) saving.
af062818b47340eef15700d2f0211576ba3506eevboxsync; Two actions may be taken in this handler since the Guest OS may
af062818b47340eef15700d2f0211576ba3506eevboxsync; be doing lazy fpu switching. So, we'll have to generate those
af062818b47340eef15700d2f0211576ba3506eevboxsync; traps which the Guest CPU CTX shall have according to the
af062818b47340eef15700d2f0211576ba3506eevboxsync; its CR0 flags. If no traps for the Guest OS, we'll save the host
af062818b47340eef15700d2f0211576ba3506eevboxsync; context and restore the guest context.
af062818b47340eef15700d2f0211576ba3506eevboxsync; @returns 0 if caller should continue execution.
af062818b47340eef15700d2f0211576ba3506eevboxsync; @returns VINF_EM_RAW_GUEST_TRAP if a guest trap should be generated.
af062818b47340eef15700d2f0211576ba3506eevboxsync; @param pCPUMCPU x86:[esp+4] GCC:rdi MSC:rcx CPUMCPU pointer
af062818b47340eef15700d2f0211576ba3506eevboxsyncBEGINPROC cpumHandleLazyFPUAsm
af062818b47340eef15700d2f0211576ba3506eevboxsync ; Figure out what to do.
af062818b47340eef15700d2f0211576ba3506eevboxsync ; There are two basic actions:
af062818b47340eef15700d2f0211576ba3506eevboxsync ; 1. Save host fpu and restore guest fpu.
af062818b47340eef15700d2f0211576ba3506eevboxsync ; 2. Generate guest trap.
af062818b47340eef15700d2f0211576ba3506eevboxsync ; When entering the hypervisor we'll always enable MP (for proper wait
af062818b47340eef15700d2f0211576ba3506eevboxsync ; trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
af062818b47340eef15700d2f0211576ba3506eevboxsync ; is taken from the guest OS in order to get proper SSE handling.
af062818b47340eef15700d2f0211576ba3506eevboxsync ; Actions taken depending on the guest CR0 flags:
af062818b47340eef15700d2f0211576ba3506eevboxsync ; TS | EM | MP | FPUInstr | WAIT :: VMM Action
af062818b47340eef15700d2f0211576ba3506eevboxsync ; ------------------------------------------------------------------------
af062818b47340eef15700d2f0211576ba3506eevboxsync ; 0 | 0 | 0 | Exec | Exec :: Clear TS & MP, Save HC, Load GC.
af062818b47340eef15700d2f0211576ba3506eevboxsync ; 0 | 0 | 1 | Exec | Exec :: Clear TS, Save HC, Load GC.
af062818b47340eef15700d2f0211576ba3506eevboxsync ; 0 | 1 | 0 | #NM | Exec :: Clear TS & MP, Save HC, Load GC;
af062818b47340eef15700d2f0211576ba3506eevboxsync ; 0 | 1 | 1 | #NM | Exec :: Clear TS, Save HC, Load GC.
af062818b47340eef15700d2f0211576ba3506eevboxsync ; 1 | 0 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
af062818b47340eef15700d2f0211576ba3506eevboxsync ; 1 | 0 | 1 | #NM | #NM :: Go to host taking trap there.
af062818b47340eef15700d2f0211576ba3506eevboxsync ; 1 | 1 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
af062818b47340eef15700d2f0211576ba3506eevboxsync ; 1 | 1 | 1 | #NM | #NM :: Go to host taking trap there.
af062818b47340eef15700d2f0211576ba3506eevboxsync ; Before taking any of these actions we're checking if we have already
af062818b47340eef15700d2f0211576ba3506eevboxsync ; loaded the GC FPU. Because if we have, this is an trap for the guest - raw ring-3.
af062818b47340eef15700d2f0211576ba3506eevboxsync%ifdef RT_ARCH_AMD64
af062818b47340eef15700d2f0211576ba3506eevboxsync %ifdef RT_OS_WINDOWS
af062818b47340eef15700d2f0211576ba3506eevboxsync mov xDX, rcx
af062818b47340eef15700d2f0211576ba3506eevboxsync mov xDX, rdi
af062818b47340eef15700d2f0211576ba3506eevboxsync mov xDX, dword [esp + 4]
af062818b47340eef15700d2f0211576ba3506eevboxsync test dword [xDX + CPUMCPU.fUseFlags], CPUM_USED_FPU
af062818b47340eef15700d2f0211576ba3506eevboxsync jz hlfpua_not_loaded
af062818b47340eef15700d2f0211576ba3506eevboxsync jmp hlfpua_to_host
af062818b47340eef15700d2f0211576ba3506eevboxsync ; Take action.
af062818b47340eef15700d2f0211576ba3506eevboxsynchlfpua_not_loaded:
af062818b47340eef15700d2f0211576ba3506eevboxsync mov eax, [xDX + CPUMCPU.Guest.cr0]
af062818b47340eef15700d2f0211576ba3506eevboxsync and eax, X86_CR0_MP | X86_CR0_EM | X86_CR0_TS
af062818b47340eef15700d2f0211576ba3506eevboxsync%ifdef RT_ARCH_AMD64
af062818b47340eef15700d2f0211576ba3506eevboxsync lea r8, [hlfpuajmp1 wrt rip]
af062818b47340eef15700d2f0211576ba3506eevboxsync jmp qword [rax*4 + r8]
af062818b47340eef15700d2f0211576ba3506eevboxsync jmp dword [eax*2 + hlfpuajmp1]
af062818b47340eef15700d2f0211576ba3506eevboxsync;; jump table using fpu related cr0 flags as index.
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF hlfpua_switch_fpu_ctx
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF hlfpua_switch_fpu_ctx
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF hlfpua_switch_fpu_ctx
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF hlfpua_switch_fpu_ctx
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF hlfpua_switch_fpu_ctx
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF hlfpua_to_host
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF hlfpua_switch_fpu_ctx
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF hlfpua_to_host
af062818b47340eef15700d2f0211576ba3506eevboxsync;; and mask for cr0.
af062818b47340eef15700d2f0211576ba3506eevboxsynchlfpu_afFlags:
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF ~(X86_CR0_TS | X86_CR0_MP)
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF ~(X86_CR0_TS)
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF ~(X86_CR0_TS | X86_CR0_MP)
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF ~(X86_CR0_TS)
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF ~(X86_CR0_MP)
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF 0
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF ~(X86_CR0_MP)
af062818b47340eef15700d2f0211576ba3506eevboxsync RTCCPTR_DEF 0
af062818b47340eef15700d2f0211576ba3506eevboxsync ; Action - switch FPU context and change cr0 flags.
af062818b47340eef15700d2f0211576ba3506eevboxsynchlfpua_switch_fpu_ctx:
af062818b47340eef15700d2f0211576ba3506eevboxsync%ifndef IN_RING3 ; IN_RC or IN_RING0
af062818b47340eef15700d2f0211576ba3506eevboxsync mov xCX, cr0
af062818b47340eef15700d2f0211576ba3506eevboxsync %ifdef RT_ARCH_AMD64
af062818b47340eef15700d2f0211576ba3506eevboxsync lea r8, [hlfpu_afFlags wrt rip]
af062818b47340eef15700d2f0211576ba3506eevboxsync and rcx, [rax*4 + r8] ; calc the new cr0 flags.
af062818b47340eef15700d2f0211576ba3506eevboxsync and ecx, [eax*2 + hlfpu_afFlags] ; calc the new cr0 flags.
af062818b47340eef15700d2f0211576ba3506eevboxsync mov xAX, cr0
af062818b47340eef15700d2f0211576ba3506eevboxsync and xAX, ~(X86_CR0_TS | X86_CR0_EM)
af062818b47340eef15700d2f0211576ba3506eevboxsync mov cr0, xAX ; clear flags so we don't trap here.
af062818b47340eef15700d2f0211576ba3506eevboxsync%ifndef RT_ARCH_AMD64
af062818b47340eef15700d2f0211576ba3506eevboxsync mov eax, edx
af062818b47340eef15700d2f0211576ba3506eevboxsync ; Calculate the PCPUM pointer
af062818b47340eef15700d2f0211576ba3506eevboxsync sub eax, [edx + CPUMCPU.ulOffCPUM]
af062818b47340eef15700d2f0211576ba3506eevboxsync test dword [eax + CPUM.CPUFeatures.edx], X86_CPUID_FEATURE_EDX_FXSR
af062818b47340eef15700d2f0211576ba3506eevboxsync jz short hlfpua_no_fxsave
af062818b47340eef15700d2f0211576ba3506eevboxsync fxsave [xDX + CPUMCPU.Host.fpu]
af062818b47340eef15700d2f0211576ba3506eevboxsync or dword [xDX + CPUMCPU.fUseFlags], (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM)
af062818b47340eef15700d2f0211576ba3506eevboxsync fxrstor [xDX + CPUMCPU.Guest.fpu]
af062818b47340eef15700d2f0211576ba3506eevboxsynchlfpua_finished_switch:
af062818b47340eef15700d2f0211576ba3506eevboxsync%ifdef IN_RC
af062818b47340eef15700d2f0211576ba3506eevboxsync mov cr0, xCX ; load the new cr0 flags.
af062818b47340eef15700d2f0211576ba3506eevboxsync ; return continue execution.
af062818b47340eef15700d2f0211576ba3506eevboxsync xor eax, eax
af062818b47340eef15700d2f0211576ba3506eevboxsync%ifndef RT_ARCH_AMD64
af062818b47340eef15700d2f0211576ba3506eevboxsync; legacy support.
af062818b47340eef15700d2f0211576ba3506eevboxsynchlfpua_no_fxsave:
af062818b47340eef15700d2f0211576ba3506eevboxsync fnsave [xDX + CPUMCPU.Host.fpu]
af062818b47340eef15700d2f0211576ba3506eevboxsync or dword [xDX + CPUMCPU.fUseFlags], dword (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM) ; yasm / nasm
af062818b47340eef15700d2f0211576ba3506eevboxsync mov eax, [xDX + CPUMCPU.Guest.fpu] ; control word
af062818b47340eef15700d2f0211576ba3506eevboxsync not eax ; 1 means exception ignored (6 LS bits)
af062818b47340eef15700d2f0211576ba3506eevboxsync and eax, byte 03Fh ; 6 LS bits only
af062818b47340eef15700d2f0211576ba3506eevboxsync test eax, [xDX + CPUMCPU.Guest.fpu + 4]; status word
af062818b47340eef15700d2f0211576ba3506eevboxsync jz short hlfpua_no_exceptions_pending
af062818b47340eef15700d2f0211576ba3506eevboxsync ; technically incorrect, but we certainly don't want any exceptions now!!
af062818b47340eef15700d2f0211576ba3506eevboxsync and dword [xDX + CPUMCPU.Guest.fpu + 4], ~03Fh
af062818b47340eef15700d2f0211576ba3506eevboxsynchlfpua_no_exceptions_pending: