PGMPhys.cpp revision 90466ec66c4fa6a8cd62f01fbf141b51189d33cb
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * PGM - Page Manager and Monitor, Physical Memory Addressing.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * available from http://www.virtualbox.org. This file is free software;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * you can redistribute it and/or modify it under the terms of the GNU
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * General Public License (GPL) as published by the Free Software
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * additional information or have any questions.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync/*******************************************************************************
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync* Header Files *
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync*******************************************************************************/
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync/*******************************************************************************
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync* Defined Constants And Macros *
7d6ce198fd361f58bd1ebdeee7772f76b4e58966vboxsync*******************************************************************************/
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync/** The number of pages to free in one batch. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync/*******************************************************************************
40839c441cb305d84420565f7ca25403d8177413vboxsync* Internal Functions *
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync*******************************************************************************/
7d6ce198fd361f58bd1ebdeee7772f76b4e58966vboxsyncstatic DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
7d6ce198fd361f58bd1ebdeee7772f76b4e58966vboxsyncstatic int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * PGMR3PhysReadU8-64
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * PGMR3PhysWriteU8-64
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * EMT worker for PGMR3PhysReadExternal.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncstatic DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Write to physical memory, external users.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns VBox status code.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @retval VINF_SUCCESS.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pVM VM Handle.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param GCPhys Physical address to write to.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pvBuf What to write.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param cbWrite How many bytes to write.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @thread Any but EMTs.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncVMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Copy loop on ram ranges.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* Find range. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* Inside range or not? */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Must work our way thru this page by page.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * If the page has an ALL access handler, we'll have to
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * delegate the job to EMT.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync int rc = VMR3ReqCall(pVM, VMCPUID_ANY, &pReq, RT_INDEFINITE_WAIT,
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync (PFNRT)pgmR3PhysReadExternalEMT, 4, pVM, &GCPhys, pvBuf, cbRead);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Simple stuff, go ahead.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync const void *pvSrc;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* next page */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync } /* walk pages in ram range. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Unassigned address space.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync } /* Ram range walk */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * EMT worker for PGMR3PhysWriteExternal.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncstatic DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync /** @todo VERR_EM_NO_MEMORY */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Write to physical memory, external users.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns VBox status code.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @retval VINF_SUCCESS.
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync * @retval VERR_EM_NO_MEMORY.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM VM Handle.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param GCPhys Physical address to write to.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pvBuf What to write.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param cbWrite How many bytes to write.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @thread Any but EMTs.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncVMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertMsg(!pVM->pgm.s.fNoMorePhysWrites, ("Calling PGMR3PhysWriteExternal after pgmR3Save()!\n"));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Copy loop on ram ranges, stop when we hit something difficult.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* Find range. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* Inside range or not? */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Must work our way thru this page by page.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * It the page is in any way problematic, we have to
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * do the work on the EMT. Anything that needs to be made
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * writable or involves access handlers is problematic.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync || PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync int rc = VMR3ReqCall(pVM, VMCPUID_ANY, &pReq, RT_INDEFINITE_WAIT,
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync (PFNRT)pgmR3PhysWriteExternalEMT, 4, pVM, &GCPhys, pvBuf, cbWrite);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Simple stuff, go ahead.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* next page */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync } /* walk pages in ram range */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Unassigned address space, skip it.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync } /* Ram range walk */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns see PGMR3PhysGCPhys2CCPtrExternal
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pVM The VM handle.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pGCPhys Pointer to the guest physical address.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param ppv Where to store the mapping address.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pLock Where to store the lock.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncstatic DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * an access handler after it succeeds.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* We *must* flush any corresponding pgm pool page here, otherwise we'll
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * not be informed about writes and keep bogus gst->shw mappings around.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Requests the mapping of a guest page into ring-3, external threads.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * release it.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * This API will assume your intention is to write to the page, and will
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * therefore replace shared and zero pages. If you do not intend to modify the
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns VBox status code.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @retval VINF_SUCCESS on success.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * backing or if the page has any active access handlers. The caller
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * must fall back on using PGMR3PhysWriteExternal.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pVM The VM handle.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param GCPhys The guest physical address of the page that should be mapped.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param ppv Where to store the address corresponding to GCPhys.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @remark Avoid calling this API from within critical sections (other than the
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * PGM one) because of the deadlock risk when we have to delegating the
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * task to an EMT.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @thread Any.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncVMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Query the Physical TLB entry for the page (may fail).
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * If the page is shared, the zero page, or being write monitored
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * it must be converted to an page that's writable if possible.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * This has to be done on an EMT.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync || RT_UNLIKELY(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED))
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = VMR3ReqCall(pVM, VMCPUID_ANY, &pReq, RT_INDEFINITE_WAIT,
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4, pVM, &GCPhys, ppv, pLock);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Now, just perform the locking and calculate the return address.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync#if 0 /** @todo implement locking properly */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync if (RT_LIKELY(pPage->cLocks != PGM_PAGE_MAX_LOCKS))
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync if (RT_UNLIKELY(++pPage->cLocks == PGM_PAGE_MAX_LOCKS))
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertMsgFailed(("%RGp is entering permanent locked state!\n", GCPhys));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pMap->cRefs++; /* Extra ref to prevent it from going away. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Requests the mapping of a guest page into ring-3, external threads.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * release it.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns VBox status code.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @retval VINF_SUCCESS on success.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * backing or if the page as an active ALL access handler. The caller
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * must fall back on using PGMPhysRead.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pVM The VM handle.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * @param GCPhys The guest physical address of the page that should be mapped.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * @param ppv Where to store the address corresponding to GCPhys.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @remark Avoid calling this API from within critical sections (other than
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * the PGM one) because of the deadlock risk.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @thread Any.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncVMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync * Query the Physical TLB entry for the page (may fail).
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* MMIO pages doesn't have any readable backing. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Now, just perform the locking and calculate the return address.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync#if 0 /** @todo implement locking properly */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync if (RT_LIKELY(pPage->cLocks != PGM_PAGE_MAX_LOCKS))
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync if (RT_UNLIKELY(++pPage->cLocks == PGM_PAGE_MAX_LOCKS))
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertMsgFailed(("%RGp is entering permanent locked state!\n", GCPhys));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pMap->cRefs++; /* Extra ref to prevent it from going away. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Called when anything was relocated.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pVM Pointer to the shared VM structure.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync || strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Links a new RAM range into the list.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM Pointer to the shared VM structure.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pNew Pointer to the new list entry.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncstatic void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Unlink an existing RAM range from the list.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM Pointer to the shared VM structure.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pRam Pointer to the new list entry.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncstatic void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Unlink an existing RAM range from the list.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM Pointer to the shared VM structure.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pRam Pointer to the new list entry.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncstatic void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* find prev. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Frees a range of pages, replacing them with ZERO pages of the specified type.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns VBox status code.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM The VM handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pRam The RAM range in which the pages resides.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param GCPhys The address of the first page.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param GCPhysLast The address of the last page.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param uType The page type to replace then with.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncstatic int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* Itegerate the pages. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync while (cPagesLeft-- > 0)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * PGMR3PhysRegisterRam worker that initializes and links a RAM range.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM The VM handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pNew The new RAM range.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param GCPhys The address of the RAM range.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param GCPhysLast The last address of the RAM range.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * if in HMA.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param R0PtrNew Ditto for R0.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pszDesc The description.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pPrev The previous RAM range (for linking).
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncstatic void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Initialize the range.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync while (iPage-- > 0)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* Update the page count stats. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Relocate a floating RAM range.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @copydoc FNPGMRELOCATE.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncstatic DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync return true;
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync /* Update myself and then relink all the ranges. */
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync return true;
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * PGMR3PhysRegisterRam worker that registers a high chunk.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @returns VBox status code.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param pVM The VM handle.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param GCPhys The address of the RAM.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param cRamPages The number of RAM pages to register.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param cbChunk The size of the PGMRAMRANGE guest mapping.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param iChunk The chunk number.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param pszDesc The RAM range description.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param ppPrev Previous RAM range pointer. In/Out.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsyncstatic int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync : MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * Allocate memory for the new chunk.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync int rc = SUPR3PageAllocEx(cChunkPages, 0 /*fFlags*/, &pvChunk,
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * Create a mapping and map the pages into it.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * We push these in below the HMA.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /*fFlags*/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * Ok, init and link the range.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync (RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * Sets up a range RAM.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * This will check for conflicting registrations, make a resource
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * reservation for the memory (with GMM), and setup the per-page
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * tracking structures (PGMPAGE).
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @returns VBox stutus code.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param pVM Pointer to the shared VM structure.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param GCPhys The physical address of the RAM.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param cb The size of the RAM.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param pszDesc The description - not copied, so, don't free or change it.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsyncVMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * Validate input.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Find range location and check for conflicts.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * (We don't lock here because the locking by EMT is only required on update.)
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Register it with GMM (the API bitches).
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * The PGMRAMRANGE structures for the high memory can get very big.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * In order to avoid SUPR3PageAllocEx allocation failures due to the
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * allocation size limit there and also to avoid being unable to find
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * guest mapping space for them, we split this memory up into 4MB in
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * The first and last page of each mapping are guard pages and marked
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * not-present. So, we've got 4186112 and 16769024 bytes available for
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * the PGMRAMRANGE structure.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * Note! The sizes used here will influence the saved state.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U*_1M - PAGE_SIZE * 2);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U*_1M - PAGE_SIZE * 2);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync /* advance */
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * Allocate, initialize and link the new RAM range.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * Notify REM.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * We do this late in the init process so that all the ROM and MMIO ranges have
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * been registered already and we don't go wasting memory on them.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * @returns VBox status code.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * @param pVM Pointer to the shared VM structure.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * Walk the RAM ranges and allocate all RAM pages, halt at
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * the first allocation error.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync while (cLeft-- > 0)
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync /* nothing to do here. */
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * Resets (zeros) the RAM.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * ASSUMES that the caller owns the PGM lock.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * @returns VBox status code.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * @param pVM Pointer to the shared VM structure.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * We batch up pages before freeing them.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync * Walk the ram ranges.
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync /* Replace all RAM pages by ZERO pages. */
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync while (iPage-- > 0)
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
4f2b002896072b0b5a7cb566341c8bac5e69392bvboxsync } /* for each page */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* Zero the memory. */
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync while (iPage-- > 0)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pMapIgnored, &pvPage);
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync } /* for each page */
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * Finish off any pages pending freeing.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * This is the interface IOM is using to register an MMIO region.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * It will check for conflicts and ensure that a RAM range structure
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * is present before calling the PGMR3HandlerPhysicalRegister API to
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * register the callbacks.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * @returns VBox status code.
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync * @param pVM Pointer to the shared VM structure.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * @param GCPhys The start of the MMIO region.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * @param cb The size of the MMIO region.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * @param pvUserR3 The user argument for R3.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pvUserR0 The user argument for R0.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pvUserRC The user argument for RC.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pszDesc The description of the MMIO region.
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsyncVMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync * Assert on some assumption.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Make sure there's a RAM range structure for the region.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync bool fRamExists = false;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync /* Simplification: all within the same range. */
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync ("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync /* Check that it's all RAM or MMIO pages. */
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync while (cLeft-- > 0)
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync ("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* Looks good. */
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Make all the pages in the range MMIO/ZERO pages, freeing any
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * RAM pages currently mapped here. This might not be 100% correct
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * for PCI memory, but we're doing the same thing for MMIO2 pages.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * No RAM range, insert an ad-hoc one.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Note that we don't have to tell REM about this range because
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * PGMHandlerPhysicalRegisterEx will do that for us.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync Log(("PGMR3PhysMMIORegister: Adding ad-hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* Initialize the range. */
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync pNew->fFlags = 0; /** @todo add some kind of ad-hoc flag? */
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync while (iPage-- > 0)
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync PGM_PAGE_INIT_ZERO_REAL(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsync /* update the page count stats. */
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync /* link it */
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Register the access handler.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync /* remove the ad-hoc range. */
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
9b62e122a37f42c2bbaae1312ad198f44bebea5cvboxsync * This is the interface IOM is using to register an MMIO region.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * It will take care of calling PGMHandlerPhysicalDeregister and clean up
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * any ad-hoc PGMRAMRANGE left behind.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @returns VBox status code.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pVM Pointer to the shared VM structure.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param GCPhys The start of the MMIO region.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param cb The size of the MMIO region.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsyncVMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * First deregister the handler, then check if we should remove the ram range.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsync /** @todo We're being a bit too careful here. rewrite. */
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsync * See if all the pages are dead MMIO pages.
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsync bool fAllMMIO = true;
cd2274c977e1b722b535e4f601a324e8029b5e43vboxsync while (cLeft-- > 0)
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync /*|| not-out-of-action later */)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
db87bb1112c1f2827ffa192593174cf845f8f04dvboxsync AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
680c2aff33be2ee9340c8763a3cb5c218c352bcfvboxsync * Ad-hoc range, unlink and free it.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync Log(("PGMR3PhysMMIODeregister: Freeing ad-hoc MMIO range for %RGp-%RGp %s\n",
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Range match? It will all be within one range (see PGMAllHandler.cpp).
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Turn the pages back into RAM pages.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Locate a MMIO2 range.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @returns Pointer to the MMIO2 range.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pVM Pointer to the shared VM structure.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pDevIns The device instance owning the region.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param iRegion The region.
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsyncDECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Search the list.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Allocate and register an MMIO2 region.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * RAM associated with a device. It is also non-shared memory with a
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * permanent ring-3 mapping and page backing (presently).
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * A MMIO2 range may overlap with base memory if a lot of RAM
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * is configured for the VM, in which case we'll drop the base
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * memory pages. Presently we will make no attempt to preserve
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * anything that happens to be present in the base memory that
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * is replaced, this is of course incorrectly but it's too much
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @returns VBox status code.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @retval VERR_ALREADY_EXISTS if the region already exists.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pVM Pointer to the shared VM structure.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param pDevIns The device instance owning the region.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * this number has to be the number of that region. Otherwise
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * it can be any number safe UINT8_MAX.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param cb The size of the region. Must be page aligned.
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * @param fFlags Reserved for future use, must be zero.
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * @param ppv Where to store the pointer to the ring-3 mapping of the memory.
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync * @param pszDesc The description.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncVMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc)
48e06e6a052c50ecf176f63f5537f80b544bf34avboxsync * Validate input.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * For the 2nd+ instance, mangle the description string so it's unique.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Try reserve and allocate the backing memory first as this is what is
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * most likely to fail.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync rc = SUPR3PageAllocEx(cPages, 0 /*fFlags*/, &pvPages, NULL /*pR0Ptr*/, paPages);
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync * Create the MMIO2 range record for it.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
680c2aff33be2ee9340c8763a3cb5c218c352bcfvboxsync //pNew->pNext = NULL;
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync //pNew->fMapped = false;
680c2aff33be2ee9340c8763a3cb5c218c352bcfvboxsync //pNew->fOverlapping = false;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
90624af27b0e648b68167bd3b332d0e3b1d18ab1vboxsync //pNew->RamRange.fFlags = 0; /// @todo MMIO2 flag?
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync while (iPage-- > 0)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync paPages[iPage].Phys & X86_PTE_PAE_PG_MASK, NIL_GMM_PAGEID,
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* update page count stats */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Link it into the list.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Since there is no particular order, just push it.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Deregisters and frees an MMIO2 region.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Any physical (and virtual) access handlers registered for the region must
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * be deregistered before calling this function.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns VBox status code.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM Pointer to the shared VM structure.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pDevIns The device instance owning the region.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncVMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Validate input.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertReturn(iRegion <= UINT8_MAX || iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync unsigned cFound = 0;
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * Unmap it if it's mapped.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * Unlink it
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * Free the memory.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync /* we're leaking hyper memory here if done at runtime. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /*rc = MMHyperFree(pVM, pCur);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertRCReturn(rc, rc); - not safe, see the alloc call. */
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync /* update page count stats */
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * Maps a MMIO2 region.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * This is done when a guest / the bios / state loading changes the
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * PCI config. The replacing of base memory has the same restrictions
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * as during registration, of course.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @returns VBox status code.
817577d2c4d6dee709de7a92d3bb7d0aeedae9aevboxsync * @param pVM Pointer to the shared VM structure.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pDevIns The
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncVMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Validate input
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Find our location in the ram range list, checking for
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * restriction we don't bother implementing yet (partially overlapping).
93e05ea894cefd56ca308d72372b4dd8045bd1eevboxsync bool fRamExists = false;
eb259de2a9eac4b4dda56e89f5004671f926bd9bvboxsync /* completely within? */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync ("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
680c2aff33be2ee9340c8763a3cb5c218c352bcfvboxsync uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
680c2aff33be2ee9340c8763a3cb5c218c352bcfvboxsync while (cPagesLeft-- > 0)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync ("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
90624af27b0e648b68167bd3b332d0e3b1d18ab1vboxsync Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Make the changes.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync/** @todo use pgmR3PhysFreePageRange here. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* replace the pages, freeing all present RAM pages. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync while (cPagesLeft-- > 0)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* link in the ram range */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Unmaps a MMIO2 region.
fd658895339cb48b2ba581b1a1141aea39009ff7vboxsync * This is done when a guest / the bios / state loading changes the
fd658895339cb48b2ba581b1a1141aea39009ff7vboxsync * PCI config. The replacing of base memory has the same restrictions
fd658895339cb48b2ba581b1a1141aea39009ff7vboxsync * as during registration, of course.
fd658895339cb48b2ba581b1a1141aea39009ff7vboxsyncVMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync bool fInformREM = false;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Validate input
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Unmap it.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* Restore the RAM pages we've replaced. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync while (cPagesLeft-- > 0)
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * Checks if the given address is an MMIO2 base address or not.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @returns true/false accordingly.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param pVM Pointer to the shared VM structure.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param pDevIns The owner of the memory, optional.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param GCPhys The address to check.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsyncVMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * Validate input
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * Search the list.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync return true;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync return false;
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * Gets the HC physical address of a page in the MMIO2 region.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * This is API is intended for MMHyper and shouldn't be called
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * by anyone else...
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @returns VBox status code.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param pVM Pointer to the shared VM structure.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param pDevIns The owner of the memory, optional.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param iRegion The region.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param off The page expressed an offset into the MMIO2 region.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param pHCPhys Where to store the result.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsyncVMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * Validate input
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * Maps a portion of an MMIO2 region into kernel space (host).
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * The kernel mapping will become invalid when the MMIO2 memory is deregistered
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * or the VM is terminated.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @return VBox status code.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param pVM Pointer to the shared VM structure.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param pDevIns The device owning the MMIO2 memory.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param iRegion The region.
0d73750f953d8569054777eab62f40ad88a66d88vboxsync * @param off The offset into the region. Must be page aligned.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param cb The number of bytes to map. Must be page aligned.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param pszDesc Mapping description.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * @param pR0Ptr Where to store the R0 address.
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsyncVMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2fce40121ae472df2fd959fbe19775ed43304a0bvboxsync * Validate input.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Pass the request on to the support library/driver.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * Registers a ROM image.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Shadowed ROM images requires double the amount of backing memory, so,
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * don't use that unless you have to. Shadowing of ROM images is process
7d6ce198fd361f58bd1ebdeee7772f76b4e58966vboxsync * where we can select where the reads go and where the writes go. On real
7d6ce198fd361f58bd1ebdeee7772f76b4e58966vboxsync * hardware the chipset provides means to configure this. We provide
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * PGMR3PhysProtectROM() for this purpose.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * A read-only copy of the ROM image will always be kept around while we
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * will allocate RAM pages for the changes on demand (unless all memory
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * is configured to be preallocated).
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns VBox status.
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * @param pVM VM Handle.
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * @param pDevIns The device instance owning the ROM.
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * @param GCPhys First physical address in the range.
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * Must be page aligned!
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * @param cbRange The size of the range (in bytes).
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * Must be page aligned!
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * @param pvBinary Pointer to the binary data backing the ROM image.
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * This must be exactly \a cbRange in size.
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * @param pszDesc Pointer to description string. This must not be freed.
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * @remark There is no way to remove the rom, automatically on device cleanup or
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * manually from the device yet. This isn't difficult in any way, it's
751a35d04fb11f94562583ad77bc0a1382957f49vboxsync * just not something we expect to be necessary for a while.
751a35d04fb11f94562583ad77bc0a1382957f49vboxsyncVMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync const void *pvBinary, uint32_t fFlags, const char *pszDesc)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Validate input.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED | PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Find the ROM location in the ROM list first.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Find the RAM location and check for conflicts.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Conflict detection is a bit different than for RAM
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * registration since a ROM can be located within a RAM
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * range. So, what we have to check for is other memory
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * types (other than RAM that is) and that we don't span
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * more than one RAM range (layz).
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync bool fRamExists = false;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* completely within? */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync ("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync while (cPagesLeft-- > 0)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync ("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Update the base memory reservation if necessary.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Allocate memory for the virgin copy of the RAM.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Allocate the new ROM range and RAM range (if necessary).
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
1042ff61f0b8de217c7e694021be0b9a5b9b8468vboxsync rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Initialize and insert the RAM range (if required).
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * !HACK ALERT! REM + (Shadowed) ROM ==> mess.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * If it's shadowed we'll register the handler after the ROM notification
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * so we get the access handler callbacks that we should. If it isn't
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * shadowed we'll do it the other way around to make REM use the built-in
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * ROM behavior and not the handler behavior (which is to route all access
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * to PGM atm).
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Copy the image over to the virgin pages.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * This must be done after linking in the RAM range.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pMapIgnored, &pvDstPage);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Initialize the ROM range.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Note that the Virgin member of the pages has already been initialized above.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync PGM_PAGE_INIT_ZERO_REAL(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* update the page count stats */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Insert the ROM range, tell REM and return successfully.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* bail out */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /** @todo Purge the mapping cache or something... */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * \#PF Handler callback for ROM write accesses.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns VINF_SUCCESS if the handler have carried out the operation.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM VM Handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param GCPhys The physical address the guest is writing to.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pvPhys The HC mapping of that address.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pvBuf What the guest is reading/writing.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param cbBuf How much it's reading/writing.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param enmAccessType The access type.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pvUser User argument.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsyncstatic DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Take the default action.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Ignore writes.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Write to the ram page.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's *way* simpler that way. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* This should be impossible now, pvPhys doesn't work cross page anylonger. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Take the lock, do lazy allocation, map the page and copy the data.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Note that we have to bypass the mapping TLB since it works on
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * guest physical addresses and entering the shadow page would
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * kind of screw things up...
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pShadowPage) != PGM_PAGE_STATE_ALLOCATED))
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = pgmPhysPageMakeWritable(pVM, pShadowPage, GCPhys);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* returned */, ("%Rrc\n", rc));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync int rc2 = pgmPhysPageMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pMapIgnored, &pvDstPage);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Called by PGMR3Reset to reset the shadow, switch to the virgin,
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * and verify that the virgin part is untouched.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * This is done after the normal memory has been cleared.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * ASSUMES that the caller owns the PGM lock.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * @param pVM The VM handle.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Reset the physical handler.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * What we do with the shadow pages depends on the memory
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * preallocation option. If not enabled, we'll just throw
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * out all the dirty pages and replace them by the zero page.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* Free the dirty pages. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow, pRom->GCPhys + (iPage << PAGE_SHIFT));
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync /* clear all the shadow pages. */
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = pgmPhysPageMakeWritable(pVM, &pRom->aPages[iPage].Shadow, GCPhys);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pMapIgnored, &pvDstPage);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync * Verify that the virgin page is unchanged if possible.
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync uint8_t const *pbSrcPage = (uint8_t const *)pRom->pvOriginal;
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
a60be2c64ea23bb7ce4c9998bcd541c4db879fbavboxsync int rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pMapIgnored, &pvDstPage);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Change the shadowing of a range of ROM pages.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * This is intended for implementing chipset specific memory registers
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * and will not be very strict about the input. It will silently ignore
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * any pages that are not the part of a shadowed ROM.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns VBox status code.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @retval VINF_PGM_SYNC_CR3
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pVM Pointer to the shared VM structure.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param GCPhys Where to start. Page aligned.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param cb How much to change. Page aligned.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param enmProt The new ROM protection.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncVMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Check input
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Process the request.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync bool fFlushTLB = false;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Iterate the relevant pages and make necessary the changes.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync bool fChanges = false;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* flush references to the page. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRamPage, &fFlushTLB);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS || RT_FAILURE(rc2)))
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Reset the access handler if we made changes, no need
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * to optimize this.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync int rc = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* Advance - cb isn't updated. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Sets the Address Gate 20 state.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pVCpu The VCPU to operate on.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param fEnable True if the gate should be enabled.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * False if the gate should be disabled.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncVMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Tree enumeration callback for dealing with age rollover.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * It will perform a simple compression of the current age.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncstatic DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* Age compression - ASSUMES iNow == 4. */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync else /* iAge = 0 */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* reinsert */
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Tree enumeration callback that updates the chunks that have
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * been used since the last
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncstatic DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Performs ageing of the ring-3 chunk mappings.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pVM The VM handle.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingCallback, pVM);
3c520cf6887d9039d9aa7cf3bbe81fd7de1ffd4cvboxsync * The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Callback used to find the mapping that's been unused for
edde275acba04aca58db4172a163741e3abadfbcvboxsync * the longest time.
edde275acba04aca58db4172a163741e3abadfbcvboxsyncstatic DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Check that it's not in any of the TLBs.
3c520cf6887d9039d9aa7cf3bbe81fd7de1ffd4cvboxsync for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync /* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
3c520cf6887d9039d9aa7cf3bbe81fd7de1ffd4cvboxsync * Finds a good candidate for unmapping when the ring-3 mapping cache is full.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * The candidate will not be part of any TLBs, so no need to flush
3c520cf6887d9039d9aa7cf3bbe81fd7de1ffd4cvboxsync * anything afterwards.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns Chunk id.
3c520cf6887d9039d9aa7cf3bbe81fd7de1ffd4cvboxsync * @param pVM The VM handle.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsyncstatic int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
edde275acba04aca58db4172a163741e3abadfbcvboxsync * Do tree ageing first?
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Enumerate the age tree starting with the left most node.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /*fFromLeft*/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Maps the given chunk into the ring-3 mapping cache.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * This will call ring-0.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @returns VBox status code.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param pVM The VM handle.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param idChunk The chunk in question.
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * @param ppChunk Where to store the chunk tracking structure.
edde275acba04aca58db4172a163741e3abadfbcvboxsync * @remarks Called from within the PGM critical section.
edde275acba04aca58db4172a163741e3abadfbcvboxsyncint pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
13493ab7596e827b8d0caab2c89e635dd65f78f9vboxsync * Allocate a new tracking structure first.
dca3cdd56f38abf4257b94ff13268323ea52e0a7vboxsync PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
dca3cdd56f38abf4257b94ff13268323ea52e0a7vboxsync PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
dca3cdd56f38abf4257b94ff13268323ea52e0a7vboxsync * Request the ring-0 part to map the chunk in question and if
dca3cdd56f38abf4257b94ff13268323ea52e0a7vboxsync * necessary unmap another one to make space in the mapping cache.
dca3cdd56f38abf4257b94ff13268323ea52e0a7vboxsync if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
dca3cdd56f38abf4257b94ff13268323ea52e0a7vboxsync Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync/** @todo This is wrong. Any thread in the VM process should be able to do this,
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * there are depenenecies on this. What currently saves the day is that
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * we don't unmap anything and that all non-zero memory will therefore
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * be present when non-EMTs tries to access it. */
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * Update the tree.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync /* insert the new one. */
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync /* remove the unmapped one. */
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * @returns see pgmR3PhysChunkMap.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * @param pVM The VM handle.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * @param idChunk The chunk to map.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsyncVMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * Invalidates the TLB for the ring-3 mapping cache.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * @param pVM The VM handle.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsyncVMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * signal and clear the out of memory condition. When contracted, this API is
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * used to try clear the condition when the user wants to resume.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * @returns The following VBox status codes.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * @retval VINF_SUCCESS on success. FFs cleared.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * @param pVM The VM handle.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * Allocate more pages, noting down the index of the first new page.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * Clear the pages.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * We should never get here unless there is a genuine shortage of
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * memory (or some internal error). Flag the error so the VM can be
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * suspended ASAP and the user informed. If we're totally out of
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * handy pages we will return failure.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync /* Report the failure. */
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync " cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
edde275acba04aca58db4172a163741e3abadfbcvboxsync for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
edde275acba04aca58db4172a163741e3abadfbcvboxsync LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
edde275acba04aca58db4172a163741e3abadfbcvboxsync i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
edde275acba04aca58db4172a163741e3abadfbcvboxsync uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
edde275acba04aca58db4172a163741e3abadfbcvboxsync if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
edde275acba04aca58db4172a163741e3abadfbcvboxsync pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
f3b077ba3204fcb9c310e3929340db83bc9b77cdvboxsync /* Set the FFs and adjust rc. */
edde275acba04aca58db4172a163741e3abadfbcvboxsync * Frees the specified RAM page and replaces it with the ZERO page.
edde275acba04aca58db4172a163741e3abadfbcvboxsync * This is used by ballooning, remapping MMIO2 and RAM reset.
edde275acba04aca58db4172a163741e3abadfbcvboxsync * @param pVM Pointer to the shared VM structure.
edde275acba04aca58db4172a163741e3abadfbcvboxsync * @param pReq Pointer to the request.
edde275acba04aca58db4172a163741e3abadfbcvboxsync * @param pPage Pointer to the page structure.
edde275acba04aca58db4172a163741e3abadfbcvboxsync * @param GCPhys The guest physical address of the page, if applicable.
edde275acba04aca58db4172a163741e3abadfbcvboxsync * @remarks The caller must own the PGM lock.
edde275acba04aca58db4172a163741e3abadfbcvboxsyncstatic int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
edde275acba04aca58db4172a163741e3abadfbcvboxsync * Assert sanity.
edde275acba04aca58db4172a163741e3abadfbcvboxsync if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
edde275acba04aca58db4172a163741e3abadfbcvboxsync && PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
edde275acba04aca58db4172a163741e3abadfbcvboxsync AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
edde275acba04aca58db4172a163741e3abadfbcvboxsync return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
04f85536aa01b3e25cece11d2a094e2a362bcbfavboxsync if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO)
04f85536aa01b3e25cece11d2a094e2a362bcbfavboxsync const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
04f85536aa01b3e25cece11d2a094e2a362bcbfavboxsync Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
04f85536aa01b3e25cece11d2a094e2a362bcbfavboxsync || PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
04f85536aa01b3e25cece11d2a094e2a362bcbfavboxsync AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
04f85536aa01b3e25cece11d2a094e2a362bcbfavboxsync return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
04f85536aa01b3e25cece11d2a094e2a362bcbfavboxsync /* update page count stats. */
04f85536aa01b3e25cece11d2a094e2a362bcbfavboxsync * pPage = ZERO page.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync * Make sure it's not in the handy page array.
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync * Push it onto the page array.
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync * Flush the pages.
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync * Converts a GC physical address to a HC ring-3 pointer, with some
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync * additional checks.
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync * @returns VBox status code.
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync * @retval VINF_SUCCESS on success.
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync * @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync * access handler of some kind.
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync * @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync * accesses or is odd in any way.
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync * @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync * @param pVM The VM handle.
eca3ddadc12f677ac68395c5eab914d41fc8963avboxsync * @param GCPhys The GC physical address to convert.
edde275acba04aca58db4172a163741e3abadfbcvboxsync * @param fWritable Whether write access is required.
edde275acba04aca58db4172a163741e3abadfbcvboxsync * @param ppv Where to store the pointer corresponding to GCPhys on
edde275acba04aca58db4172a163741e3abadfbcvboxsyncVMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
edde275acba04aca58db4172a163741e3abadfbcvboxsync int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
1042ff61f0b8de217c7e694021be0b9a5b9b8468vboxsync if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
1042ff61f0b8de217c7e694021be0b9a5b9b8468vboxsync /** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
1042ff61f0b8de217c7e694021be0b9a5b9b8468vboxsync * in -norawr0 mode. */
1042ff61f0b8de217c7e694021be0b9a5b9b8468vboxsync /* Temporarily disabled physical handler(s), since the recompiler
1042ff61f0b8de217c7e694021be0b9a5b9b8468vboxsync doesn't get notified when it's reset we'll have to pretend it's
1042ff61f0b8de217c7e694021be0b9a5b9b8468vboxsync operating normally. */
edde275acba04aca58db4172a163741e3abadfbcvboxsync /* Make sure what we return is writable. */
8302394f164acb4adb187954f6ac8ef7a9efa629vboxsync if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
04f85536aa01b3e25cece11d2a094e2a362bcbfavboxsync rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
9564efb26e4be678018e90c7f18dfb06c8b23009vboxsync /* Get a ring-3 mapping of the address. */
9564efb26e4be678018e90c7f18dfb06c8b23009vboxsync rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
9564efb26e4be678018e90c7f18dfb06c8b23009vboxsync *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
9564efb26e4be678018e90c7f18dfb06c8b23009vboxsync /** @todo mapping/locking hell; this isn't horribly efficient since
9564efb26e4be678018e90c7f18dfb06c8b23009vboxsync * pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
9564efb26e4be678018e90c7f18dfb06c8b23009vboxsync Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] *ppv=%p\n", GCPhys, rc, pPage, *ppv));
9564efb26e4be678018e90c7f18dfb06c8b23009vboxsync Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
9564efb26e4be678018e90c7f18dfb06c8b23009vboxsync /* else: handler catching all access, no pointer returned. */