PGM.cpp revision 72a925d2c24794318caf689fdee5a90dfae6a4b6
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
8502773207230763deba3e622495f2099398dcb0vboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * available from http://www.virtualbox.org. This file is free software;
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * you can redistribute it and/or modify it under the terms of the GNU
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * General Public License (GPL) as published by the Free Software
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * additional information or have any questions.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync/** @page pg_pgm PGM - The Page Manager and Monitor
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * @see grp_pgm,
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * @ref pg_pgm_pool,
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * @ref pg_pgm_phys.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * @section sec_pgm_modes Paging Modes
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * There are three memory contexts: Host Context (HC), Guest Context (GC)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * and intermediate context. When talking about paging HC can also be refered to
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * as "host paging", and GC refered to as "shadow paging".
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * is defined by the host operating system. The mode used in the shadow paging mode
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * depends on the host paging mode and what the mode the guest is currently in. The
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * following relation between the two is defined:
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * @verbatim
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync Host > 32-bit | PAE | AMD64 |
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync Guest | | | |
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync ==v================================
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync 32-bit 32-bit PAE PAE
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync -------|--------|--------|--------|
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync PAE PAE PAE PAE
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync -------|--------|--------|--------|
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync AMD64 AMD64 AMD64 AMD64
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync -------|--------|--------|--------| @endverbatim
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * All configuration except those in the diagonal (upper left) are expected to
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * require special effort from the switcher (i.e. a bit slower).
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @section sec_pgm_shw The Shadow Memory Context
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Because of guest context mappings requires PDPT and PML4 entries to allow
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * writing on AMD64, the two upper levels will have fixed flags whatever the
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * guest is thinking of using there. So, when shadowing the PD level we will
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * calculate the effective flags of PD and all the higher levels. In legacy
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * PAE mode this only applies to the PWT and PCD bits (the rest are
8502773207230763deba3e622495f2099398dcb0vboxsync * ignored/reserved/MBZ). We will ignore those bits for the present.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * @section sec_pgm_int The Intermediate Memory Context
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * The world switch goes thru an intermediate memory context which purpose it is
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * to provide different mappings of the switcher code. All guest mappings are also
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * present in this context.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * The switcher code is mapped at the same location as on the host, at an
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * identity mapped location (physical equals virtual address), and at the
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * hypervisor location. The identity mapped location is for when the world
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * switches that involves disabling paging.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * simplifies switching guest CPU mode and consistency at the cost of more
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * code to do the work. All memory use for those page tables is located below
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * 4GB (this includes page tables for guest context mappings).
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @subsection subsec_pgm_int_gc Guest Context Mappings
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * During assignment and relocation of a guest context mapping the intermediate
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * memory context is used to verify the new location.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Guest context mappings are currently restricted to below 4GB, for reasons
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * of simplicity. This may change when we implement AMD64 support.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * @section sec_pgm_misc Misc
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
cf9045d402be1e8b7344a439eaefe2ca4c2b53d3vboxsync * The differences between legacy PAE and long mode PAE are:
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * usual meanings while 6 is ignored (AMD). This means that upon switching to
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * legacy PAE mode we'll have to clear these bits and when going to long mode
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * they must be set. This applies to both intermediate and shadow contexts,
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * however we don't need to do it for the intermediate one since we're
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * executing with CR0.WP at that time.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * a page aligned one is required.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * @section sec_pgm_handlers Access Handlers
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Placeholder.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * @subsection sec_pgm_handlers_virt Virtual Access Handlers
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Placeholder.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @subsection sec_pgm_handlers_virt Virtual Access Handlers
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * We currently implement three types of virtual access handlers: ALL, WRITE
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * rest of this section is going to be about these handlers.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * We'll go thru the life cycle of a handler and try make sense of it all, don't know
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * how successfull this is gonna be...
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * and create a new node that is inserted into the AVL tree (range key). Then
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * via the current guest CR3 and update the physical page -> virtual handler
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * translation. Needless to say, this doesn't exactly scale very well. If any changes
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * are detected, it will flag a virtual bit update just like we did on registration.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * PGMPHYS pages with changes will have their virtual handler state reset to NONE.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * 2b. The virtual bit update process will iterate all the pages covered by all the
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * virtual handlers and update the PGMPAGE virtual handler state to the max of all
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * virtual handlers on that page.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * we don't miss any alias mappings of the monitored pages.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * 2d. SyncCR3 will then proceed with syncing the CR3 table.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * 3. \#PF(np,read) on a page in the range. This will cause it to be synced
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * read-only and resumed if it's a WRITE handler. If it's an ALL handler we
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * will call the handlers like in the next step. If the physical mapping has
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * changed we will - some time in the future - perform a handler callback
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * (optional) and update the physical -> virtual handler cache.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * 4. \#PF(,write) on a page in the range. This will cause the handler to
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * be invoked.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * 5. The guest invalidates the page and changes the physical backing or
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * unmaps it. This should cause the invalidation callback to be invoked
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * (it might not yet be 100% perfect). Exactly what happens next... is
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * this where we mess up and end up out of sync for a while?
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * We will then set all PGMPAGEs in the physical -> virtual handler cache for
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * this handler to NONE and trigger a full PGM resync (basically the same
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * as int step 1). Which means 2 is executed again.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * @subsubsection sub_sec_pgm_handler_virt_todo TODOs
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * There is a bunch of things that needs to be done to make the virtual handlers
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * work 100% correctly and work more efficiently.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * The first bit hasn't been implemented yet because it's going to slow the
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * whole mess down even more, and besides it seems to be working reliably for
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * our current uses. OTOH, some of the optimizations might end up more or less
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * implementing the missing bits, so we'll see.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * On the optimization side, the first thing to do is to try avoid unnecessary
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * cache flushing. Then try team up with the shadowing code to track changes
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * in mappings by means of access to them (shadow in), updates to shadows pages,
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * invlpg, and shadow PT discarding (perhaps).
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Some idea that have popped up for optimization for current and new features:
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - bitmap indicating where there are virtual handlers installed.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * (4KB => 2**20 pages, page 2**12 => covers 32-bit address space 1:1!)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - Further optimize this by min/max (needs min/max avl getters).
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - Shadow page table entry bit (if any left)?
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync/** @page pg_pgm_phys PGM Physical Guest Memory Management
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Objectives:
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - Guest RAM over-commitment using memory ballooning,
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * zero pages and general page sharing.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - Moving or mirroring a VM onto a different physical machine.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * @subsection subsec_pgmPhys_Definitions Definitions
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * machinery assoicated with it.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * @subsection subsec_pgmPhys_AllocPage Allocating a page.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Initially we map *all* guest memory to the (per VM) zero page, which
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * means that none of the read functions will cause pages to be allocated.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Exception, access bit in page tables that have been shared. This must
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * be handled, but we must also make sure PGMGst*Modify doesn't make
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * unnecessary modifications.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Allocation points:
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - Replacing a zero page mapping at \#PF.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - Replacing a shared page mapping at \#PF.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - ROM registration (currently MMR3RomRegister).
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - VM restore (pgmR3Load).
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * For the first three it would make sense to keep a few pages handy
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * until we've reached the max memory commitment for the VM.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * For the ROM registration, we know exactly how many pages we need
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * and will request these from ring-0. For restore, we will save
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * the number of non-zero pages in the saved state and allocate
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * them up front. This would allow the ring-0 component to refuse
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * the request if the isn't sufficient memory available for VM use.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Btw. for both ROM and restore allocations we won't be requiring
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * zeroed pages as they are going to be filled instantly.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * @subsection subsec_pgmPhys_FreePage Freeing a page
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * There are a few points where a page can be freed:
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - After being replaced by the zero page.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - After being replaced by a shared page.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - After being ballooned by the guest additions.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - At reset.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * - At restore.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * When freeing one or more pages they will be returned to the ring-0
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * component and replaced by the zero page.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The reasoning for clearing out all the pages on reset is that it will
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * return us to the exact same state as on power on, and may thereby help
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * us reduce the memory load on the system. Further it might have a
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * On restore, as mention under the allocation topic, pages should be
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * freed / allocated depending on how many is actually required by the
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * new VM state. The simplest approach is to do like on reset, and free
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * all non-ROM pages and then allocate what we need.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * A measure to prevent some fragmentation, would be to let each allocation
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * chunk have some affinity towards the VM having allocated the most pages
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * from it. Also, try make sure to allocate from allocation chunks that
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * are almost full. Admittedly, both these measures might work counter to
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * our intentions and its probably not worth putting a lot of effort,
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * cpu time or memory into this.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @subsection subsec_pgmPhys_SharePage Sharing a page
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The basic idea is that there there will be a idle priority kernel
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * thread walking the non-shared VM pages hashing them and looking for
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * pages with the same checksum. If such pages are found, it will compare
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * them byte-by-byte to see if they actually are identical. If found to be
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * identical it will allocate a shared page, copy the content, check that
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * the page didn't change while doing this, and finally request both the
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * VMs to use the shared page instead. If the page is all zeros (special
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * checksum and byte-by-byte check) it will request the VM that owns it
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * to replace it with the zero page.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * To make this efficient, we will have to make sure not to try share a page
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * that will change its contents soon. This part requires the most work.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * A simple idea would be to request the VM to write monitor the page for
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * a while to make sure it isn't modified any time soon. Also, it may
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * make sense to skip pages that are being write monitored since this
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * information is readily available to the thread if it works on the
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * per-VM guest memory structures (presently called PGMRAMRANGE).
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The pages are organized in allocation chunks in ring-0, this is a necessity
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * if we wish to have an OS agnostic approach to this whole thing. (On Linux we
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * could easily work on a page-by-page basis if we liked. Whether this is possible
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * or efficient on NT I don't quite know.) Fragmentation within these chunks may
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * become a problem as part of the idea here is that we wish to return memory to
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * the host system.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * For instance, starting two VMs at the same time, they will both allocate the
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * guest memory on-demand and if permitted their page allocations will be
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * intermixed. Shut down one of the two VMs and it will be difficult to return
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * any memory to the host system because the page allocation for the two VMs are
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * mixed up in the same allocation chunks.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * To further complicate matters, when pages are freed because they have been
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * ballooned or become shared/zero the whole idea is that the page is supposed
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * to be reused by another VM or returned to the host system. This will cause
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * allocation chunks to contain pages belonging to different VMs and prevent
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * returning memory to the host when one of those VM shuts down.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The only way to really deal with this problem is to move pages. This can
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * either be done at VM shutdown and or by the idle priority worker thread
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * that will be responsible for finding sharable/zero pages. The mechanisms
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * involved for coercing a VM to move a page (or to do it for it) will be
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * the same as when telling it to share/zero a page.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * There's a difficult balance between keeping the per-page tracking structures
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * (global and guest page) easy to use and keeping them from eating too much
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * memory. We have limited virtual memory resources available when operating in
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * 32-bit kernel space (on 64-bit there'll it's quite a different story). The
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * tracking structures will be attemted designed such that we can deal with up
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @see pg_GMM
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Fixed info is the physical address of the page (HCPhys) and the page id
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Today we've restricting ourselves to 40(-12) bits because this is the current
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * restrictions of all AMD64 implementations (I think Barcelona will up this
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * to 48(-12) bits, not that it really matters) and I needed the bits for
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * decent range for the page id: 2^(28+12) = 1024TB.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * In additions to these, we'll have to keep maintaining the page flags as we
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * currently do. Although it wouldn't harm to optimize these quite a bit, like
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * for instance the ROM shouldn't depend on having a write handler installed
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * in order for it to become read-only. A RO/RW bit should be considered so
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * that the page syncing code doesn't have to mess about checking multiple
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * flag combinations (ROM || RW handler || write monitored) in order to
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * figure out how to setup a shadow PTE. But this of course, is second
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * priority at present. Current this requires 12 bits, but could probably
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * be optimized to ~8.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Then there's the 24 bits used to track which shadow page tables are
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * currently mapping a page for the purpose of speeding up physical
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * access handlers, and thereby the page pool cache. More bit for this
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * purpose wouldn't hurt IIRC.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Then there is a new bit in which we need to record what kind of page
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * this is, shared, zero, normal or write-monitored-normal. This'll
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * require 2 bits. One bit might be needed for indicating whether a
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * write monitored page has been written to. And yet another one or
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * two for tracking migration status. 3-4 bits total then.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Whatever is left will can be used to record the sharabilitiy of a
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * page. The page checksum will not be stored in the per-VM table as
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * the idle thread will not be permitted to do modifications to it.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * It will instead have to keep its own working set of potentially
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * shareable pages and their check sums and stuff.
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * For the present we'll keep the current packing of the
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * we'll have to change it to a struct with a total of 128-bits at
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * our disposal.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The initial layout will be like this:
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @verbatim
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync RTHCPHYS HCPhys; The current stuff.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync 63:40 Current shadow PT tracking stuff.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync 39:12 The physical page frame number.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync 11:0 The current flags.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync uint32_t u28PageId : 28; The page id.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync uint32_t u1Reserved : 1; Reserved for later.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync uint32_t u32Reserved; Reserved for later, mostly sharing stats.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync @endverbatim
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The final layout will be something like this:
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @verbatim
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync RTHCPHYS HCPhys; The current stuff.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync 63:48 High page id (12+).
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync 47:12 The physical page frame number.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync 11:0 Low page id.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync @endverbatim
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Cost wise, this means we'll double the cost for guest memory. There isn't anyway
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * around that I'm afraid. It means that the cost of dealing out 32GB of memory
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * A couple of cost examples for the total cost per-VM + kernel.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * 32-bit Windows and 32-bit linux:
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * 64-bit Windows and 64-bit linux:
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * UPDATE - 2007-09-27:
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Will need a ballooned flag/state too because we cannot
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * trust the guest 100% and reporting the same page as ballooned more
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * than once will put the GMM off balance.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @subsection subsec_pgmPhys_Serializing Serializing Access
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Initially, we'll try a simple scheme:
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * by the EMT thread of that VM while in the pgm critsect.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * - Other threads in the VM process that needs to make reliable use of
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * the per-VM RAM tracking structures will enter the critsect.
cf9045d402be1e8b7344a439eaefe2ca4c2b53d3vboxsync * - No process external thread or kernel thread will ever try enter
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * the pgm critical section, as that just won't work.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * - The idle thread (and similar threads) doesn't not need 100% reliable
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * data when performing it tasks as the EMT thread will be the one to
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * do the actual changes later anyway. So, as long as it only accesses
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * the main ram range, it can do so by somehow preventing the VM from
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * being destroyed while it works on it...
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * - The over-commitment management, including the allocating/freeing
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * chunks, is serialized by a ring-0 mutex lock (a fast one since the
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * more mundane mutex implementation is broken on Linux).
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * - A separeate mutex is protecting the set of allocation chunks so
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * that pages can be shared or/and freed up while some other VM is
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * allocating more chunks. This mutex can be take from under the other
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * one, but not the otherway around.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @subsection subsec_pgmPhys_Request VM Request interface
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * When in ring-0 it will become necessary to send requests to a VM so it can
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * for instance move a page while defragmenting during VM destroy. The idle
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * thread will make use of this interface to request VMs to setup shared
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * pages and to perform write monitoring of pages.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * I would propose an interface similar to the current VMReq interface, similar
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * in that it doesn't require locking and that the one sending the request may
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * wait for completion if it wishes to. This shouldn't be very difficult to
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The requests themselves are also pretty simple. They are basically:
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * -# Check that some precondition is still true.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * -# Do the update.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * -# Update all shadow page tables involved with the page.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The 3rd step is identical to what we're already doing when updating a
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @section sec_pgmPhys_MappingCaches Mapping Caches
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * In order to be able to map in and out memory and to be able to support
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * guest with more RAM than we've got virtual address space, we'll employing
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * and we'll create a similar one for ring-0 unless we decide to setup a dedicate
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * memory context for the HWACCM execution.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * We've considered implementing the ring-3 mapping cache page based but found
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * that this was bother some when one had to take into account TLBs+SMP and
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * portability (missing the necessary APIs on several platforms). There were
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * also some performance concerns with this approach which hadn't quite been
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * worked out.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Instead, we'll be mapping allocation chunks into the VM process. This simplifies
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * compared to the previous idea is that mapping or unmapping a 1MB chunk is more
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * costly than a single page, although how much more costly is uncertain. We'll
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * try address this by using a very big cache, preferably bigger than the actual
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * VM RAM size if possible. The current VM RAM sizes should give some idea for
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * 32-bit boxes, while on 64-bit we can probably get away with employing an
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * unlimited cache.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The cache have to parts, as already indicated, the ring-3 side and the
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * ring-0 side.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The ring-0 will be tied to the page allocator since it will operate on the
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * memory objects it contains. It will therefore require the first ring-0 mutex
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * discussed in @ref subsec_pgmPhys_Serializing. We
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * some double house keeping wrt to who has mapped what I think, since both
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * require anyone that desires to do changes to the mapping cache to do that
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * from within this critsect. Alternatively, we could employ a separate critsect
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * for serializing changes to the mapping cache as this would reduce potential
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * contention with other threads accessing mappings unrelated to the changes
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * that are in process. We can see about this later, contention will show
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * up in the statistics anyway, so it'll be simple to tell.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The organization of the ring-3 part will be very much like how the allocation
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * having to walk the tree all the time, we'll have a couple of lookaside entries
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * like in we do for I/O ports and MMIO in IOM.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The simplified flow of a PGMPhysRead/Write function:
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * -# Enter the PGM critsect.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * -# Lookup GCPhys in the ram ranges and get the Page ID.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * -# Calc the Allocation Chunk ID from the Page ID.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * -# Check the lookaside entries and then the AVL tree for the Chunk ID.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * If not found in cache:
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * -# Call ring-0 and request it to be mapped and supply
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * a chunk to be unmapped if the cache is maxed out already.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * -# Insert the new mapping into the AVL tree (id + R3 address).
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * -# Update the relevant lookaside entry and return the mapping address.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * -# Do the read/write according to monitoring flags and everything.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * -# Leave the critsect.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @section sec_pgmPhys_Fallback Fallback
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * API and thus require a fallback.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * will return to the ring-3 caller (and later ring-0) and asking it to seed
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * "SeededAllocPages" call to ring-0.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * all page sharing (zero page detection will continue). It will also force
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * all allocations to come from the VM which seeded the page. Both these
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * measures are taken to make sure that there will never be any need for
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * mapping anything into ring-3 - everything will be mapped already.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Whether we'll continue to use the current MM locked memory management
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * for this I don't quite know (I'd prefer not to and just ditch that all
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * togther), we'll see what's simplest to do.
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * @section sec_pgmPhys_Changes Changes
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Breakdown of the changes involved?
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync/*******************************************************************************
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync* Header Files *
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync*******************************************************************************/
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync/*******************************************************************************
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync* Defined Constants And Macros *
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync*******************************************************************************/
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync/** Saved state data unit version for 2.5.x and later. */
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync/** Saved state data unit version for 2.2.0. */
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync/** Saved state data unit version. */
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync/*******************************************************************************
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync* Internal Functions *
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync*******************************************************************************/
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync/** @todo Convert the first two commands to 'info' items. */
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsyncstatic DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
d809f5627a423664bd420048579ee741164d13f5vboxsyncstatic DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync/*******************************************************************************
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync* Global Variables *
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync*******************************************************************************/
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
d809f5627a423664bd420048579ee741164d13f5vboxsync /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync { 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync/** Command descriptors. */
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync /* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync { "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync { "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync { "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync { "pgmerror", 0, 1, &g_aPgmErrorArgs[0],1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync { "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0],1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync { "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync { "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Shadow - 32-bit mode
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync/* Guest - real mode */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/* Guest - protected mode */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
1c434bf12564eb5a885b3f7e230b7638955004cevboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync/* Guest - 32-bit mode */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Shadow - PAE mode
cf9045d402be1e8b7344a439eaefe2ca4c2b53d3vboxsync#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
cf9045d402be1e8b7344a439eaefe2ca4c2b53d3vboxsync#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
cf9045d402be1e8b7344a439eaefe2ca4c2b53d3vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
cf9045d402be1e8b7344a439eaefe2ca4c2b53d3vboxsync/* Guest - real mode */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
1c434bf12564eb5a885b3f7e230b7638955004cevboxsync/* Guest - protected mode */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
cf9045d402be1e8b7344a439eaefe2ca4c2b53d3vboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
cf9045d402be1e8b7344a439eaefe2ca4c2b53d3vboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
4eb5a468e1ff750304441e03d1b2311ce049956avboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
1c434bf12564eb5a885b3f7e230b7638955004cevboxsync/* Guest - 32-bit mode */
1c434bf12564eb5a885b3f7e230b7638955004cevboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1c434bf12564eb5a885b3f7e230b7638955004cevboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1c434bf12564eb5a885b3f7e230b7638955004cevboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
1c434bf12564eb5a885b3f7e230b7638955004cevboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
1c434bf12564eb5a885b3f7e230b7638955004cevboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
1c434bf12564eb5a885b3f7e230b7638955004cevboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync/* Guest - PAE mode */
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Shadow - AMD64 mode
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync/* Guest - AMD64 mode */
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#endif /* VBOX_WITH_64_BITS_GUESTS */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * Shadow - Nested paging mode
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync/* Guest - real mode */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync/* Guest - protected mode */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
cf9045d402be1e8b7344a439eaefe2ca4c2b53d3vboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync/* Guest - 32-bit mode */
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync/* Guest - PAE mode */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync/* Guest - AMD64 mode */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
cf9045d402be1e8b7344a439eaefe2ca4c2b53d3vboxsync# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#endif /* VBOX_WITH_64_BITS_GUESTS */
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync * Shadow - EPT
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync/* Guest - real mode */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
cf9045d402be1e8b7344a439eaefe2ca4c2b53d3vboxsync/* Guest - protected mode */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync/* Guest - 32-bit mode */
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync/* Guest - PAE mode */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync/* Guest - AMD64 mode */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
7bc0784812dcf63751c5eebfdd1c5d24ac26b389vboxsync# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#endif /* VBOX_WITH_64_BITS_GUESTS */
int rc;
#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
cbRam = 0;
cbRam = 0;
return rc;
#ifdef VBOX_STRICT
return rc;
rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
#ifdef VBOX_WITH_DEBUGGER
static bool s_fRegisteredCmds = false;
if (!s_fRegisteredCmds)
s_fRegisteredCmds = true;
return VINF_SUCCESS;
return rc;
return VINF_SUCCESS;
return rc;
return VERR_NO_PAGE_MEMORY;
AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A | PGM_PLXFLAGS_PERMANENT
pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A | PGM_PLXFLAGS_PERMANENT
case SUPPAGINGMODE_32_BIT:
case SUPPAGINGMODE_PAE:
case SUPPAGINGMODE_PAE_GLOBAL:
case SUPPAGINGMODE_PAE_NX:
case SUPPAGINGMODE_AMD64:
case SUPPAGINGMODE_AMD64_NX:
#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
return VINF_SUCCESS;
return rc;
int rc;
STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_OCCURENCES, "The number of handy pages (not included in cAllPages).");
STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
#ifdef VBOX_WITH_STATISTICS
# define PGM_REG_COUNTER(a, b, c) \
# define PGM_REG_PROFILE(a, b, c) \
rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
#define PGM_REG_COUNTER(a, b, c) \
rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
#define PGM_REG_PROFILE(a, b, c) \
rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
PGM_REG_COUNTER(&pPGM->cGuestModeChanges, "/PGM/CPU%d/cGuestModeChanges", "Number of guest mode changes.");
#ifdef VBOX_WITH_STATISTICS
STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
PGM_REG_COUNTER(&pPGM->StatR0DynMapMigrateInvlPg, "/PGM/CPU%d/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
PGM_REG_PROFILE(&pPGM->StatR0DynMapGCPageInl, "/PGM/CPU%d/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPageInl, "/PGM/CPU%d/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlHits, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapSetOptimize, "/PGM/CPU%d/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchFlushes, "/PGM/CPU%d/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchHits, "/PGM/CPU%d/R0/DynMapPage/SetSearchHits", "Set search hits.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchMisses, "/PGM/CPU%d/R0/DynMapPage/SetSearchMisses", "Set search misses.");
PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPage, "/PGM/CPU%d/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
PGM_REG_COUNTER(&pPGM->StatR0DynMapPageInvlPg, "/PGM/CPU%d/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlow, "/PGM/CPU%d/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%d/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%d/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
//PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLostHits, "/PGM/CPU%d/R0/DynMapPage/SlowLostHits", "Lost hits.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapSubsets, "/PGM/CPU%d/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapPopFlushes, "/PGM/CPU%d/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0e, "/PGM/CPU%d/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%d/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeSyncPT, "/PGM/CPU%d/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeMapping, "/PGM/CPU%d/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeHandlers, "/PGM/CPU%d/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2CSAM, "/PGM/CPU%d/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%d/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%d/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2Misc, "/PGM/CPU%d/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2SyncPT, "/PGM/CPU%d/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eConflicts, "/PGM/CPU%d/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersMapping, "/PGM/CPU%d/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersPhysical, "/PGM/CPU%d/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtual, "/PGM/CPU%d/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%d/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersInvalid, "/PGM/CPU%d/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSReserved, "/PGM/CPU%d/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVReserved, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPF, "/PGM/CPU%d/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFUnh, "/PGM/CPU%d/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFMapping, "/PGM/CPU%d/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%d/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulToR3, "/PGM/CPU%d/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteHandled, "/PGM/CPU%d/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%d/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteConflict, "/PGM/CPU%d/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteHandled, "/PGM/CPU%d/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteUnhandled, "/PGM/CPU%d/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
PGM_REG_PROFILE(&pPGM->StatRZSyncCR3, "/PGM/CPU%d/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
PGM_REG_PROFILE(&pPGM->StatRZSyncCR3Handlers, "/PGM/CPU%d/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3Global, "/PGM/CPU%d/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3NotGlobal, "/PGM/CPU%d/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstCacheHit, "/PGM/CPU%d/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreed, "/PGM/CPU%d/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%d/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstNotPresent, "/PGM/CPU%d/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
PGM_REG_COUNTER(&pPGM->StatRZSyncPTFailed, "/PGM/CPU%d/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDNAs, "/PGM/CPU%d/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDOutOfSync, "/PGM/CPU%d/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
PGM_REG_COUNTER(&pPGM->StatRZAccessedPage, "/PGM/CPU%d/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
PGM_REG_PROFILE(&pPGM->StatRZDirtyBitTracking, "/PGM/CPU%d/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
PGM_REG_COUNTER(&pPGM->StatRZDirtyPage, "/PGM/CPU%d/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatRZDirtyPageBig, "/PGM/CPU%d/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatRZDirtyPageSkipped, "/PGM/CPU%d/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
PGM_REG_COUNTER(&pPGM->StatRZDirtyPageTrap, "/PGM/CPU%d/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatRZDirtiedPage, "/PGM/CPU%d/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
PGM_REG_COUNTER(&pPGM->StatRZDirtyTrackRealPF, "/PGM/CPU%d/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatRZPageAlreadyDirty, "/PGM/CPU%d/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
PGM_REG_PROFILE(&pPGM->StatRZInvalidatePage, "/PGM/CPU%d/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4KBPages, "/PGM/CPU%d/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPages, "/PGM/CPU%d/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%d/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDMappings, "/PGM/CPU%d/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNAs, "/PGM/CPU%d/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNPs, "/PGM/CPU%d/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%d/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePageSkipped, "/PGM/CPU%d/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%d/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncUser, "/PGM/CPU%d/RZ/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
PGM_REG_PROFILE(&pPGM->StatRZFlushTLB, "/PGM/CPU%d/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3, "/PGM/CPU%d/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3Global, "/PGM/CPU%d/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3, "/PGM/CPU%d/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3Global, "/PGM/CPU%d/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
PGM_REG_PROFILE(&pPGM->StatRZGstModifyPage, "/PGM/CPU%d/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
PGM_REG_PROFILE(&pPGM->StatR3SyncCR3, "/PGM/CPU%d/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
PGM_REG_PROFILE(&pPGM->StatR3SyncCR3Handlers, "/PGM/CPU%d/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3Global, "/PGM/CPU%d/R3/SyncCR3/Global", "The number of global CR3 syncs.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3NotGlobal, "/PGM/CPU%d/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstCacheHit, "/PGM/CPU%d/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreed, "/PGM/CPU%d/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%d/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstNotPresent, "/PGM/CPU%d/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
PGM_REG_COUNTER(&pPGM->StatR3SyncPTFailed, "/PGM/CPU%d/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDNAs, "/PGM/CPU%d/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDOutOfSync, "/PGM/CPU%d/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
PGM_REG_COUNTER(&pPGM->StatR3AccessedPage, "/PGM/CPU%d/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
PGM_REG_PROFILE(&pPGM->StatR3DirtyBitTracking, "/PGM/CPU%d/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
PGM_REG_COUNTER(&pPGM->StatR3DirtyPage, "/PGM/CPU%d/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatR3DirtyPageBig, "/PGM/CPU%d/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatR3DirtyPageSkipped, "/PGM/CPU%d/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
PGM_REG_COUNTER(&pPGM->StatR3DirtyPageTrap, "/PGM/CPU%d/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatR3DirtiedPage, "/PGM/CPU%d/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
PGM_REG_COUNTER(&pPGM->StatR3DirtyTrackRealPF, "/PGM/CPU%d/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatR3PageAlreadyDirty, "/PGM/CPU%d/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
PGM_REG_PROFILE(&pPGM->StatR3InvalidatePage, "/PGM/CPU%d/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4KBPages, "/PGM/CPU%d/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPages, "/PGM/CPU%d/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%d/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDMappings, "/PGM/CPU%d/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNAs, "/PGM/CPU%d/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNPs, "/PGM/CPU%d/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%d/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePageSkipped, "/PGM/CPU%d/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%d/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncUser, "/PGM/CPU%d/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
PGM_REG_PROFILE(&pPGM->StatR3FlushTLB, "/PGM/CPU%d/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3, "/PGM/CPU%d/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3Global, "/PGM/CPU%d/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3, "/PGM/CPU%d/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3Global, "/PGM/CPU%d/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
PGM_REG_PROFILE(&pPGM->StatR3GstModifyPage, "/PGM/CPU%d/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
int rc;
&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
return rc;
int rc;
pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
return rc;
LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
int rc;
#ifdef DEBUG
#ifdef VBOX_STRICT
static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
return NULL;
static int pgmR3SavePage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
int rc;
void const *pvPage;
AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
return rc;
static int pgmR3SaveShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
return rc;
bool fMappingsFixed;
bool fA20Enabled;
} PGMOLD;
int rc;
static int pgmR3LoadPageZero(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
return VERR_SSM_UNEXPECTED_DATA;
return VERR_SSM_UNEXPECTED_DATA;
return VINF_SUCCESS;
static int pgmR3LoadPageBits(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
int rc;
void *pvPage;
return rc;
static int pgmR3LoadPage(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
rc);
return VINF_SUCCESS;
static int pgmR3LoadShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
return rc;
int rc;
return rc;
return rc;
uint32_t i = 0;
return rc;
if (u32Sep == ~0U)
if (u32Sep != i)
return rc;
return rc;
return rc;
if (u32Sep == ~0U)
if (u32Sep != i)
return rc;
return rc;
|| ( cchDesc
|| !fHaveBits)
AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
if ( !fHaveBits
AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
if (fPresent)
AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
return rc;
int rc;
AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
/* Restore pVM->pgm.s.GCPhysCR3. */
return rc;
if (pszArgs)
fGuest = true;
fShadow = true;
fHost = true;
if (fGuest)
if (fShadow)
pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
if (fHost)
const char *psz;
pVM,
Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
iPD,
iPD,
return rc;
switch (pgmMode)
case PGMMODE_PAE:
case PGMMODE_AMD64:
int rc;
pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
#ifdef VBOX_WITH_64_BITS_GUESTS
#ifdef VBOX_WITH_64_BITS_GUESTS
case SUPPAGINGMODE_32_BIT:
# ifdef VBOX_WITH_64_BITS_GUESTS
case SUPPAGINGMODE_PAE:
case SUPPAGINGMODE_PAE_NX:
case SUPPAGINGMODE_PAE_GLOBAL:
# ifdef VBOX_WITH_64_BITS_GUESTS
case SUPPAGINGMODE_AMD64:
case SUPPAGINGMODE_AMD64_NX:
# ifdef VBOX_WITH_64_BITS_GUESTS
AssertFailed();
#ifdef VBOX_WITH_64_BITS_GUESTS
return VINF_SUCCESS;
#ifdef VBOX_STRICT
#ifdef VBOX_STRICT
#ifdef VBOX_STRICT
static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
switch (enmGuestMode)
case PGMMODE_REAL:
case PGMMODE_PROTECTED:
switch (enmHostMode)
case SUPPAGINGMODE_32_BIT:
case SUPPAGINGMODE_PAE:
case SUPPAGINGMODE_PAE_NX:
case SUPPAGINGMODE_PAE_GLOBAL:
#ifdef DEBUG_bird
case SUPPAGINGMODE_AMD64:
case SUPPAGINGMODE_AMD64_NX:
#ifdef DEBUG_bird
case PGMMODE_32_BIT:
switch (enmHostMode)
case SUPPAGINGMODE_32_BIT:
case SUPPAGINGMODE_PAE:
case SUPPAGINGMODE_PAE_NX:
case SUPPAGINGMODE_PAE_GLOBAL:
#ifdef DEBUG_bird
case SUPPAGINGMODE_AMD64:
case SUPPAGINGMODE_AMD64_NX:
#ifdef DEBUG_bird
case PGMMODE_PAE:
switch (enmHostMode)
case SUPPAGINGMODE_32_BIT:
case SUPPAGINGMODE_PAE:
case SUPPAGINGMODE_PAE_NX:
case SUPPAGINGMODE_PAE_GLOBAL:
case SUPPAGINGMODE_AMD64:
case SUPPAGINGMODE_AMD64_NX:
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX:
switch (enmHostMode)
case SUPPAGINGMODE_32_BIT:
case SUPPAGINGMODE_PAE:
case SUPPAGINGMODE_PAE_NX:
case SUPPAGINGMODE_PAE_GLOBAL:
case SUPPAGINGMODE_AMD64:
case SUPPAGINGMODE_AMD64_NX:
return PGMMODE_INVALID;
return enmShadowMode;
Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
return rc;
LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
return rc;
LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
return rc;
int rc;
switch (enmShadowMode)
case PGMMODE_32_BIT:
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX:
case PGMMODE_NESTED:
case PGMMODE_EPT:
case PGMMODE_REAL:
case PGMMODE_PROTECTED:
return VERR_INTERNAL_ERROR;
return rc;
switch (enmGuestMode)
case PGMMODE_REAL:
case PGMMODE_32_BIT:
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
case PGMMODE_NESTED:
case PGMMODE_EPT:
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX:
default: AssertFailed(); break;
case PGMMODE_PROTECTED:
case PGMMODE_32_BIT:
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
case PGMMODE_NESTED:
case PGMMODE_EPT:
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX:
default: AssertFailed(); break;
case PGMMODE_32_BIT:
case PGMMODE_32_BIT:
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
case PGMMODE_NESTED:
case PGMMODE_EPT:
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX:
default: AssertFailed(); break;
case PGMMODE_PAE_NX:
case PGMMODE_PAE:
N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
case PGMMODE_NESTED:
case PGMMODE_EPT:
case PGMMODE_32_BIT:
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX:
default: AssertFailed(); break;
#ifdef VBOX_WITH_64_BITS_GUESTS
case PGMMODE_AMD64_NX:
case PGMMODE_AMD64:
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX:
case PGMMODE_NESTED:
case PGMMODE_EPT:
case PGMMODE_32_BIT:
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
default: AssertFailed(); break;
return rc;
/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
return rc;
("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
return rc;
static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
return VINF_SUCCESS;
static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
if (!pPD)
pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
return VERR_INVALID_PARAMETER;
pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
if (pPT)
return rc;
static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
if (!pPDPT)
pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
return VERR_INVALID_PARAMETER;
if (fLongMode)
i << X86_PDPT_SHIFT,
int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
return rc;
static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
if (!pPML4)
return VERR_INVALID_PARAMETER;
uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) | (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
return rc;
return VINF_SUCCESS;
int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
if (!pPD)
pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
return VERR_INVALID_PARAMETER;
pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
if (pPT)
pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
return rc;
Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
return VINF_SUCCESS;
bool fLongMode = false;
return VERR_INVALID_PARAMETER;
if (pPT)
return rc;
VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
if (!pHlp)
if (!cMaxDepth)
return VINF_SUCCESS;
if (fLongMode)
return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
#ifdef VBOX_WITH_DEBUGGER
static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
if (!pVM)
return rc;
return VINF_SUCCESS;
static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
if (!pVM)
int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
return rc;
return rc;
return VINF_SUCCESS;
static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
if (!pVM)
if (!cArgs)
return VINF_SUCCESS;
static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
if (!pVM)
return rc;
return VINF_SUCCESS;
#ifdef VBOX_STRICT
static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
if (!pVM)
return rc;
return VINF_SUCCESS;
static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
if (!pVM)
typedef struct PGMCHECKINTARGS
static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
|| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
|| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
|| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
|| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD),
pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
int cErrors = 0;
cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);